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mmc: core: Use delayed work in clock gating framework
Current clock gating framework disables the MCI clock as soon as the request is completed and enables it when a request arrives. This aggressive clock gating framework, when enabled, cause following issues: When there are back-to-back requests from the Queue layer, we unnecessarily end up disabling and enabling the clocks between these requests since 8MCLK clock cycles is a very short duration compared to the time delay between back to back requests reaching the MMC layer. This overhead can effect the overall performance depending on how long the clock enable and disable calls take which is platform dependent. For example on some platforms we can have clock control not on the local processor, but on a different subsystem and the time taken to perform the clock enable/disable can add significant overhead. Also if the host controller driver decides to disable the host clock too when mmc_set_ios function is called with ios.clock=0, it adds additional delay and it is highly possible that the next request had already arrived and unnecessarily blocked in enabling the clocks. This is seen frequently when the processor is executing at high speeds and in multi-core platforms thus reduces the overall throughput compared to if clock gating is disabled. Fix this by delaying turning off the clocks by posting request on delayed workqueue. Also cancel the unscheduled pending work, if any, when there is access to card. sysfs entry is provided to tune the delay as needed, default value set to 200ms. Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
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@ -64,3 +64,13 @@ Note on Erase Size and Preferred Erase Size:
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size specified by the card.
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"preferred_erase_size" is in bytes.
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SD/MMC/SDIO Clock Gating Attribute
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==================================
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Read and write access is provided to following attribute.
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This attribute appears only if CONFIG_MMC_CLKGATE is enabled.
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clkgate_delay Tune the clock gating delay with desired value in milli seconds.
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echo <desired delay> > /sys/class/mmc_host/mmcX/clkgate_delay
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@ -54,6 +54,31 @@ static DEFINE_IDR(mmc_host_idr);
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static DEFINE_SPINLOCK(mmc_host_lock);
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#ifdef CONFIG_MMC_CLKGATE
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static ssize_t clkgate_delay_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct mmc_host *host = cls_dev_to_mmc_host(dev);
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return snprintf(buf, PAGE_SIZE, "%lu millisecs\n",
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host->clkgate_delay);
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}
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static ssize_t clkgate_delay_store(struct device *dev,
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struct device_attribute *attr, const char *buf, size_t count)
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{
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struct mmc_host *host = cls_dev_to_mmc_host(dev);
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unsigned long flags, value;
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if (kstrtoul(buf, 0, &value))
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return -EINVAL;
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spin_lock_irqsave(&host->clk_lock, flags);
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host->clkgate_delay = value;
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spin_unlock_irqrestore(&host->clk_lock, flags);
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pr_info("%s: clock gate delay set to %lu ms\n",
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mmc_hostname(host), value);
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return count;
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}
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/*
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* Enabling clock gating will make the core call out to the host
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@ -114,7 +139,7 @@ static void mmc_host_clk_gate_delayed(struct mmc_host *host)
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static void mmc_host_clk_gate_work(struct work_struct *work)
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{
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struct mmc_host *host = container_of(work, struct mmc_host,
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clk_gate_work);
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clk_gate_work.work);
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mmc_host_clk_gate_delayed(host);
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}
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@ -131,6 +156,8 @@ void mmc_host_clk_hold(struct mmc_host *host)
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{
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unsigned long flags;
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/* cancel any clock gating work scheduled by mmc_host_clk_release() */
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cancel_delayed_work_sync(&host->clk_gate_work);
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mutex_lock(&host->clk_gate_mutex);
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spin_lock_irqsave(&host->clk_lock, flags);
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if (host->clk_gated) {
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@ -180,7 +207,8 @@ void mmc_host_clk_release(struct mmc_host *host)
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host->clk_requests--;
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if (mmc_host_may_gate_card(host->card) &&
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!host->clk_requests)
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queue_work(system_nrt_wq, &host->clk_gate_work);
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queue_delayed_work(system_nrt_wq, &host->clk_gate_work,
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msecs_to_jiffies(host->clkgate_delay));
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spin_unlock_irqrestore(&host->clk_lock, flags);
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}
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@ -213,8 +241,13 @@ static inline void mmc_host_clk_init(struct mmc_host *host)
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host->clk_requests = 0;
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/* Hold MCI clock for 8 cycles by default */
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host->clk_delay = 8;
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/*
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* Default clock gating delay is 200ms.
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* This value can be tuned by writing into sysfs entry.
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*/
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host->clkgate_delay = 200;
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host->clk_gated = false;
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INIT_WORK(&host->clk_gate_work, mmc_host_clk_gate_work);
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INIT_DELAYED_WORK(&host->clk_gate_work, mmc_host_clk_gate_work);
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spin_lock_init(&host->clk_lock);
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mutex_init(&host->clk_gate_mutex);
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}
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@ -229,7 +262,7 @@ static inline void mmc_host_clk_exit(struct mmc_host *host)
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* Wait for any outstanding gate and then make sure we're
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* ungated before exiting.
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*/
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if (cancel_work_sync(&host->clk_gate_work))
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if (cancel_delayed_work_sync(&host->clk_gate_work))
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mmc_host_clk_gate_delayed(host);
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if (host->clk_gated)
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mmc_host_clk_hold(host);
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@ -237,6 +270,17 @@ static inline void mmc_host_clk_exit(struct mmc_host *host)
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WARN_ON(host->clk_requests > 1);
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}
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static inline void mmc_host_clk_sysfs_init(struct mmc_host *host)
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{
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host->clkgate_delay_attr.show = clkgate_delay_show;
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host->clkgate_delay_attr.store = clkgate_delay_store;
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sysfs_attr_init(&host->clkgate_delay_attr.attr);
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host->clkgate_delay_attr.attr.name = "clkgate_delay";
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host->clkgate_delay_attr.attr.mode = S_IRUGO | S_IWUSR;
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if (device_create_file(&host->class_dev, &host->clkgate_delay_attr))
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pr_err("%s: Failed to create clkgate_delay sysfs entry\n",
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mmc_hostname(host));
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}
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#else
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static inline void mmc_host_clk_init(struct mmc_host *host)
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@ -247,6 +291,10 @@ static inline void mmc_host_clk_exit(struct mmc_host *host)
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{
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}
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static inline void mmc_host_clk_sysfs_init(struct mmc_host *host)
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{
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}
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#endif
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/**
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@ -335,6 +383,7 @@ int mmc_add_host(struct mmc_host *host)
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#ifdef CONFIG_DEBUG_FS
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mmc_add_host_debugfs(host);
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#endif
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mmc_host_clk_sysfs_init(host);
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mmc_start_host(host);
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register_pm_notifier(&host->pm_notify);
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@ -253,10 +253,12 @@ struct mmc_host {
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int clk_requests; /* internal reference counter */
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unsigned int clk_delay; /* number of MCI clk hold cycles */
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bool clk_gated; /* clock gated */
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struct work_struct clk_gate_work; /* delayed clock gate */
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struct delayed_work clk_gate_work; /* delayed clock gate */
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unsigned int clk_old; /* old clock value cache */
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spinlock_t clk_lock; /* lock for clk fields */
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struct mutex clk_gate_mutex; /* mutex for clock gating */
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struct device_attribute clkgate_delay_attr;
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unsigned long clkgate_delay;
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#endif
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/* host specific block data */
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