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atl1c: restore max-read-request-size in Device Conrol Register
in some platforms, we found the max-read-request-size in Device Control Register is set to 0 by (BIOS?) during bootup, this will cause the performance(throughput) very bad. Restore it to a min-value. register definition of REG_DEVICE_CTRL is removed, using kernel API to access it as it's a standard pcie register. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -54,11 +54,7 @@ int atl1c_phy_power_saving(struct atl1c_hw *hw);
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#define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7
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#define DEVICE_CAP_MAX_PAYLOAD_SHIFT 0
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#define REG_DEVICE_CTRL 0x60
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#define DEVICE_CTRL_MAX_PAYLOAD_MASK 0x7
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#define DEVICE_CTRL_MAX_PAYLOAD_SHIFT 5
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#define DEVICE_CTRL_MAX_RREQ_SZ_MASK 0x7
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#define DEVICE_CTRL_MAX_RREQ_SZ_SHIFT 12
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#define DEVICE_CTRL_MAXRRS_MIN 2
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#define REG_LINK_CTRL 0x68
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#define LINK_CTRL_L0S_EN 0x01
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@ -1045,19 +1045,23 @@ static void atl1c_configure_des_ring(struct atl1c_adapter *adapter)
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static void atl1c_configure_tx(struct atl1c_adapter *adapter)
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{
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struct atl1c_hw *hw = &adapter->hw;
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u32 dev_ctrl_data;
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u32 max_pay_load;
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int max_pay_load;
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u16 tx_offload_thresh;
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u32 txq_ctrl_data;
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tx_offload_thresh = MAX_TX_OFFLOAD_THRESH;
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AT_WRITE_REG(hw, REG_TX_TSO_OFFLOAD_THRESH,
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(tx_offload_thresh >> 3) & TX_TSO_OFFLOAD_THRESH_MASK);
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AT_READ_REG(hw, REG_DEVICE_CTRL, &dev_ctrl_data);
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max_pay_load = (dev_ctrl_data >> DEVICE_CTRL_MAX_RREQ_SZ_SHIFT) &
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DEVICE_CTRL_MAX_RREQ_SZ_MASK;
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max_pay_load = pcie_get_readrq(adapter->pdev) >> 8;
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hw->dmar_block = min_t(u32, max_pay_load, hw->dmar_block);
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/*
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* if BIOS had changed the dam-read-max-length to an invalid value,
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* restore it to default value
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*/
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if (hw->dmar_block < DEVICE_CTRL_MAXRRS_MIN) {
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pcie_set_readrq(adapter->pdev, 128 << DEVICE_CTRL_MAXRRS_MIN);
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hw->dmar_block = DEVICE_CTRL_MAXRRS_MIN;
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}
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txq_ctrl_data =
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hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2 ?
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L2CB_TXQ_CFGV : L1C_TXQ_CFGV;
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