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MIPS: Octeon: Improve interrupt handling.
The main change is to change most of the IRQs from handle_percpu_irq to handle_fasteoi_irq. This necessitates extracting all the .ack code to common functions that are not exposed to the irq core. The affinity code now acts more sanely, by doing round-robin distribution instead of broadcasting. Because of the change to handle_fasteoi_irq and affinity, some of the IRQs had to be split into separate groups with their own struct irq_chip to prevent undefined operations on specific IRQ lines. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1485/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
David Daney
Ralf Baechle
parent
a894f14d7e
commit
5aae1fd4d4
@ -3,7 +3,7 @@
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2004-2008 Cavium Networks
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* Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
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*/
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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@ -39,14 +39,14 @@ static void octeon_irq_core_ack(unsigned int irq)
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static void octeon_irq_core_eoi(unsigned int irq)
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{
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struct irq_desc *desc = irq_desc + irq;
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struct irq_desc *desc = irq_to_desc(irq);
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unsigned int bit = irq - OCTEON_IRQ_SW0;
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/*
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* If an IRQ is being processed while we are disabling it the
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* handler will attempt to unmask the interrupt after it has
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* been disabled.
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*/
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if (desc->status & IRQ_DISABLED)
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if ((unlikely(desc->status & IRQ_DISABLED)))
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return;
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/*
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* We don't need to disable IRQs to make these atomic since
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@ -104,6 +104,29 @@ static struct irq_chip octeon_irq_chip_core = {
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static void octeon_irq_ciu0_ack(unsigned int irq)
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{
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switch (irq) {
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case OCTEON_IRQ_GMX_DRP0:
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case OCTEON_IRQ_GMX_DRP1:
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case OCTEON_IRQ_IPD_DRP:
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case OCTEON_IRQ_KEY_ZERO:
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case OCTEON_IRQ_TIMER0:
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case OCTEON_IRQ_TIMER1:
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case OCTEON_IRQ_TIMER2:
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case OCTEON_IRQ_TIMER3:
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{
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int index = cvmx_get_core_num() * 2;
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u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
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/*
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* CIU timer type interrupts must be acknoleged by
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* writing a '1' bit to their sum0 bit.
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*/
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cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
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break;
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}
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default:
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break;
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}
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/*
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* In order to avoid any locking accessing the CIU, we
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* acknowledge CIU interrupts by disabling all of them. This
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@ -128,7 +151,53 @@ static void octeon_irq_ciu0_eoi(unsigned int irq)
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set_c0_status(0x100 << 2);
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}
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static int next_coreid_for_irq(struct irq_desc *desc)
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{
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#ifdef CONFIG_SMP
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int coreid;
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int weight = cpumask_weight(desc->affinity);
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if (weight > 1) {
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int cpu = smp_processor_id();
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for (;;) {
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cpu = cpumask_next(cpu, desc->affinity);
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if (cpu >= nr_cpu_ids) {
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cpu = -1;
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continue;
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} else if (cpumask_test_cpu(cpu, cpu_online_mask)) {
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break;
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}
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}
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coreid = octeon_coreid_for_cpu(cpu);
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} else if (weight == 1) {
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coreid = octeon_coreid_for_cpu(cpumask_first(desc->affinity));
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} else {
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coreid = cvmx_get_core_num();
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}
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return coreid;
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#else
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return cvmx_get_core_num();
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#endif
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}
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static void octeon_irq_ciu0_enable(unsigned int irq)
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{
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struct irq_desc *desc = irq_to_desc(irq);
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int coreid = next_coreid_for_irq(desc);
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unsigned long flags;
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uint64_t en0;
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int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
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raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
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en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
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en0 |= 1ull << bit;
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cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
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cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
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raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
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}
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static void octeon_irq_ciu0_enable_mbox(unsigned int irq)
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{
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int coreid = cvmx_get_core_num();
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unsigned long flags;
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@ -165,14 +234,31 @@ static void octeon_irq_ciu0_disable(unsigned int irq)
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}
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/*
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* Enable the irq on the current core for chips that have the EN*_W1{S,C}
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* registers.
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* Enable the irq on the next core in the affinity set for chips that
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* have the EN*_W1{S,C} registers.
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*/
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static void octeon_irq_ciu0_enable_v2(unsigned int irq)
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{
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int index = cvmx_get_core_num() * 2;
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int index;
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u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
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struct irq_desc *desc = irq_to_desc(irq);
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if ((desc->status & IRQ_DISABLED) == 0) {
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index = next_coreid_for_irq(desc) * 2;
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cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
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}
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}
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/*
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* Enable the irq on the current CPU for chips that
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* have the EN*_W1{S,C} registers.
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*/
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static void octeon_irq_ciu0_enable_mbox_v2(unsigned int irq)
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{
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int index;
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u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
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index = cvmx_get_core_num() * 2;
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cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
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}
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@ -185,43 +271,39 @@ static void octeon_irq_ciu0_ack_v2(unsigned int irq)
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int index = cvmx_get_core_num() * 2;
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u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
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cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
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}
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/*
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* CIU timer type interrupts must be acknoleged by writing a '1' bit
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* to their sum0 bit.
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switch (irq) {
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case OCTEON_IRQ_GMX_DRP0:
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case OCTEON_IRQ_GMX_DRP1:
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case OCTEON_IRQ_IPD_DRP:
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case OCTEON_IRQ_KEY_ZERO:
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case OCTEON_IRQ_TIMER0:
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case OCTEON_IRQ_TIMER1:
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case OCTEON_IRQ_TIMER2:
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case OCTEON_IRQ_TIMER3:
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/*
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* CIU timer type interrupts must be acknoleged by
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* writing a '1' bit to their sum0 bit.
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*/
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static void octeon_irq_ciu0_timer_ack(unsigned int irq)
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{
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int index = cvmx_get_core_num() * 2;
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uint64_t mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
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cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
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}
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break;
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default:
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break;
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}
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static void octeon_irq_ciu0_timer_ack_v1(unsigned int irq)
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{
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octeon_irq_ciu0_timer_ack(irq);
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octeon_irq_ciu0_ack(irq);
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}
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static void octeon_irq_ciu0_timer_ack_v2(unsigned int irq)
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{
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octeon_irq_ciu0_timer_ack(irq);
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octeon_irq_ciu0_ack_v2(irq);
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cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
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}
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/*
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* Enable the irq on the current core for chips that have the EN*_W1{S,C}
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* registers.
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*/
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static void octeon_irq_ciu0_eoi_v2(unsigned int irq)
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static void octeon_irq_ciu0_eoi_mbox_v2(unsigned int irq)
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{
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struct irq_desc *desc = irq_desc + irq;
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struct irq_desc *desc = irq_to_desc(irq);
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int index = cvmx_get_core_num() * 2;
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u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
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if ((desc->status & IRQ_DISABLED) == 0)
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if (likely((desc->status & IRQ_DISABLED) == 0))
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cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
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}
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@ -244,18 +326,30 @@ static void octeon_irq_ciu0_disable_all_v2(unsigned int irq)
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static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest)
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{
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int cpu;
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struct irq_desc *desc = irq_to_desc(irq);
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int enable_one = (desc->status & IRQ_DISABLED) == 0;
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unsigned long flags;
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int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
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/*
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* For non-v2 CIU, we will allow only single CPU affinity.
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* This removes the need to do locking in the .ack/.eoi
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* functions.
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*/
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if (cpumask_weight(dest) != 1)
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return -EINVAL;
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raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
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for_each_online_cpu(cpu) {
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int coreid = octeon_coreid_for_cpu(cpu);
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uint64_t en0 =
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cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
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if (cpumask_test_cpu(cpu, dest))
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if (cpumask_test_cpu(cpu, dest) && enable_one) {
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enable_one = 0;
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en0 |= 1ull << bit;
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else
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} else {
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en0 &= ~(1ull << bit);
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}
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cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
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}
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/*
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@ -277,14 +371,19 @@ static int octeon_irq_ciu0_set_affinity_v2(unsigned int irq,
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{
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int cpu;
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int index;
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struct irq_desc *desc = irq_to_desc(irq);
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int enable_one = (desc->status & IRQ_DISABLED) == 0;
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u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
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for_each_online_cpu(cpu) {
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index = octeon_coreid_for_cpu(cpu) * 2;
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if (cpumask_test_cpu(cpu, dest))
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if (cpumask_test_cpu(cpu, dest) && enable_one) {
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enable_one = 0;
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cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
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else
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} else {
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cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
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}
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}
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return 0;
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}
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#endif
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@ -296,8 +395,7 @@ static struct irq_chip octeon_irq_chip_ciu0_v2 = {
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.name = "CIU0",
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.enable = octeon_irq_ciu0_enable_v2,
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.disable = octeon_irq_ciu0_disable_all_v2,
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.ack = octeon_irq_ciu0_ack_v2,
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.eoi = octeon_irq_ciu0_eoi_v2,
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.eoi = octeon_irq_ciu0_enable_v2,
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#ifdef CONFIG_SMP
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.set_affinity = octeon_irq_ciu0_set_affinity_v2,
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#endif
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@ -307,35 +405,26 @@ static struct irq_chip octeon_irq_chip_ciu0 = {
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.name = "CIU0",
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.enable = octeon_irq_ciu0_enable,
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.disable = octeon_irq_ciu0_disable,
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.ack = octeon_irq_ciu0_ack,
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.eoi = octeon_irq_ciu0_eoi,
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#ifdef CONFIG_SMP
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.set_affinity = octeon_irq_ciu0_set_affinity,
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#endif
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};
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static struct irq_chip octeon_irq_chip_ciu0_timer_v2 = {
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.name = "CIU0-T",
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.enable = octeon_irq_ciu0_enable_v2,
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.disable = octeon_irq_ciu0_disable_all_v2,
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.ack = octeon_irq_ciu0_timer_ack_v2,
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.eoi = octeon_irq_ciu0_eoi_v2,
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#ifdef CONFIG_SMP
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.set_affinity = octeon_irq_ciu0_set_affinity_v2,
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#endif
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};
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static struct irq_chip octeon_irq_chip_ciu0_timer = {
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.name = "CIU0-T",
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.enable = octeon_irq_ciu0_enable,
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/* The mbox versions don't do any affinity or round-robin. */
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static struct irq_chip octeon_irq_chip_ciu0_mbox_v2 = {
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.name = "CIU0-M",
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.enable = octeon_irq_ciu0_enable_mbox_v2,
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.disable = octeon_irq_ciu0_disable,
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.ack = octeon_irq_ciu0_timer_ack_v1,
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.eoi = octeon_irq_ciu0_eoi,
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#ifdef CONFIG_SMP
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.set_affinity = octeon_irq_ciu0_set_affinity,
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#endif
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.eoi = octeon_irq_ciu0_eoi_mbox_v2,
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};
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static struct irq_chip octeon_irq_chip_ciu0_mbox = {
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.name = "CIU0-M",
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.enable = octeon_irq_ciu0_enable_mbox,
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.disable = octeon_irq_ciu0_disable,
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.eoi = octeon_irq_ciu0_eoi,
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};
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static void octeon_irq_ciu1_ack(unsigned int irq)
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{
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@ -363,7 +452,8 @@ static void octeon_irq_ciu1_eoi(unsigned int irq)
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static void octeon_irq_ciu1_enable(unsigned int irq)
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{
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int coreid = cvmx_get_core_num();
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struct irq_desc *desc = irq_to_desc(irq);
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int coreid = next_coreid_for_irq(desc);
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unsigned long flags;
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uint64_t en1;
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int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
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@ -376,6 +466,25 @@ static void octeon_irq_ciu1_enable(unsigned int irq)
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raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
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}
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/*
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* Watchdog interrupts are special. They are associated with a single
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* core, so we hardwire the affinity to that core.
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*/
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static void octeon_irq_ciu1_wd_enable(unsigned int irq)
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{
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unsigned long flags;
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uint64_t en1;
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int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
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int coreid = bit;
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raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
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en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
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en1 |= 1ull << bit;
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cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
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cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
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raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
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}
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static void octeon_irq_ciu1_disable(unsigned int irq)
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{
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int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
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@ -403,10 +512,31 @@ static void octeon_irq_ciu1_disable(unsigned int irq)
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*/
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static void octeon_irq_ciu1_enable_v2(unsigned int irq)
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{
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int index = cvmx_get_core_num() * 2 + 1;
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int index;
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u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
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struct irq_desc *desc = irq_to_desc(irq);
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if ((desc->status & IRQ_DISABLED) == 0) {
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index = next_coreid_for_irq(desc) * 2 + 1;
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cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
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}
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}
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/*
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* Watchdog interrupts are special. They are associated with a single
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* core, so we hardwire the affinity to that core.
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*/
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static void octeon_irq_ciu1_wd_enable_v2(unsigned int irq)
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{
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int index;
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int coreid = irq - OCTEON_IRQ_WDOG0;
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u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
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struct irq_desc *desc = irq_to_desc(irq);
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if ((desc->status & IRQ_DISABLED) == 0) {
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index = coreid * 2 + 1;
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cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
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}
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}
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/*
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@ -421,20 +551,6 @@ static void octeon_irq_ciu1_ack_v2(unsigned int irq)
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cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
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}
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/*
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* Enable the irq on the current core for chips that have the EN*_W1{S,C}
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* registers.
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*/
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static void octeon_irq_ciu1_eoi_v2(unsigned int irq)
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{
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struct irq_desc *desc = irq_desc + irq;
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int index = cvmx_get_core_num() * 2 + 1;
|
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u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
|
||||
|
||||
if ((desc->status & IRQ_DISABLED) == 0)
|
||||
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
|
||||
}
|
||||
|
||||
/*
|
||||
* Disable the irq on the all cores for chips that have the EN*_W1{S,C}
|
||||
* registers.
|
||||
@ -455,19 +571,30 @@ static int octeon_irq_ciu1_set_affinity(unsigned int irq,
|
||||
const struct cpumask *dest)
|
||||
{
|
||||
int cpu;
|
||||
struct irq_desc *desc = irq_to_desc(irq);
|
||||
int enable_one = (desc->status & IRQ_DISABLED) == 0;
|
||||
unsigned long flags;
|
||||
int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
|
||||
|
||||
/*
|
||||
* For non-v2 CIU, we will allow only single CPU affinity.
|
||||
* This removes the need to do locking in the .ack/.eoi
|
||||
* functions.
|
||||
*/
|
||||
if (cpumask_weight(dest) != 1)
|
||||
return -EINVAL;
|
||||
|
||||
raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
|
||||
for_each_online_cpu(cpu) {
|
||||
int coreid = octeon_coreid_for_cpu(cpu);
|
||||
uint64_t en1 =
|
||||
cvmx_read_csr(CVMX_CIU_INTX_EN1
|
||||
(coreid * 2 + 1));
|
||||
if (cpumask_test_cpu(cpu, dest))
|
||||
cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
|
||||
if (cpumask_test_cpu(cpu, dest) && enable_one) {
|
||||
enable_one = 0;
|
||||
en1 |= 1ull << bit;
|
||||
else
|
||||
} else {
|
||||
en1 &= ~(1ull << bit);
|
||||
}
|
||||
cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
|
||||
}
|
||||
/*
|
||||
@ -489,14 +616,18 @@ static int octeon_irq_ciu1_set_affinity_v2(unsigned int irq,
|
||||
{
|
||||
int cpu;
|
||||
int index;
|
||||
struct irq_desc *desc = irq_to_desc(irq);
|
||||
int enable_one = (desc->status & IRQ_DISABLED) == 0;
|
||||
u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
|
||||
for_each_online_cpu(cpu) {
|
||||
index = octeon_coreid_for_cpu(cpu) * 2 + 1;
|
||||
if (cpumask_test_cpu(cpu, dest))
|
||||
if (cpumask_test_cpu(cpu, dest) && enable_one) {
|
||||
enable_one = 0;
|
||||
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
|
||||
else
|
||||
} else {
|
||||
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
@ -505,11 +636,10 @@ static int octeon_irq_ciu1_set_affinity_v2(unsigned int irq,
|
||||
* Newer octeon chips have support for lockless CIU operation.
|
||||
*/
|
||||
static struct irq_chip octeon_irq_chip_ciu1_v2 = {
|
||||
.name = "CIU0",
|
||||
.name = "CIU1",
|
||||
.enable = octeon_irq_ciu1_enable_v2,
|
||||
.disable = octeon_irq_ciu1_disable_all_v2,
|
||||
.ack = octeon_irq_ciu1_ack_v2,
|
||||
.eoi = octeon_irq_ciu1_eoi_v2,
|
||||
.eoi = octeon_irq_ciu1_enable_v2,
|
||||
#ifdef CONFIG_SMP
|
||||
.set_affinity = octeon_irq_ciu1_set_affinity_v2,
|
||||
#endif
|
||||
@ -519,19 +649,36 @@ static struct irq_chip octeon_irq_chip_ciu1 = {
|
||||
.name = "CIU1",
|
||||
.enable = octeon_irq_ciu1_enable,
|
||||
.disable = octeon_irq_ciu1_disable,
|
||||
.ack = octeon_irq_ciu1_ack,
|
||||
.eoi = octeon_irq_ciu1_eoi,
|
||||
#ifdef CONFIG_SMP
|
||||
.set_affinity = octeon_irq_ciu1_set_affinity,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct irq_chip octeon_irq_chip_ciu1_wd_v2 = {
|
||||
.name = "CIU1-W",
|
||||
.enable = octeon_irq_ciu1_wd_enable_v2,
|
||||
.disable = octeon_irq_ciu1_disable_all_v2,
|
||||
.eoi = octeon_irq_ciu1_wd_enable_v2,
|
||||
};
|
||||
|
||||
static struct irq_chip octeon_irq_chip_ciu1_wd = {
|
||||
.name = "CIU1-W",
|
||||
.enable = octeon_irq_ciu1_wd_enable,
|
||||
.disable = octeon_irq_ciu1_disable,
|
||||
.eoi = octeon_irq_ciu1_eoi,
|
||||
};
|
||||
|
||||
static void (*octeon_ciu0_ack)(unsigned int);
|
||||
static void (*octeon_ciu1_ack)(unsigned int);
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
int irq;
|
||||
unsigned int irq;
|
||||
struct irq_chip *chip0;
|
||||
struct irq_chip *chip0_timer;
|
||||
struct irq_chip *chip0_mbox;
|
||||
struct irq_chip *chip1;
|
||||
struct irq_chip *chip1_wd;
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
/* Set the default affinity to the boot cpu. */
|
||||
@ -545,13 +692,19 @@ void __init arch_init_irq(void)
|
||||
if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) ||
|
||||
OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
|
||||
OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X)) {
|
||||
octeon_ciu0_ack = octeon_irq_ciu0_ack_v2;
|
||||
octeon_ciu1_ack = octeon_irq_ciu1_ack_v2;
|
||||
chip0 = &octeon_irq_chip_ciu0_v2;
|
||||
chip0_timer = &octeon_irq_chip_ciu0_timer_v2;
|
||||
chip0_mbox = &octeon_irq_chip_ciu0_mbox_v2;
|
||||
chip1 = &octeon_irq_chip_ciu1_v2;
|
||||
chip1_wd = &octeon_irq_chip_ciu1_wd_v2;
|
||||
} else {
|
||||
octeon_ciu0_ack = octeon_irq_ciu0_ack;
|
||||
octeon_ciu1_ack = octeon_irq_ciu1_ack;
|
||||
chip0 = &octeon_irq_chip_ciu0;
|
||||
chip0_timer = &octeon_irq_chip_ciu0_timer;
|
||||
chip0_mbox = &octeon_irq_chip_ciu0_mbox;
|
||||
chip1 = &octeon_irq_chip_ciu1;
|
||||
chip1_wd = &octeon_irq_chip_ciu1_wd;
|
||||
}
|
||||
|
||||
/* 0 - 15 reserved for i8259 master and slave controller. */
|
||||
@ -565,26 +718,22 @@ void __init arch_init_irq(void)
|
||||
/* 24 - 87 CIU_INT_SUM0 */
|
||||
for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) {
|
||||
switch (irq) {
|
||||
case OCTEON_IRQ_GMX_DRP0:
|
||||
case OCTEON_IRQ_GMX_DRP1:
|
||||
case OCTEON_IRQ_IPD_DRP:
|
||||
case OCTEON_IRQ_KEY_ZERO:
|
||||
case OCTEON_IRQ_TIMER0:
|
||||
case OCTEON_IRQ_TIMER1:
|
||||
case OCTEON_IRQ_TIMER2:
|
||||
case OCTEON_IRQ_TIMER3:
|
||||
set_irq_chip_and_handler(irq, chip0_timer, handle_percpu_irq);
|
||||
case OCTEON_IRQ_MBOX0:
|
||||
case OCTEON_IRQ_MBOX1:
|
||||
set_irq_chip_and_handler(irq, chip0_mbox, handle_percpu_irq);
|
||||
break;
|
||||
default:
|
||||
set_irq_chip_and_handler(irq, chip0, handle_percpu_irq);
|
||||
set_irq_chip_and_handler(irq, chip0, handle_fasteoi_irq);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* 88 - 151 CIU_INT_SUM1 */
|
||||
for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_RESERVED151; irq++) {
|
||||
set_irq_chip_and_handler(irq, chip1, handle_percpu_irq);
|
||||
}
|
||||
for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_WDOG15; irq++)
|
||||
set_irq_chip_and_handler(irq, chip1_wd, handle_fasteoi_irq);
|
||||
|
||||
for (irq = OCTEON_IRQ_UART2; irq <= OCTEON_IRQ_RESERVED151; irq++)
|
||||
set_irq_chip_and_handler(irq, chip1, handle_fasteoi_irq);
|
||||
|
||||
set_c0_status(0x300 << 2);
|
||||
}
|
||||
@ -600,6 +749,7 @@ asmlinkage void plat_irq_dispatch(void)
|
||||
unsigned long cop0_status;
|
||||
uint64_t ciu_en;
|
||||
uint64_t ciu_sum;
|
||||
unsigned int irq;
|
||||
|
||||
while (1) {
|
||||
cop0_cause = read_c0_cause();
|
||||
@ -611,18 +761,24 @@ asmlinkage void plat_irq_dispatch(void)
|
||||
ciu_sum = cvmx_read_csr(ciu_sum0_address);
|
||||
ciu_en = cvmx_read_csr(ciu_en0_address);
|
||||
ciu_sum &= ciu_en;
|
||||
if (likely(ciu_sum))
|
||||
do_IRQ(fls64(ciu_sum) + OCTEON_IRQ_WORKQ0 - 1);
|
||||
else
|
||||
if (likely(ciu_sum)) {
|
||||
irq = fls64(ciu_sum) + OCTEON_IRQ_WORKQ0 - 1;
|
||||
octeon_ciu0_ack(irq);
|
||||
do_IRQ(irq);
|
||||
} else {
|
||||
spurious_interrupt();
|
||||
}
|
||||
} else if (unlikely(cop0_cause & STATUSF_IP3)) {
|
||||
ciu_sum = cvmx_read_csr(ciu_sum1_address);
|
||||
ciu_en = cvmx_read_csr(ciu_en1_address);
|
||||
ciu_sum &= ciu_en;
|
||||
if (likely(ciu_sum))
|
||||
do_IRQ(fls64(ciu_sum) + OCTEON_IRQ_WDOG0 - 1);
|
||||
else
|
||||
if (likely(ciu_sum)) {
|
||||
irq = fls64(ciu_sum) + OCTEON_IRQ_WDOG0 - 1;
|
||||
octeon_ciu1_ack(irq);
|
||||
do_IRQ(irq);
|
||||
} else {
|
||||
spurious_interrupt();
|
||||
}
|
||||
} else if (likely(cop0_cause)) {
|
||||
do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE);
|
||||
} else {
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user