FEX-Emu/linux
1
0
Fork 0
mirror of https://github.com/FEX-Emu/linux.git synced 2024-12-25 10:59:05 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Fixes for omaps for issues discovered during the merge window and

Browse Source 
enabling of a few features that had to wait for the driver
 dependencies to clear.
 
 The fixes included are:
 
 - Fix am43xx hard reset flags
 
 - Fix SoC detection for DRA722
 
 - Fix CPU OPP table for omap5
 
 - Fix legacy mux parser bug if requested muxname is a prefix of
   multiple mux entries
 
 - Fix qspi interrupt binding that relies on the irq crossbar
   that has not yet been enabled
 
 - Add missing phy_sel for am43x-epos-evm
 
 - Drop unused gic_init_irq() that is no longer needed
 
 And the enabling of features that had driver dependencies are:
 
 - Change dra7 to use Audio Tracking Logic clock instead of a fixed
   clock now that the clock driver for it has been merged
 
 - Enable off idle configuration for selected omaps as all the kernel
   dependencies for device tree based booting are finally merged as
   this is needed to get the automated PM tests working finally with
   device tree based booting
 
 - Add hwmod entry for ocp2scp3 for omap5 to get sata working as
   all the driver dependencies are now in the kernel and this patch
   fell through the cracks during the merge window
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJTn/+wAAoJEBvUPslcq6Vzr1AP/1/HCOmp5B4tP3WhRPDK7nSr
 hNjoa3uFhhpc6LoO1PMsbHcusBwrD9/Dr1BM53vltRXGGMFiADRw02N0BMSiDB4y
 cWKo6C7d1PEsX7SvH6ehzQV6pB8v8zAhShuuA2sPQRcGsKPfUTCI3rjjvCNvcnmr
 fIyLOwZ8MkFkAxrSCNUHULRK4U8Tivxa0k9eTEoPo+y5rkolTwtU9C5ybpUk4Jju
 K1yjZOo+hbNENFLS4FqM6Y4IjlJlz49baDoaZXkIhP+UhvdKSLAhNta76vRtnnDE
 wX0STSCYbPL/Tj+bfCk3VJa1dpgkHYY9y8H7FOsf0osqbP5j0H49i/+y3+lTu3A3
 NzVYZRlu32llCp5pvVVy6ibjme9jRwz/HPtKEXDtbtFG41pvDaHnSF72OOVz6DoN
 Yu9tN6vojMaeQeE69mFzy7RI6SWpOVxjHyPG1b2rGoJayY+P2oR43iPAeWF6q7lp
 Nz/LWDqNwIj4H1T4KWIhK+mv/+YJDzWnIDczToK0ROZ8JOR3A0MRWwBvYpvHPRnY
 rxE2vtRpHUqOPiPtj1sKzUti74xJahCL9oXLRuFbG4z5Le1jelM9dYdjf4wpAoWs
 H+1RP20GRos1dNIzoPZieOP+X4jp0m6A1wtcy49Dbivw6Gx7oJecH7zkMvobgy8C
 gJ8G86a9R4EXKNJmjqvc
 =2HDE
 -----END PGP SIGNATURE-----

Merge tag 'omap-for-v3.16/fixes-against-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes

Merge OMAP fixes from Tony Lindgren:

Fixes for omaps for issues discovered during the merge window and
enabling of a few features that had to wait for the driver
dependencies to clear.

The fixes included are:

- Fix am43xx hard reset flags
- Fix SoC detection for DRA722
- Fix CPU OPP table for omap5
- Fix legacy mux parser bug if requested muxname is a prefix of
  multiple mux entries
- Fix qspi interrupt binding that relies on the irq crossbar
  that has not yet been enabled
- Add missing phy_sel for am43x-epos-evm
- Drop unused gic_init_irq() that is no longer needed

And the enabling of features that had driver dependencies are:

- Change dra7 to use Audio Tracking Logic clock instead of a fixed
  clock now that the clock driver for it has been merged

- Enable off idle configuration for selected omaps as all the kernel
  dependencies for device tree based booting are finally merged as
  this is needed to get the automated PM tests working finally with
  device tree based booting

- Add hwmod entry for ocp2scp3 for omap5 to get sata working as
  all the driver dependencies are now in the kernel and this patch
  fell through the cracks during the merge window

* tag 'omap-for-v3.16/fixes-against-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: dts: dra7-evm: remove interrupt binding
  ARM: OMAP2+: Fix parser-bug in platform muxing code
  ARM: DTS: dra7/dra7xx-clocks: ATL related changes
  ARM: OMAP2+: drop unused function
  ARM: dts: am43x-epos-evm: Add Missing cpsw-phy-sel for am43x-epos-evm
  ARM: dts: omap5: Update CPU OPP table as per final production Manual
  ARM: DRA722: add detection of SoC information
  ARM: dts: Enable twl4030 off-idle configuration for selected omaps
  ARM: OMAP5: hwmod: Add ocp2scp3 and sata hwmods
  ARM: OMAP2+: hwmod: Change hardreset soc_ops for AM43XX
This commit is contained in:
Olof Johansson 2014-07-04 21:45:38 -07:00
commit 5acd78c59a
16 changed files with 139 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/boot/dts/am43x-epos-evm.dts
View File

@ -319,6 +319,10 @@
phy-mode = "rmii";
};
&phy_sel {
rmii-clock-ext;
};
&i2c0 {
status = "okay";
pinctrl-names = "default";

12
arch/arm/boot/dts/dra7.dtsi
View File

@ -773,7 +773,6 @@
clocks = <&qspi_gfclk_div>;
clock-names = "fck";
num-cs = <4>;
interrupts = <0 343 0x4>;
status = "disabled";
};
@ -984,6 +983,17 @@
#size-cells = <1>;
status = "disabled";
};
atl: atl@4843c000 {
compatible = "ti,dra7-atl";
reg = <0x4843c000 0x3ff>;
ti,hwmods = "atl";
ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
<&atl_clkin2_ck>, <&atl_clkin3_ck>;
clocks = <&atl_gfclk_mux>;
clock-names = "fck";
status = "disabled";
};
};
};

16
arch/arm/boot/dts/dra7xx-clocks.dtsi
View File

@ -10,26 +10,26 @@
&cm_core_aon_clocks {
atl_clkin0_ck: atl_clkin0_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
compatible = "ti,dra7-atl-clock";
clocks = <&atl_gfclk_mux>;
};
atl_clkin1_ck: atl_clkin1_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
compatible = "ti,dra7-atl-clock";
clocks = <&atl_gfclk_mux>;
};
atl_clkin2_ck: atl_clkin2_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
compatible = "ti,dra7-atl-clock";
clocks = <&atl_gfclk_mux>;
};
atl_clkin3_ck: atl_clkin3_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
compatible = "ti,dra7-atl-clock";
clocks = <&atl_gfclk_mux>;
};
hdmi_clkin_ck: hdmi_clkin_ck {

6
arch/arm/boot/dts/omap3-beagle-xm.dts
View File

@ -251,6 +251,11 @@
codec {
};
};
twl_power: power {
compatible = "ti,twl4030-power-beagleboard-xm", "ti,twl4030-power-idle-osc-off";
ti,use_poweroff;
};
};
};
@ -301,6 +306,7 @@
};
&uart3 {
interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
};

7
arch/arm/boot/dts/omap3-evm-common.dtsi
View File

@ -50,6 +50,13 @@
gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>;
};
&twl {
twl_power: power {
compatible = "ti,twl4030-power-omap3-evm", "ti,twl4030-power-idle";
ti,use_poweroff;
};
};
&i2c2 {
clock-frequency = <400000>;
};

5
arch/arm/boot/dts/omap3-n900.dts
View File

@ -351,6 +351,11 @@
compatible = "ti,twl4030-audio";
ti,enable-vibra = <1>;
};
twl_power: power {
compatible = "ti,twl4030-power-n900", "ti,twl4030-power-idle-osc-off";
ti,use_poweroff;
};
};
&twl_keypad {

1
arch/arm/boot/dts/omap5.dtsi
View File

@ -45,7 +45,6 @@
operating-points = <
/* kHz uV */
500000 880000
1000000 1060000
1500000 1250000
>;

6
arch/arm/mach-omap2/Makefile
View File

@ -110,14 +110,16 @@ obj-y += prm_common.o cm_common.o
obj-$(CONFIG_ARCH_OMAP2) += prm2xxx_3xxx.o prm2xxx.o cm2xxx.o
obj-$(CONFIG_ARCH_OMAP3) += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o
obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
obj-$(CONFIG_SOC_AM33XX) += prm33xx.o cm33xx.o
omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \
prcm_mpu44xx.o prminst44xx.o \
vc44xx_data.o vp44xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common)
obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common)
obj-$(CONFIG_SOC_DRA7XX) += $(omap-prcm-4-5-common)
obj-$(CONFIG_SOC_AM43XX) += $(omap-prcm-4-5-common)
am33xx-43xx-prcm-common += prm33xx.o cm33xx.o
obj-$(CONFIG_SOC_AM33XX) += $(am33xx-43xx-prcm-common)
obj-$(CONFIG_SOC_AM43XX) += $(omap-prcm-4-5-common) \
$(am33xx-43xx-prcm-common)
# OMAP voltage domains
voltagedomain-common := voltage.o vc.o vp.o

2
arch/arm/mach-omap2/cm33xx.h
View File

@ -380,7 +380,7 @@ void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs);
void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs);
void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs);
#ifdef CONFIG_SOC_AM33XX
#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
u16 clkctrl_offs);
extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,

1
arch/arm/mach-omap2/common.h
View File

@ -248,7 +248,6 @@ static inline void __iomem *omap4_get_scu_base(void)
}
#endif
extern void __init gic_init_irq(void);
extern void gic_dist_disable(void);
extern void gic_dist_enable(void);
extern bool gic_dist_disabled(void);

12
arch/arm/mach-omap2/id.c
View File

@ -649,6 +649,18 @@ void __init dra7xxx_check_revision(void)
}
break;
case 0xb9bc:
switch (rev) {
case 0:
omap_revision = DRA722_REV_ES1_0;
break;
default:
/* If we have no new revisions */
omap_revision = DRA722_REV_ES1_0;
break;
}
break;
default:
/* Unknown default to latest silicon rev as default*/
pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%d)\n",

6
arch/arm/mach-omap2/mux.c
View File

@ -183,8 +183,10 @@ static int __init _omap_mux_get_by_name(struct omap_mux_partition *partition,
m0_entry = mux->muxnames[0];
/* First check for full name in mode0.muxmode format */
if (mode0_len && strncmp(muxname, m0_entry, mode0_len))
continue;
if (mode0_len)
if (strncmp(muxname, m0_entry, mode0_len) ||
(strlen(m0_entry) != mode0_len))
continue;
/* Then check for muxmode only */
for (i = 0; i < OMAP_MUX_NR_MODES; i++) {

20
arch/arm/mach-omap2/omap4-common.c
View File

@ -102,26 +102,6 @@ void __init omap_barriers_init(void)
{}
#endif
void __init gic_init_irq(void)
{
void __iomem *omap_irq_base;
/* Static mapping, never released */
gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
BUG_ON(!gic_dist_base_addr);
twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_4K);
BUG_ON(!twd_base);
/* Static mapping, never released */
omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
BUG_ON(!omap_irq_base);
omap_wakeupgen_init();
gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
}
void gic_dist_disable(void)
{
if (gic_dist_base_addr)

6
arch/arm/mach-omap2/omap_hwmod.c
View File

@ -4251,9 +4251,9 @@ void __init omap_hwmod_init(void)
soc_ops.enable_module = _omap4_enable_module;
soc_ops.disable_module = _omap4_disable_module;
soc_ops.wait_target_ready = _omap4_wait_target_ready;
soc_ops.assert_hardreset = _omap4_assert_hardreset;
soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
soc_ops.assert_hardreset = _am33xx_assert_hardreset;
soc_ops.deassert_hardreset = _am33xx_deassert_hardreset;
soc_ops.is_hardreset_asserted = _am33xx_is_hardreset_asserted;
soc_ops.init_clkdm = _init_clkdm;
} else if (soc_is_am33xx()) {
soc_ops.enable_module = _am33xx_enable_module;

73
arch/arm/mach-omap2/omap_hwmod_54xx_data.c
View File

@ -2020,6 +2020,77 @@ static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
},
};
/*
* 'ocp2scp' class
* bridge to transform ocp interface protocol to scp (serial control port)
* protocol
*/
/* ocp2scp3 */
static struct omap_hwmod omap54xx_ocp2scp3_hwmod;
/* l4_cfg -> ocp2scp3 */
static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp3 = {
.master = &omap54xx_l4_cfg_hwmod,
.slave = &omap54xx_ocp2scp3_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod omap54xx_ocp2scp3_hwmod = {
.name = "ocp2scp3",
.class = &omap54xx_ocp2scp_hwmod_class,
.clkdm_name = "l3init_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
};
/*
* 'sata' class
* sata: serial ata interface gen2 compliant ( 1 rx/ 1 tx)
*/
static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
.sysc_offs = 0x0000,
.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2,
};
static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
.name = "sata",
.sysc = &omap54xx_sata_sysc,
};
/* sata */
static struct omap_hwmod omap54xx_sata_hwmod = {
.name = "sata",
.class = &omap54xx_sata_hwmod_class,
.clkdm_name = "l3init_clkdm",
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.main_clk = "func_48m_fclk",
.mpu_rt_idx = 1,
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
.context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* l4_cfg -> sata */
static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
.master = &omap54xx_l4_cfg_hwmod,
.slave = &omap54xx_sata_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/*
* Interfaces
@ -2765,6 +2836,8 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
&omap54xx_l4_cfg__usb_tll_hs,
&omap54xx_l4_cfg__usb_otg_ss,
&omap54xx_l4_wkup__wd_timer2,
&omap54xx_l4_cfg__ocp2scp3,
&omap54xx_l4_cfg__sata,
NULL,
};

1
arch/arm/mach-omap2/soc.h
View File

@ -462,6 +462,7 @@ IS_OMAP_TYPE(3430, 0x3430)
#define DRA7XX_CLASS 0x07000000
#define DRA752_REV_ES1_0 (DRA7XX_CLASS | (0x52 << 16) | (0x10 << 8))
#define DRA752_REV_ES1_1 (DRA7XX_CLASS | (0x52 << 16) | (0x11 << 8))
#define DRA722_REV_ES1_0 (DRA7XX_CLASS | (0x22 << 16) | (0x10 << 8))
void omap2xxx_check_revision(void);
void omap3xxx_check_revision(void);