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Merge branch 'next/cleanup-header' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup

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From Kukjin Kim:
AS I commented, this makes <mach/*.h> local so that they could be removed.

* 'next/cleanup-header' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (26 commits)
  ARM: S3C64XX: Fix missing header error with CONFIG_CPU_IDLE enabled
  ARM: S3C64XX: make regs-syscon-power.h local
  ARM: S3C64XX: make regs-sys.h local
  ARM: S3C64XX: make regs-srom.h local
  ARM: S3C64XX: make regs-modem.h local
  ARM: S3C64XX: make regs-gpio-memport.h local
  ARM: S3C64XX: make crag6410.h local
  ARM: S3C24XX: remove dsc.c and make regs-dsc.h local
  ARM: S3C24XX: remove idle.h
  ARM: S3C2412: cleanup regs-s3c2412.h
  ARM: S3C2416: remove regs-s3c2416-mem.h and regs-s3c2416.h
  ARM: S3C24XX: make vr1000-cpld.h, vr1000-irq.h and vr1000-map.h local
  ARM: S3C24XX: make otom-map.h local
  ARM: S3C24XX: make osiris-cpld.h and osiris-map.h local
  ARM: S3C24XX: make h1940.h and h1940-latch.h local
  ARM: S3C24XX: make gta02.h local
  ARM: S3C24XX: make bast-cpld.h, bast-irq.h and bast-map.h local
  ARM: S3C24XX: make anubis-cpld, anubis-irq and anubis-map local
  ARM: SAMSUNG: cleanup mach/gpio-fns.h gpio-track.h and gpio-nrs.h
  ARM: SAMSUNG: cleanup mach/regs-audss.h file
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2013-02-04 21:49:03 -08:00
commit 5b399db0b7
105 changed files with 852 additions and 1792 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/mach-exynos/common.c
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@ -36,7 +36,6 @@
#include <mach/regs-irq.h>
#include <mach/regs-pmu.h>
#include <mach/regs-gpio.h>
#include <mach/pmu.h>
#include <plat/cpu.h>
#include <plat/clock.h>

20
arch/arm/mach-exynos/common.h
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@ -64,4 +64,24 @@ extern struct smp_operations exynos_smp_ops;
extern void exynos_cpu_die(unsigned int cpu);
/* PMU(Power Management Unit) support */
#define PMU_TABLE_END NULL
enum sys_powerdown {
SYS_AFTR,
SYS_LPA,
SYS_SLEEP,
NUM_SYS_POWERDOWN,
};
extern unsigned long l2x0_regs_phys;
struct exynos_pmu_conf {
void __iomem *reg;
unsigned int val[NUM_SYS_POWERDOWN];
};
extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
extern void s3c_cpu_resume(void);
#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */

3
arch/arm/mach-exynos/cpuidle.c
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@ -23,10 +23,11 @@
#include <asm/cpuidle.h>
#include <mach/regs-clock.h>
#include <mach/regs-pmu.h>
#include <mach/pmu.h>
#include <plat/cpu.h>
#include "common.h"
#define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
(S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))

3
arch/arm/mach-exynos/dev-audio.c
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@ -21,7 +21,8 @@
#include <mach/map.h>
#include <mach/dma.h>
#include <mach/irqs.h>
#include <mach/regs-audss.h>
#define EXYNOS4_AUDSS_INT_MEM (0x03000000)
static int exynos4_cfg_i2s(struct platform_device *pdev)
{

34
arch/arm/mach-exynos/include/mach/pmu.h
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@ -1,34 +0,0 @@
/* linux/arch/arm/mach-exynos4/include/mach/pmu.h
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* EXYNOS4210 - PMU(Power Management Unit) support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_PMU_H
#define __ASM_ARCH_PMU_H __FILE__
#define PMU_TABLE_END NULL
enum sys_powerdown {
SYS_AFTR,
SYS_LPA,
SYS_SLEEP,
NUM_SYS_POWERDOWN,
};
extern unsigned long l2x0_regs_phys;
struct exynos_pmu_conf {
void __iomem *reg;
unsigned int val[NUM_SYS_POWERDOWN];
};
extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
extern void s3c_cpu_resume(void);
#endif /* __ASM_ARCH_PMU_H */

18
arch/arm/mach-exynos/include/mach/regs-audss.h
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@ -1,18 +0,0 @@
/* arch/arm/mach-exynos4/include/mach/regs-audss.h
*
* Copyright (c) 2011 Samsung Electronics
* http://www.samsung.com
*
* Exynos4 Audio SubSystem clock register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PLAT_REGS_AUDSS_H
#define __PLAT_REGS_AUDSS_H __FILE__
#define EXYNOS4_AUDSS_INT_MEM (0x03000000)
#endif /* _PLAT_REGS_AUDSS_H */

3
arch/arm/mach-exynos/pm.c
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@ -34,7 +34,8 @@
#include <mach/regs-clock.h>
#include <mach/regs-pmu.h>
#include <mach/pm-core.h>
#include <mach/pmu.h>
#include "common.h"
static struct sleep_save exynos4_set_clksrc[] = {
{ .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, },

3
arch/arm/mach-exynos/pmu.c
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@ -14,7 +14,8 @@
#include <linux/bug.h>
#include <mach/regs-clock.h>
#include <mach/pmu.h>
#include "common.h"
static struct exynos_pmu_conf *exynos_pmu_config;

2
arch/arm/mach-s3c2440/Makefile
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@ -9,8 +9,6 @@ obj-m :=
obj-n :=
obj- :=
obj-$(CONFIG_CPU_S3C2440) += dsc.o
obj-$(CONFIG_S3C2440_CPUFREQ) += s3c2440-cpufreq.o
obj-$(CONFIG_S3C2440_PLL_12000000) += s3c2440-pll-12000000.o

54
arch/arm/mach-s3c2440/dsc.c
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@ -1,54 +0,0 @@
/* linux/arch/arm/mach-s3c2440/dsc.c
*
* Copyright (c) 2004-2005 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Samsung S3C2440 Drive Strength Control support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/io.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <mach/regs-gpio.h>
#include <mach/regs-dsc.h>
#include <plat/cpu.h>
#include <plat/s3c244x.h>
int s3c2440_set_dsc(unsigned int pin, unsigned int value)
{
void __iomem *base;
unsigned long val;
unsigned long flags;
unsigned long mask;
base = (pin & S3C2440_SELECT_DSC1) ? S3C2440_DSC1 : S3C2440_DSC0;
mask = 3 << S3C2440_DSC_GETSHIFT(pin);
local_irq_save(flags);
val = __raw_readl(base);
val &= ~mask;
val |= value & mask;
__raw_writel(val, base);
local_irq_restore(flags);
return 0;
}
EXPORT_SYMBOL(s3c2440_set_dsc);

53
arch/arm/mach-s3c24xx/anubis.h Normal file
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@ -0,0 +1,53 @@
/*
* Copyright (c) 2005 Simtec Electronics
* http://www.simtec.co.uk/products/
* Ben Dooks <ben@simtec.co.uk>
*
* ANUBIS - CPLD control constants
* ANUBIS - IRQ Number definitions
* ANUBIS - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __MACH_S3C24XX_ANUBIS_H
#define __MACH_S3C24XX_ANUBIS_H __FILE__
/* CTRL2 - NAND WP control, IDE Reset assert/check */
#define ANUBIS_CTRL1_NANDSEL (0x3)
/* IDREG - revision */
#define ANUBIS_IDREG_REVMASK (0x7)
/* irq */
#define ANUBIS_IRQ_IDE0 IRQ_EINT2
#define ANUBIS_IRQ_IDE1 IRQ_EINT3
#define ANUBIS_IRQ_ASIX IRQ_EINT1
/* map */
/* start peripherals off after the S3C2410 */
#define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x01800000))
#define ANUBIS_PA_CPLD (S3C2410_CS1 | (1<<26))
/* we put the CPLD registers next, to get them out of the way */
#define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000)
#define ANUBIS_PA_CTRL1 ANUBIS_PA_CPLD
#define ANUBIS_VA_IDREG ANUBIS_IOADDR(0x00300000)
#define ANUBIS_PA_IDREG (ANUBIS_PA_CPLD + (3 << 23))
#define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000)
#define ANUBIS_IDEPRIAUX ANUBIS_IOADDR(0x01100000)
#define ANUBIS_IDESEC ANUBIS_IOADDR(0x01200000)
#define ANUBIS_IDESECAUX ANUBIS_IOADDR(0x01300000)
#endif /* __MACH_S3C24XX_ANUBIS_H */

18
arch/arm/mach-s3c24xx/bast-ide.c
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@ -25,8 +25,8 @@
#include <asm/mach/irq.h>
#include <mach/map.h>
#include <mach/bast-map.h>
#include <mach/bast-irq.h>
#include "bast.h"
/* IDE ports */
@ -34,12 +34,10 @@ static struct pata_platform_info bast_ide_platdata = {
.ioport_shift = 5,
};
#define IDE_CS S3C2410_CS5
static struct resource bast_ide0_resource[] = {
[0] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDEPRI, 8 * 0x20),
[1] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDEPRIAUX + (6 * 0x20), 0x20),
[2] = DEFINE_RES_IRQ(IRQ_IDE0),
[0] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDEPRI, 8 * 0x20),
[1] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDEPRIAUX + (6 * 0x20), 0x20),
[2] = DEFINE_RES_IRQ(BAST_IRQ_IDE0),
};
static struct platform_device bast_device_ide0 = {
@ -55,9 +53,9 @@ static struct platform_device bast_device_ide0 = {
};
static struct resource bast_ide1_resource[] = {
[0] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDESEC, 8 * 0x20),
[1] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDESECAUX + (6 * 0x20), 0x20),
[2] = DEFINE_RES_IRQ(IRQ_IDE1),
[0] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDESEC, 8 * 0x20),
[1] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDESECAUX + (6 * 0x20), 0x20),
[2] = DEFINE_RES_IRQ(BAST_IRQ_IDE1),
};
static struct platform_device bast_device_ide1 = {

19
arch/arm/mach-s3c24xx/bast-irq.c
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@ -27,27 +27,20 @@
#include <linux/device.h>
#include <linux/io.h>
#include <asm/mach-types.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include <mach/regs-irq.h>
#include <mach/bast-map.h>
#include <mach/bast-irq.h>
#include <plat/irq.h>
#if 0
#include <asm/debug-ll.h>
#endif
#include "bast.h"
#define irqdbf(x...)
#define irqdbf2(x...)
/* handle PC104 ISA interrupts from the system CPLD */
/* table of ISA irq nos to the relevant mask... zero means
@ -87,7 +80,7 @@ bast_pc104_mask(struct irq_data *data)
static void
bast_pc104_maskack(struct irq_data *data)
{
struct irq_desc *desc = irq_desc + IRQ_ISA;
struct irq_desc *desc = irq_desc + BAST_IRQ_ISA;
bast_pc104_mask(data);
desc->irq_data.chip->irq_ack(&desc->irq_data);
@ -122,7 +115,7 @@ bast_irq_pc104_demux(unsigned int irq,
if (unlikely(stat == 0)) {
/* ack if we get an irq with nothing (ie, startup) */
desc = irq_desc + IRQ_ISA;
desc = irq_desc + BAST_IRQ_ISA;
desc->irq_data.chip->irq_ack(&desc->irq_data);
} else {
/* handle the IRQ */
@ -147,7 +140,7 @@ static __init int bast_irq_init(void)
__raw_writeb(0x0, BAST_VA_PC104_IRQMASK);
irq_set_chained_handler(IRQ_ISA, bast_irq_pc104_demux);
irq_set_chained_handler(BAST_IRQ_ISA, bast_irq_pc104_demux);
/* register our IRQs */

197
arch/arm/mach-s3c24xx/bast.h Normal file
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@ -0,0 +1,197 @@
/*
* Copyright (c) 2003-2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* BAST - CPLD control constants
* BAST - IRQ Number definitions
* BAST - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __MACH_S3C24XX_BAST_H
#define __MACH_S3C24XX_BAST_H __FILE__
/* CTRL1 - Audio LR routing */
#define BAST_CPLD_CTRL1_LRCOFF (0x00)
#define BAST_CPLD_CTRL1_LRCADC (0x01)
#define BAST_CPLD_CTRL1_LRCDAC (0x02)
#define BAST_CPLD_CTRL1_LRCARM (0x03)
#define BAST_CPLD_CTRL1_LRMASK (0x03)
/* CTRL2 - NAND WP control, IDE Reset assert/check */
#define BAST_CPLD_CTRL2_WNAND (0x04)
#define BAST_CPLD_CTLR2_IDERST (0x08)
/* CTRL3 - rom write control, CPLD identity */
#define BAST_CPLD_CTRL3_IDMASK (0x0e)
#define BAST_CPLD_CTRL3_ROMWEN (0x01)
/* CTRL4 - 8bit LCD interface control/status */
#define BAST_CPLD_CTRL4_LLAT (0x01)
#define BAST_CPLD_CTRL4_LCDRW (0x02)
#define BAST_CPLD_CTRL4_LCDCMD (0x04)
#define BAST_CPLD_CTRL4_LCDE2 (0x01)
/* CTRL5 - DMA routing */
#define BAST_CPLD_DMA0_PRIIDE (0)
#define BAST_CPLD_DMA0_SECIDE (1)
#define BAST_CPLD_DMA0_ISA15 (2)
#define BAST_CPLD_DMA0_ISA36 (3)
#define BAST_CPLD_DMA1_PRIIDE (0 << 2)
#define BAST_CPLD_DMA1_SECIDE (1 << 2)
#define BAST_CPLD_DMA1_ISA15 (2 << 2)
#define BAST_CPLD_DMA1_ISA36 (3 << 2)
/* irq numbers to onboard peripherals */
#define BAST_IRQ_USBOC IRQ_EINT18
#define BAST_IRQ_IDE0 IRQ_EINT16
#define BAST_IRQ_IDE1 IRQ_EINT17
#define BAST_IRQ_PCSERIAL1 IRQ_EINT15
#define BAST_IRQ_PCSERIAL2 IRQ_EINT14
#define BAST_IRQ_PCPARALLEL IRQ_EINT13
#define BAST_IRQ_ASIX IRQ_EINT11
#define BAST_IRQ_DM9000 IRQ_EINT10
#define BAST_IRQ_ISA IRQ_EINT9
#define BAST_IRQ_SMALERT IRQ_EINT8
/* map */
/*
* ok, we've used up to 0x13000000, now we need to find space for the
* peripherals that live in the nGCS[x] areas, which are quite numerous
* in their space. We also have the board's CPLD to find register space
* for.
*/
#define BAST_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000))
/* we put the CPLD registers next, to get them out of the way */
#define BAST_VA_CTRL1 BAST_IOADDR(0x00000000)
#define BAST_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
#define BAST_VA_CTRL2 BAST_IOADDR(0x00100000)
#define BAST_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
#define BAST_VA_CTRL3 BAST_IOADDR(0x00200000)
#define BAST_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
#define BAST_VA_CTRL4 BAST_IOADDR(0x00300000)
#define BAST_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
/* next, we have the PC104 ISA interrupt registers */
#define BAST_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000)
#define BAST_VA_PC104_IRQREQ BAST_IOADDR(0x00400000)
#define BAST_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000)
#define BAST_VA_PC104_IRQRAW BAST_IOADDR(0x00500000)
#define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000)
#define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000)
#define BAST_PA_LCD_RCMD1 (0x8800000)
#define BAST_VA_LCD_RCMD1 BAST_IOADDR(0x00700000)
#define BAST_PA_LCD_WCMD1 (0x8000000)
#define BAST_VA_LCD_WCMD1 BAST_IOADDR(0x00800000)
#define BAST_PA_LCD_RDATA1 (0x9800000)
#define BAST_VA_LCD_RDATA1 BAST_IOADDR(0x00900000)
#define BAST_PA_LCD_WDATA1 (0x9000000)
#define BAST_VA_LCD_WDATA1 BAST_IOADDR(0x00A00000)
#define BAST_PA_LCD_RCMD2 (0xA800000)
#define BAST_VA_LCD_RCMD2 BAST_IOADDR(0x00B00000)
#define BAST_PA_LCD_WCMD2 (0xA000000)
#define BAST_VA_LCD_WCMD2 BAST_IOADDR(0x00C00000)
#define BAST_PA_LCD_RDATA2 (0xB800000)
#define BAST_VA_LCD_RDATA2 BAST_IOADDR(0x00D00000)
#define BAST_PA_LCD_WDATA2 (0xB000000)
#define BAST_VA_LCD_WDATA2 BAST_IOADDR(0x00E00000)
/*
* 0xE0000000 contains the IO space that is split by speed and
* whether the access is for 8 or 16bit IO... this ensures that
* the correct access is made
*
* 0x10000000 of space, partitioned as so:
*
* 0x00000000 to 0x04000000 8bit, slow
* 0x04000000 to 0x08000000 16bit, slow
* 0x08000000 to 0x0C000000 16bit, net
* 0x0C000000 to 0x10000000 16bit, fast
*
* each of these spaces has the following in:
*
* 0x00000000 to 0x01000000 16MB ISA IO space
* 0x01000000 to 0x02000000 16MB ISA memory space
* 0x02000000 to 0x02100000 1MB IDE primary channel
* 0x02100000 to 0x02200000 1MB IDE primary channel aux
* 0x02200000 to 0x02400000 1MB IDE secondary channel
* 0x02300000 to 0x02400000 1MB IDE secondary channel aux
* 0x02400000 to 0x02500000 1MB ASIX ethernet controller
* 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controller
* 0x02600000 to 0x02700000 1MB PC SuperIO controller
*
* the phyiscal layout of the zones are:
* nGCS2 - 8bit, slow
* nGCS3 - 16bit, slow
* nGCS4 - 16bit, net
* nGCS5 - 16bit, fast
*/
#define BAST_VA_MULTISPACE (0xE0000000)
#define BAST_VA_ISAIO (BAST_VA_MULTISPACE + 0x00000000)
#define BAST_VA_ISAMEM (BAST_VA_MULTISPACE + 0x01000000)
#define BAST_VA_IDEPRI (BAST_VA_MULTISPACE + 0x02000000)
#define BAST_VA_IDEPRIAUX (BAST_VA_MULTISPACE + 0x02100000)
#define BAST_VA_IDESEC (BAST_VA_MULTISPACE + 0x02200000)
#define BAST_VA_IDESECAUX (BAST_VA_MULTISPACE + 0x02300000)
#define BAST_VA_ASIXNET (BAST_VA_MULTISPACE + 0x02400000)
#define BAST_VA_DM9000 (BAST_VA_MULTISPACE + 0x02500000)
#define BAST_VA_SUPERIO (BAST_VA_MULTISPACE + 0x02600000)
#define BAST_VAM_CS2 (0x00000000)
#define BAST_VAM_CS3 (0x04000000)
#define BAST_VAM_CS4 (0x08000000)
#define BAST_VAM_CS5 (0x0C000000)
/* physical offset addresses for the peripherals */
#define BAST_PA_ISAIO (0x00000000)
#define BAST_PA_ASIXNET (0x01000000)
#define BAST_PA_SUPERIO (0x01800000)
#define BAST_PA_IDEPRI (0x02000000)
#define BAST_PA_IDEPRIAUX (0x02800000)
#define BAST_PA_IDESEC (0x03000000)
#define BAST_PA_IDESECAUX (0x03800000)
#define BAST_PA_ISAMEM (0x04000000)
#define BAST_PA_DM9000 (0x05000000)
/* some configurations for the peripherals */
#define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2)
#define BAST_ASIXNET_CS BAST_VAM_CS5
#define BAST_DM9000_CS BAST_VAM_CS4
#define BAST_IDE_CS S3C2410_CS5
#endif /* __MACH_S3C24XX_BAST_H */

14
arch/arm/mach-s3c24xx/include/mach/gta02.h → arch/arm/mach-s3c24xx/gta02.h
View File

@ -1,5 +1,13 @@
#ifndef _GTA02_H
#define _GTA02_H
/*
* GTA02 header
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __MACH_S3C24XX_GTA02_H
#define __MACH_S3C24XX_GTA02_H __FILE__
#include <mach/regs-gpio.h>
@ -12,4 +20,4 @@
#define GTA02_IRQ_PCF50633 IRQ_EINT9
#endif /* _GTA02_H */
#endif /* __MACH_S3C24XX_GTA02_H */

6
arch/arm/mach-s3c24xx/h1940-bluetooth.c
View File

@ -19,10 +19,10 @@
#include <linux/gpio.h>
#include <linux/rfkill.h>
#include <mach/regs-gpio.h>
#include <mach/hardware.h>
#include <mach/h1940-latch.h>
#include <mach/h1940.h>
#include <mach/regs-gpio.h>
#include "h1940.h"
#define DRV_NAME "h1940-bt"

22
arch/arm/mach-s3c24xx/include/mach/h1940-latch.h → arch/arm/mach-s3c24xx/h1940.h
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@ -1,20 +1,30 @@
/* arch/arm/mach-s3c2410/include/mach/h1940-latch.h
/*
* Copyright 2006 Ben Dooks <ben-linux@fluff.org>
*
* Copyright (c) 2005 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* iPAQ H1940 series - latch definitions
* iPAQ H1940 series definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_H1940_LATCH_H
#define __ASM_ARCH_H1940_LATCH_H
#ifndef __MACH_S3C24XX_H1940_H
#define __MACH_S3C24XX_H1940_H __FILE__
#include <asm/gpio.h>
#define H1940_SUSPEND_CHECKSUM (0x30003ff8)
#define H1940_SUSPEND_RESUMEAT (0x30081000)
#define H1940_SUSPEND_CHECK (0x30080000)
extern void h1940_pm_return(void);
extern int h1940_led_blink_set(unsigned gpio, int state,
unsigned long *delay_on,
unsigned long *delay_off);
#include <linux/gpio.h>
#define H1940_LATCH_GPIO(x) (S3C_GPIO_END + (x))
@ -40,4 +50,4 @@
#define H1940_LATCH_LED_GREEN H1940_LATCH_GPIO(14)
#define H1940_LATCH_LED_FLASH H1940_LATCH_GPIO(15)
#endif /* __ASM_ARCH_H1940_LATCH_H */
#endif /* __MACH_S3C24XX_H1940_H */

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arch/arm/mach-s3c24xx/include/mach/anubis-cpld.h
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/* arch/arm/mach-s3c2410/include/mach/anubis-cpld.h
*
* Copyright (c) 2005 Simtec Electronics
* http://www.simtec.co.uk/products/
* Ben Dooks <ben@simtec.co.uk>
*
* ANUBIS - CPLD control constants
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_ANUBISCPLD_H
#define __ASM_ARCH_ANUBISCPLD_H
/* CTRL2 - NAND WP control, IDE Reset assert/check */
#define ANUBIS_CTRL1_NANDSEL (0x3)
/* IDREG - revision */
#define ANUBIS_IDREG_REVMASK (0x7)
#endif /* __ASM_ARCH_ANUBISCPLD_H */

21
arch/arm/mach-s3c24xx/include/mach/anubis-irq.h
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/* arch/arm/mach-s3c2410/include/mach/anubis-irq.h
*
* Copyright (c) 2005 Simtec Electronics
* http://www.simtec.co.uk/products/
* Ben Dooks <ben@simtec.co.uk>
*
* ANUBIS - IRQ Number definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_ANUBISIRQ_H
#define __ASM_ARCH_ANUBISIRQ_H
#define IRQ_IDE0 IRQ_EINT2
#define IRQ_IDE1 IRQ_EINT3
#define IRQ_ASIX IRQ_EINT1
#endif /* __ASM_ARCH_ANUBISIRQ_H */

38
arch/arm/mach-s3c24xx/include/mach/anubis-map.h
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@ -1,38 +0,0 @@
/* arch/arm/mach-s3c2410/include/mach/anubis-map.h
*
* Copyright (c) 2005 Simtec Electronics
* http://www.simtec.co.uk/products/
* Ben Dooks <ben@simtec.co.uk>
*
* ANUBIS - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* needs arch/map.h including with this */
#ifndef __ASM_ARCH_ANUBISMAP_H
#define __ASM_ARCH_ANUBISMAP_H
/* start peripherals off after the S3C2410 */
#define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x01800000))
#define ANUBIS_PA_CPLD (S3C2410_CS1 | (1<<26))
/* we put the CPLD registers next, to get them out of the way */
#define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000) /* 0x01800000 */
#define ANUBIS_PA_CTRL1 (ANUBIS_PA_CPLD)
#define ANUBIS_VA_IDREG ANUBIS_IOADDR(0x00300000) /* 0x01B00000 */
#define ANUBIS_PA_IDREG (ANUBIS_PA_CPLD + (3<<23))
#define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000)
#define ANUBIS_IDEPRIAUX ANUBIS_IOADDR(0x01100000)
#define ANUBIS_IDESEC ANUBIS_IOADDR(0x01200000)
#define ANUBIS_IDESECAUX ANUBIS_IOADDR(0x01300000)
#endif /* __ASM_ARCH_ANUBISMAP_H */

53
arch/arm/mach-s3c24xx/include/mach/bast-cpld.h
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@ -1,53 +0,0 @@
/* arch/arm/mach-s3c2410/include/mach/bast-cpld.h
*
* Copyright (c) 2003-2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* BAST - CPLD control constants
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_BASTCPLD_H
#define __ASM_ARCH_BASTCPLD_H
/* CTRL1 - Audio LR routing */
#define BAST_CPLD_CTRL1_LRCOFF (0x00)
#define BAST_CPLD_CTRL1_LRCADC (0x01)
#define BAST_CPLD_CTRL1_LRCDAC (0x02)
#define BAST_CPLD_CTRL1_LRCARM (0x03)
#define BAST_CPLD_CTRL1_LRMASK (0x03)
/* CTRL2 - NAND WP control, IDE Reset assert/check */
#define BAST_CPLD_CTRL2_WNAND (0x04)
#define BAST_CPLD_CTLR2_IDERST (0x08)
/* CTRL3 - rom write control, CPLD identity */
#define BAST_CPLD_CTRL3_IDMASK (0x0e)
#define BAST_CPLD_CTRL3_ROMWEN (0x01)
/* CTRL4 - 8bit LCD interface control/status */
#define BAST_CPLD_CTRL4_LLAT (0x01)
#define BAST_CPLD_CTRL4_LCDRW (0x02)
#define BAST_CPLD_CTRL4_LCDCMD (0x04)
#define BAST_CPLD_CTRL4_LCDE2 (0x01)
/* CTRL5 - DMA routing */
#define BAST_CPLD_DMA0_PRIIDE (0<<0)
#define BAST_CPLD_DMA0_SECIDE (1<<0)
#define BAST_CPLD_DMA0_ISA15 (2<<0)
#define BAST_CPLD_DMA0_ISA36 (3<<0)
#define BAST_CPLD_DMA1_PRIIDE (0<<2)
#define BAST_CPLD_DMA1_SECIDE (1<<2)
#define BAST_CPLD_DMA1_ISA15 (2<<2)
#define BAST_CPLD_DMA1_ISA36 (3<<2)
#endif /* __ASM_ARCH_BASTCPLD_H */

29
arch/arm/mach-s3c24xx/include/mach/bast-irq.h
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@ -1,29 +0,0 @@
/* arch/arm/mach-s3c2410/include/mach/bast-irq.h
*
* Copyright (c) 2003-2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Machine BAST - IRQ Number definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_BASTIRQ_H
#define __ASM_ARCH_BASTIRQ_H
/* irq numbers to onboard peripherals */
#define IRQ_USBOC IRQ_EINT18
#define IRQ_IDE0 IRQ_EINT16
#define IRQ_IDE1 IRQ_EINT17
#define IRQ_PCSERIAL1 IRQ_EINT15
#define IRQ_PCSERIAL2 IRQ_EINT14
#define IRQ_PCPARALLEL IRQ_EINT13
#define IRQ_ASIX IRQ_EINT11
#define IRQ_DM9000 IRQ_EINT10
#define IRQ_ISA IRQ_EINT9
#define IRQ_SMALERT IRQ_EINT8
#endif /* __ASM_ARCH_BASTIRQ_H */

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arch/arm/mach-s3c24xx/include/mach/bast-map.h
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@ -1,146 +0,0 @@
/* arch/arm/mach-s3c2410/include/mach/bast-map.h
*
* Copyright (c) 2003-2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Machine BAST - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* needs arch/map.h including with this */
/* ok, we've used up to 0x13000000, now we need to find space for the
* peripherals that live in the nGCS[x] areas, which are quite numerous
* in their space. We also have the board's CPLD to find register space
* for.
*/
#ifndef __ASM_ARCH_BASTMAP_H
#define __ASM_ARCH_BASTMAP_H
#define BAST_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000))
/* we put the CPLD registers next, to get them out of the way */
#define BAST_VA_CTRL1 BAST_IOADDR(0x00000000) /* 0x01300000 */
#define BAST_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
#define BAST_VA_CTRL2 BAST_IOADDR(0x00100000) /* 0x01400000 */
#define BAST_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
#define BAST_VA_CTRL3 BAST_IOADDR(0x00200000) /* 0x01500000 */
#define BAST_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
#define BAST_VA_CTRL4 BAST_IOADDR(0x00300000) /* 0x01600000 */
#define BAST_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
/* next, we have the PC104 ISA interrupt registers */
#define BAST_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
#define BAST_VA_PC104_IRQREQ BAST_IOADDR(0x00400000)
#define BAST_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
#define BAST_VA_PC104_IRQRAW BAST_IOADDR(0x00500000)
#define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
#define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000)
#define BAST_PA_LCD_RCMD1 (0x8800000)
#define BAST_VA_LCD_RCMD1 BAST_IOADDR(0x00700000)
#define BAST_PA_LCD_WCMD1 (0x8000000)
#define BAST_VA_LCD_WCMD1 BAST_IOADDR(0x00800000)
#define BAST_PA_LCD_RDATA1 (0x9800000)
#define BAST_VA_LCD_RDATA1 BAST_IOADDR(0x00900000)
#define BAST_PA_LCD_WDATA1 (0x9000000)
#define BAST_VA_LCD_WDATA1 BAST_IOADDR(0x00A00000)
#define BAST_PA_LCD_RCMD2 (0xA800000)
#define BAST_VA_LCD_RCMD2 BAST_IOADDR(0x00B00000)
#define BAST_PA_LCD_WCMD2 (0xA000000)
#define BAST_VA_LCD_WCMD2 BAST_IOADDR(0x00C00000)
#define BAST_PA_LCD_RDATA2 (0xB800000)
#define BAST_VA_LCD_RDATA2 BAST_IOADDR(0x00D00000)
#define BAST_PA_LCD_WDATA2 (0xB000000)
#define BAST_VA_LCD_WDATA2 BAST_IOADDR(0x00E00000)
/* 0xE0000000 contains the IO space that is split by speed and
* whether the access is for 8 or 16bit IO... this ensures that
* the correct access is made
*
* 0x10000000 of space, partitioned as so:
*
* 0x00000000 to 0x04000000 8bit, slow
* 0x04000000 to 0x08000000 16bit, slow
* 0x08000000 to 0x0C000000 16bit, net
* 0x0C000000 to 0x10000000 16bit, fast
*
* each of these spaces has the following in:
*
* 0x00000000 to 0x01000000 16MB ISA IO space
* 0x01000000 to 0x02000000 16MB ISA memory space
* 0x02000000 to 0x02100000 1MB IDE primary channel
* 0x02100000 to 0x02200000 1MB IDE primary channel aux
* 0x02200000 to 0x02400000 1MB IDE secondary channel
* 0x02300000 to 0x02400000 1MB IDE secondary channel aux
* 0x02400000 to 0x02500000 1MB ASIX ethernet controller
* 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controller
* 0x02600000 to 0x02700000 1MB PC SuperIO controller
*
* the phyiscal layout of the zones are:
* nGCS2 - 8bit, slow
* nGCS3 - 16bit, slow
* nGCS4 - 16bit, net
* nGCS5 - 16bit, fast
*/
#define BAST_VA_MULTISPACE (0xE0000000)
#define BAST_VA_ISAIO (BAST_VA_MULTISPACE + 0x00000000)
#define BAST_VA_ISAMEM (BAST_VA_MULTISPACE + 0x01000000)
#define BAST_VA_IDEPRI (BAST_VA_MULTISPACE + 0x02000000)
#define BAST_VA_IDEPRIAUX (BAST_VA_MULTISPACE + 0x02100000)
#define BAST_VA_IDESEC (BAST_VA_MULTISPACE + 0x02200000)
#define BAST_VA_IDESECAUX (BAST_VA_MULTISPACE + 0x02300000)
#define BAST_VA_ASIXNET (BAST_VA_MULTISPACE + 0x02400000)
#define BAST_VA_DM9000 (BAST_VA_MULTISPACE + 0x02500000)
#define BAST_VA_SUPERIO (BAST_VA_MULTISPACE + 0x02600000)
#define BAST_VA_MULTISPACE (0xE0000000)
#define BAST_VAM_CS2 (0x00000000)
#define BAST_VAM_CS3 (0x04000000)
#define BAST_VAM_CS4 (0x08000000)
#define BAST_VAM_CS5 (0x0C000000)
/* physical offset addresses for the peripherals */
#define BAST_PA_ISAIO (0x00000000)
#define BAST_PA_ASIXNET (0x01000000)
#define BAST_PA_SUPERIO (0x01800000)
#define BAST_PA_IDEPRI (0x02000000)
#define BAST_PA_IDEPRIAUX (0x02800000)
#define BAST_PA_IDESEC (0x03000000)
#define BAST_PA_IDESECAUX (0x03800000)
#define BAST_PA_ISAMEM (0x04000000)
#define BAST_PA_DM9000 (0x05000000)
/* some configurations for the peripherals */
#define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2)
/* */
#define BAST_ASIXNET_CS BAST_VAM_CS5
#define BAST_IDE_CS BAST_VAM_CS5
#define BAST_DM9000_CS BAST_VAM_CS4
#endif /* __ASM_ARCH_BASTMAP_H */

1
arch/arm/mach-s3c24xx/include/mach/gpio-fns.h
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@ -1 +0,0 @@
#include <plat/gpio-fns.h>

97
arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h
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@ -1,97 +0,0 @@
/* arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
*
* Copyright (c) 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 - GPIO bank numbering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __MACH_GPIONRS_H
#define __MACH_GPIONRS_H
#define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
#define S3C2410_GPIO_BANKG (32*6)
#define S3C2410_GPIO_BANKH (32*7)
/* GPIO sizes for various SoCs:
*
* 2442
* 2410 2412 2440 2443 2416
* ---- ---- ---- ---- ----
* A 23 22 25 16 25
* B 11 11 11 11 9
* C 16 15 16 16 16
* D 16 16 16 16 16
* E 16 16 16 16 16
* F 8 8 8 8 8
* G 16 16 16 16 8
* H 11 11 9 15 15
* J -- -- 13 16 --
* K -- -- -- -- 16
* L -- -- -- 15 7
* M -- -- -- 2 2
*/
/* GPIO bank sizes */
#define S3C2410_GPIO_A_NR (32)
#define S3C2410_GPIO_B_NR (32)
#define S3C2410_GPIO_C_NR (32)
#define S3C2410_GPIO_D_NR (32)
#define S3C2410_GPIO_E_NR (32)
#define S3C2410_GPIO_F_NR (32)
#define S3C2410_GPIO_G_NR (32)
#define S3C2410_GPIO_H_NR (32)
#define S3C2410_GPIO_J_NR (32) /* technically 16. */
#define S3C2410_GPIO_K_NR (32) /* technically 16. */
#define S3C2410_GPIO_L_NR (32) /* technically 15. */
#define S3C2410_GPIO_M_NR (32) /* technically 2. */
#if CONFIG_S3C_GPIO_SPACE != 0
#error CONFIG_S3C_GPIO_SPACE cannot be nonzero at the moment
#endif
#define S3C2410_GPIO_NEXT(__gpio) \
((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 0)
#ifndef __ASSEMBLY__
enum s3c_gpio_number {
S3C2410_GPIO_A_START = 0,
S3C2410_GPIO_B_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_A),
S3C2410_GPIO_C_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_B),
S3C2410_GPIO_D_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_C),
S3C2410_GPIO_E_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_D),
S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E),
S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F),
S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G),
S3C2410_GPIO_J_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_H),
S3C2410_GPIO_K_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_J),
S3C2410_GPIO_L_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_K),
S3C2410_GPIO_M_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_L),
};
#endif /* __ASSEMBLY__ */
/* S3C2410 GPIO number definitions. */
#define S3C2410_GPA(_nr) (S3C2410_GPIO_A_START + (_nr))
#define S3C2410_GPB(_nr) (S3C2410_GPIO_B_START + (_nr))
#define S3C2410_GPC(_nr) (S3C2410_GPIO_C_START + (_nr))
#define S3C2410_GPD(_nr) (S3C2410_GPIO_D_START + (_nr))
#define S3C2410_GPE(_nr) (S3C2410_GPIO_E_START + (_nr))
#define S3C2410_GPF(_nr) (S3C2410_GPIO_F_START + (_nr))
#define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr))
#define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr))
#define S3C2410_GPJ(_nr) (S3C2410_GPIO_J_START + (_nr))
#define S3C2410_GPK(_nr) (S3C2410_GPIO_K_START + (_nr))
#define S3C2410_GPL(_nr) (S3C2410_GPIO_L_START + (_nr))
#define S3C2410_GPM(_nr) (S3C2410_GPIO_M_START + (_nr))
#endif /* __MACH_GPIONRS_H */

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arch/arm/mach-s3c24xx/include/mach/gpio-track.h
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@ -1,33 +0,0 @@
/* arch/arm/mach-s3c24100/include/mach/gpio-core.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C2410 - GPIO core support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_GPIO_CORE_H
#define __ASM_ARCH_GPIO_CORE_H __FILE__
#include <mach/regs-gpio.h>
extern struct samsung_gpio_chip s3c24xx_gpios[];
static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int pin)
{
struct samsung_gpio_chip *chip;
if (pin > S3C_GPIO_END)
return NULL;
chip = &s3c24xx_gpios[pin/32];
return ((pin - chip->chip.base) < chip->chip.ngpio) ? chip : NULL;
}
#endif /* __ASM_ARCH_GPIO_CORE_H */

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arch/arm/mach-s3c24xx/include/mach/gpio.h
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@ -1,5 +1,4 @@
/* arch/arm/mach-s3c2410/include/mach/gpio.h
*
/*
* Copyright (c) 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
@ -15,6 +14,9 @@
* devices that need GPIO.
*/
#ifndef __MACH_GPIO_H
#define __MACH_GPIO_H __FILE__
#ifdef CONFIG_CPU_S3C244X
#define ARCH_NR_GPIOS (32 * 9 + CONFIG_S3C24XX_GPIO_EXTRA)
#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
@ -23,8 +25,83 @@
#define ARCH_NR_GPIOS (256 + CONFIG_S3C24XX_GPIO_EXTRA)
#endif
#include <mach/gpio-nrs.h>
#include <mach/gpio-fns.h>
/*
* GPIO sizes for various SoCs:
*
* 2410 2412 2440 2443 2416
* 2442
* ---- ---- ---- ---- ----
* A 23 22 25 16 25
* B 11 11 11 11 9
* C 16 15 16 16 16
* D 16 16 16 16 16
* E 16 16 16 16 16
* F 8 8 8 8 8
* G 16 16 16 16 8
* H 11 11 9 15 15
* J -- -- 13 16 --
* K -- -- -- -- 16
* L -- -- -- 15 7
* M -- -- -- 2 2
*/
/* GPIO bank sizes */
#define S3C2410_GPIO_A_NR (32)
#define S3C2410_GPIO_B_NR (32)
#define S3C2410_GPIO_C_NR (32)
#define S3C2410_GPIO_D_NR (32)
#define S3C2410_GPIO_E_NR (32)
#define S3C2410_GPIO_F_NR (32)
#define S3C2410_GPIO_G_NR (32)
#define S3C2410_GPIO_H_NR (32)
#define S3C2410_GPIO_J_NR (32) /* technically 16. */
#define S3C2410_GPIO_K_NR (32) /* technically 16. */
#define S3C2410_GPIO_L_NR (32) /* technically 15. */
#define S3C2410_GPIO_M_NR (32) /* technically 2. */
#if CONFIG_S3C_GPIO_SPACE != 0
#error CONFIG_S3C_GPIO_SPACE cannot be nonzero at the moment
#endif
#define S3C2410_GPIO_NEXT(__gpio) \
((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 0)
#ifndef __ASSEMBLY__
enum s3c_gpio_number {
S3C2410_GPIO_A_START = 0,
S3C2410_GPIO_B_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_A),
S3C2410_GPIO_C_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_B),
S3C2410_GPIO_D_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_C),
S3C2410_GPIO_E_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_D),
S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E),
S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F),
S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G),
S3C2410_GPIO_J_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_H),
S3C2410_GPIO_K_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_J),
S3C2410_GPIO_L_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_K),
S3C2410_GPIO_M_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_L),
};
#endif /* __ASSEMBLY__ */
/* S3C2410 GPIO number definitions. */
#define S3C2410_GPA(_nr) (S3C2410_GPIO_A_START + (_nr))
#define S3C2410_GPB(_nr) (S3C2410_GPIO_B_START + (_nr))
#define S3C2410_GPC(_nr) (S3C2410_GPIO_C_START + (_nr))
#define S3C2410_GPD(_nr) (S3C2410_GPIO_D_START + (_nr))
#define S3C2410_GPE(_nr) (S3C2410_GPIO_E_START + (_nr))
#define S3C2410_GPF(_nr) (S3C2410_GPIO_F_START + (_nr))
#define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr))
#define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr))
#define S3C2410_GPJ(_nr) (S3C2410_GPIO_J_START + (_nr))
#define S3C2410_GPK(_nr) (S3C2410_GPIO_K_START + (_nr))
#define S3C2410_GPL(_nr) (S3C2410_GPIO_L_START + (_nr))
#define S3C2410_GPM(_nr) (S3C2410_GPIO_M_START + (_nr))
#include <plat/gpio-cfg.h>
#ifdef CONFIG_CPU_S3C244X
#define S3C_GPIO_END (S3C2410_GPJ(0) + 32)
@ -33,3 +110,5 @@
#else
#define S3C_GPIO_END (S3C2410_GPH(0) + 32)
#endif
#endif /* __MACH_GPIO_H */

24
arch/arm/mach-s3c24xx/include/mach/h1940.h
View File

@ -1,24 +0,0 @@
/* arch/arm/mach-s3c2410/include/mach/h1940.h
*
* Copyright 2006 Ben Dooks <ben-linux@fluff.org>
*
* H1940 definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_H1940_H
#define __ASM_ARCH_H1940_H
#define H1940_SUSPEND_CHECKSUM (0x30003ff8)
#define H1940_SUSPEND_RESUMEAT (0x30081000)
#define H1940_SUSPEND_CHECK (0x30080000)
extern void h1940_pm_return(void);
extern int h1940_led_blink_set(unsigned gpio, int state,
unsigned long *delay_on, unsigned long *delay_off);
#endif /* __ASM_ARCH_H1940_H */

24
arch/arm/mach-s3c24xx/include/mach/idle.h
View File

@ -1,24 +0,0 @@
/* arch/arm/mach-s3c2410/include/mach/idle.h
*
* Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
* http://www.simtec.co.uk/products/SWLINUX/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C2410 CPU Idle controls
*/
#ifndef __ASM_ARCH_IDLE_H
#define __ASM_ARCH_IDLE_H __FILE__
/* This allows the over-ride of the default idle code, in case there
* is any other things to be done over idle (like DVS)
*/
extern void (*s3c24xx_idle)(void);
extern void s3c24xx_default_idle(void);
#endif /* __ASM_ARCH_IDLE_H */

30
arch/arm/mach-s3c24xx/include/mach/osiris-cpld.h
View File

@ -1,30 +0,0 @@
/* arch/arm/mach-s3c2410/include/mach/osiris-cpld.h
*
* Copyright 2005 Simtec Electronics
* http://www.simtec.co.uk/products/
* Ben Dooks <ben@simtec.co.uk>
*
* OSIRIS - CPLD control constants
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_OSIRISCPLD_H
#define __ASM_ARCH_OSIRISCPLD_H
/* CTRL0 - NAND WP control */
#define OSIRIS_CTRL0_NANDSEL (0x3)
#define OSIRIS_CTRL0_BOOT_INT (1<<3)
#define OSIRIS_CTRL0_PCMCIA (1<<4)
#define OSIRIS_CTRL0_FIX8 (1<<5)
#define OSIRIS_CTRL0_PCMCIA_nWAIT (1<<6)
#define OSIRIS_CTRL0_PCMCIA_nIOIS16 (1<<7)
#define OSIRIS_CTRL1_FIX8 (1<<0)
#define OSIRIS_ID_REVMASK (0x7)
#endif /* __ASM_ARCH_OSIRISCPLD_H */

2
arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
View File

@ -14,8 +14,6 @@
#ifndef __ASM_ARCH_REGS_GPIO_H
#define __ASM_ARCH_REGS_GPIO_H
#include <mach/gpio-nrs.h>
#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80)
/* general configuration options */

23
arch/arm/mach-s3c24xx/include/mach/regs-s3c2412.h
View File

@ -1,23 +0,0 @@
/* arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h
*
* Copyright 2007 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C2412 specific register definitions
*/
#ifndef __ASM_ARCH_REGS_S3C2412_H
#define __ASM_ARCH_REGS_S3C2412_H "s3c2412"
#define S3C2412_SWRST (S3C24XX_VA_CLKPWR + 0x30)
#define S3C2412_SWRST_RESET (0x533C2412)
/* see regs-power.h for the other registers in the power block. */
#endif /* __ASM_ARCH_REGS_S3C2412_H */

30
arch/arm/mach-s3c24xx/include/mach/regs-s3c2416-mem.h
View File

@ -1,30 +0,0 @@
/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h
*
* Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
* as part of OpenInkpot project
* Copyright (c) 2009 Promwad Innovation Company
* Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C2416 memory register definitions
*/
#ifndef __ASM_ARM_REGS_S3C2416_MEM
#define __ASM_ARM_REGS_S3C2416_MEM
#ifndef S3C2416_MEMREG
#define S3C2416_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
#endif
#define S3C2416_BANKCFG S3C2416_MEMREG(0x00)
#define S3C2416_BANKCON1 S3C2416_MEMREG(0x04)
#define S3C2416_BANKCON2 S3C2416_MEMREG(0x08)
#define S3C2416_BANKCON3 S3C2416_MEMREG(0x0C)
#define S3C2416_REFRESH S3C2416_MEMREG(0x10)
#define S3C2416_TIMEOUT S3C2416_MEMREG(0x14)
#endif /* __ASM_ARM_REGS_S3C2416_MEM */

24
arch/arm/mach-s3c24xx/include/mach/regs-s3c2416.h
View File

@ -1,24 +0,0 @@
/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h
*
* Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
* as part of OpenInkpot project
* Copyright (c) 2009 Promwad Innovation Company
* Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C2416 specific register definitions
*/
#ifndef __ASM_ARCH_REGS_S3C2416_H
#define __ASM_ARCH_REGS_S3C2416_H "s3c2416"
#define S3C2416_SWRST (S3C24XX_VA_CLKPWR + 0x44)
#define S3C2416_SWRST_RESET (0x533C2416)
/* see regs-power.h for the other registers in the power block. */
#endif /* __ASM_ARCH_REGS_S3C2416_H */

18
arch/arm/mach-s3c24xx/include/mach/vr1000-cpld.h
View File

@ -1,18 +0,0 @@
/* arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h
*
* Copyright (c) 2003 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* VR1000 - CPLD control constants
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_VR1000CPLD_H
#define __ASM_ARCH_VR1000CPLD_H
#define VR1000_CPLD_CTRL2_RAMWEN (0x04) /* SRAM Write Enable */
#endif /* __ASM_ARCH_VR1000CPLD_H */

26
arch/arm/mach-s3c24xx/include/mach/vr1000-irq.h
View File

@ -1,26 +0,0 @@
/* arch/arm/mach-s3c2410/include/mach/vr1000-irq.h
*
* Copyright (c) 2003-2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Machine VR1000 - IRQ Number definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_VR1000IRQ_H
#define __ASM_ARCH_VR1000IRQ_H
/* irq numbers to onboard peripherals */
#define IRQ_USBOC IRQ_EINT19
#define IRQ_IDE0 IRQ_EINT16
#define IRQ_IDE1 IRQ_EINT17
#define IRQ_VR1000_SERIAL IRQ_EINT12
#define IRQ_VR1000_DM9000A IRQ_EINT10
#define IRQ_VR1000_DM9000N IRQ_EINT9
#define IRQ_SMALERT IRQ_EINT8
#endif /* __ASM_ARCH_VR1000IRQ_H */

110
arch/arm/mach-s3c24xx/include/mach/vr1000-map.h
View File

@ -1,110 +0,0 @@
/* arch/arm/mach-s3c2410/include/mach/vr1000-map.h
*
* Copyright (c) 2003-2005 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Machine VR1000 - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* needs arch/map.h including with this */
/* ok, we've used up to 0x13000000, now we need to find space for the
* peripherals that live in the nGCS[x] areas, which are quite numerous
* in their space. We also have the board's CPLD to find register space
* for.
*/
#ifndef __ASM_ARCH_VR1000MAP_H
#define __ASM_ARCH_VR1000MAP_H
#include <mach/bast-map.h>
#define VR1000_IOADDR(x) BAST_IOADDR(x)
/* we put the CPLD registers next, to get them out of the way */
#define VR1000_VA_CTRL1 VR1000_IOADDR(0x00000000) /* 0x01300000 */
#define VR1000_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
#define VR1000_VA_CTRL2 VR1000_IOADDR(0x00100000) /* 0x01400000 */
#define VR1000_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
#define VR1000_VA_CTRL3 VR1000_IOADDR(0x00200000) /* 0x01500000 */
#define VR1000_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
#define VR1000_VA_CTRL4 VR1000_IOADDR(0x00300000) /* 0x01600000 */
#define VR1000_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
/* next, we have the PC104 ISA interrupt registers */
#define VR1000_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
#define VR1000_VA_PC104_IRQREQ VR1000_IOADDR(0x00400000)
#define VR1000_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
#define VR1000_VA_PC104_IRQRAW VR1000_IOADDR(0x00500000)
#define VR1000_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
#define VR1000_VA_PC104_IRQMASK VR1000_IOADDR(0x00600000)
/* 0xE0000000 contains the IO space that is split by speed and
* whether the access is for 8 or 16bit IO... this ensures that
* the correct access is made
*
* 0x10000000 of space, partitioned as so:
*
* 0x00000000 to 0x04000000 8bit, slow
* 0x04000000 to 0x08000000 16bit, slow
* 0x08000000 to 0x0C000000 16bit, net
* 0x0C000000 to 0x10000000 16bit, fast
*
* each of these spaces has the following in:
*
* 0x02000000 to 0x02100000 1MB IDE primary channel
* 0x02100000 to 0x02200000 1MB IDE primary channel aux
* 0x02200000 to 0x02400000 1MB IDE secondary channel
* 0x02300000 to 0x02400000 1MB IDE secondary channel aux
* 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controllers
* 0x02600000 to 0x02700000 1MB
*
* the phyiscal layout of the zones are:
* nGCS2 - 8bit, slow
* nGCS3 - 16bit, slow
* nGCS4 - 16bit, net
* nGCS5 - 16bit, fast
*/
#define VR1000_VA_MULTISPACE (0xE0000000)
#define VR1000_VA_ISAIO (VR1000_VA_MULTISPACE + 0x00000000)
#define VR1000_VA_ISAMEM (VR1000_VA_MULTISPACE + 0x01000000)
#define VR1000_VA_IDEPRI (VR1000_VA_MULTISPACE + 0x02000000)
#define VR1000_VA_IDEPRIAUX (VR1000_VA_MULTISPACE + 0x02100000)
#define VR1000_VA_IDESEC (VR1000_VA_MULTISPACE + 0x02200000)
#define VR1000_VA_IDESECAUX (VR1000_VA_MULTISPACE + 0x02300000)
#define VR1000_VA_ASIXNET (VR1000_VA_MULTISPACE + 0x02400000)
#define VR1000_VA_DM9000 (VR1000_VA_MULTISPACE + 0x02500000)
#define VR1000_VA_SUPERIO (VR1000_VA_MULTISPACE + 0x02600000)
/* physical offset addresses for the peripherals */
#define VR1000_PA_IDEPRI (0x02000000)
#define VR1000_PA_IDEPRIAUX (0x02800000)
#define VR1000_PA_IDESEC (0x03000000)
#define VR1000_PA_IDESECAUX (0x03800000)
#define VR1000_PA_DM9000 (0x05000000)
#define VR1000_PA_SERIAL (0x11800000)
#define VR1000_VA_SERIAL (VR1000_IOADDR(0x00700000))
/* VR1000 ram is in CS1, with A26..A24 = 2_101 */
#define VR1000_PA_SRAM (S3C2410_CS1 | 0x05000000)
/* some configurations for the peripherals */
#define VR1000_DM9000_CS VR1000_VAM_CS4
#endif /* __ASM_ARCH_VR1000MAP_H */

13
arch/arm/mach-s3c24xx/mach-anubis.c
View File

@ -28,10 +28,6 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/anubis-map.h>
#include <mach/anubis-irq.h>
#include <mach/anubis-cpld.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
@ -55,8 +51,9 @@
#include <plat/cpu.h>
#include <linux/platform_data/asoc-s3c24xx_simtec.h>
#include "simtec.h"
#include "anubis.h"
#include "common.h"
#include "simtec.h"
#define COPYRIGHT ", Copyright 2005-2009 Simtec Electronics"
@ -237,7 +234,7 @@ static struct pata_platform_info anubis_ide_platdata = {
static struct resource anubis_ide0_resource[] = {
[0] = DEFINE_RES_MEM(S3C2410_CS3, 8 * 32),
[2] = DEFINE_RES_MEM(S3C2410_CS3 + (1 << 26) + (6 * 32), 32),
[3] = DEFINE_RES_IRQ(IRQ_IDE0),
[3] = DEFINE_RES_IRQ(ANUBIS_IRQ_IDE0),
};
static struct platform_device anubis_device_ide0 = {
@ -254,7 +251,7 @@ static struct platform_device anubis_device_ide0 = {
static struct resource anubis_ide1_resource[] = {
[0] = DEFINE_RES_MEM(S3C2410_CS4, 8 * 32),
[1] = DEFINE_RES_MEM(S3C2410_CS4 + (1 << 26) + (6 * 32), 32),
[2] = DEFINE_RES_IRQ(IRQ_IDE0),
[2] = DEFINE_RES_IRQ(ANUBIS_IRQ_IDE0),
};
static struct platform_device anubis_device_ide1 = {
@ -279,7 +276,7 @@ static struct ax_plat_data anubis_asix_platdata = {
static struct resource anubis_asix_resource[] = {
[0] = DEFINE_RES_MEM(S3C2410_CS5, 0x20 * 0x20),
[1] = DEFINE_RES_IRQ(IRQ_ASIX),
[1] = DEFINE_RES_IRQ(ANUBIS_IRQ_ASIX),
};
static struct platform_device anubis_device_asix = {

1
arch/arm/mach-s3c24xx/mach-at2440evb.c
View File

@ -14,6 +14,7 @@
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>

60
arch/arm/mach-s3c24xx/mach-bast.c
View File

@ -24,48 +24,42 @@
#include <linux/ata_platform.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <net/ax88796.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/bast-map.h>
#include <mach/bast-irq.h>
#include <mach/bast-cpld.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
//#include <asm/debug-ll.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <linux/platform_data/hwmon-s3c.h>
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <linux/platform_data/i2c-s3c2410.h>
#include <mach/fb.h>
#include <linux/serial_8250.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>
#include <linux/serial_8250.h>
#include <linux/platform_data/asoc-s3c24xx_simtec.h>
#include <linux/platform_data/hwmon-s3c.h>
#include <linux/platform_data/i2c-s3c2410.h>
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <net/ax88796.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/mach-types.h>
#include <mach/fb.h>
#include <mach/hardware.h>
#include <mach/regs-gpio.h>
#include <mach/regs-lcd.h>
#include <mach/regs-mem.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/cpu-freq.h>
#include <plat/devs.h>
#include <plat/gpio-cfg.h>
#include <linux/platform_data/asoc-s3c24xx_simtec.h>
#include <plat/regs-serial.h>
#include "simtec.h"
#include "bast.h"
#include "common.h"
#include "simtec.h"
#define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
@ -312,7 +306,7 @@ static struct s3c2410_platform_nand __initdata bast_nand_info = {
static struct resource bast_dm9k_resource[] = {
[0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000, 4),
[1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000 + 0x40, 0x40),
[2] = DEFINE_RES_NAMED(IRQ_DM9000 , 1, NULL, IORESOURCE_IRQ \
[2] = DEFINE_RES_NAMED(BAST_IRQ_DM9000 , 1, NULL, IORESOURCE_IRQ \
| IORESOURCE_IRQ_HIGHLEVEL),
};
@ -343,7 +337,7 @@ static struct platform_device bast_device_dm9k = {
static struct plat_serial8250_port bast_sio_data[] = {
[0] = {
.mapbase = SERIAL_BASE + 0x2f8,
.irq = IRQ_PCSERIAL1,
.irq = BAST_IRQ_PCSERIAL1,
.flags = SERIAL_FLAGS,
.iotype = UPIO_MEM,
.regshift = 0,
@ -351,7 +345,7 @@ static struct plat_serial8250_port bast_sio_data[] = {
},
[1] = {
.mapbase = SERIAL_BASE + 0x3f8,
.irq = IRQ_PCSERIAL2,
.irq = BAST_IRQ_PCSERIAL2,
.flags = SERIAL_FLAGS,
.iotype = UPIO_MEM,
.regshift = 0,
@ -390,7 +384,7 @@ static struct ax_plat_data bast_asix_platdata = {
static struct resource bast_asix_resource[] = {
[0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET, 0x18 * 0x20),
[1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20), 1),
[2] = DEFINE_RES_IRQ(IRQ_ASIX),
[2] = DEFINE_RES_IRQ(BAST_IRQ_ASIX),
};
static struct platform_device bast_device_asix = {

67
arch/arm/mach-s3c24xx/mach-gta02.c
View File

@ -1,6 +1,4 @@
/*
* linux/arch/arm/mach-s3c2442/mach-gta02.c
*
* S3C2442 Machine Support for Openmoko GTA02 / FreeRunner.
*
* Copyright (C) 2006-2009 by Openmoko, Inc.
@ -23,7 +21,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <linux/kernel.h>
@ -34,62 +31,60 @@
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
#include <linux/workqueue.h>
#include <linux/platform_device.h>
#include <linux/serial_core.h>
#include <linux/spi/spi.h>
#include <linux/spi/s3c24xx.h>
#include <linux/input.h>
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/mmc/host.h>
#include <linux/mfd/pcf50633/adc.h>
#include <linux/mfd/pcf50633/backlight.h>
#include <linux/mfd/pcf50633/core.h>
#include <linux/mfd/pcf50633/gpio.h>
#include <linux/mfd/pcf50633/mbc.h>
#include <linux/mfd/pcf50633/pmic.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/regulator/machine.h>
#include <linux/mfd/pcf50633/core.h>
#include <linux/mfd/pcf50633/mbc.h>
#include <linux/mfd/pcf50633/adc.h>
#include <linux/mfd/pcf50633/gpio.h>
#include <linux/mfd/pcf50633/pmic.h>
#include <linux/mfd/pcf50633/backlight.h>
#include <linux/input.h>
#include <linux/gpio_keys.h>
#include <linux/spi/spi.h>
#include <linux/spi/s3c24xx.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <mach/regs-irq.h>
#include <mach/regs-gpio.h>
#include <mach/fb.h>
#include <linux/platform_data/usb-ohci-s3c2410.h>
#include <mach/regs-mem.h>
#include <mach/hardware.h>
#include <mach/gta02.h>
#include <plat/regs-serial.h>
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/pm.h>
#include <linux/platform_data/usb-s3c2410_udc.h>
#include <plat/gpio-cfg.h>
#include <linux/platform_data/i2c-s3c2410.h>
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <linux/platform_data/touchscreen-s3c2410.h>
#include <linux/platform_data/usb-ohci-s3c2410.h>
#include <linux/platform_data/usb-s3c2410_udc.h>
#include <mach/fb.h>
#include <mach/hardware.h>
#include <mach/regs-gpio.h>
#include <mach/regs-irq.h>
#include <mach/regs-mem.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/gpio-cfg.h>
#include <plat/pm.h>
#include <plat/regs-serial.h>
#include "common.h"
#include "gta02.h"
static struct pcf50633 *gta02_pcf;

45
arch/arm/mach-s3c24xx/mach-h1940.c
View File

@ -1,5 +1,4 @@
/* linux/arch/arm/mach-s3c2410/mach-h1940.c
*
/*
* Copyright (c) 2003-2005 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
@ -37,40 +36,36 @@
#include <linux/mmc/host.h>
#include <linux/export.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
#include <mach/regs-lcd.h>
#include <mach/regs-clock.h>
#include <mach/regs-gpio.h>
#include <mach/gpio-fns.h>
#include <mach/gpio-nrs.h>
#include <mach/h1940.h>
#include <mach/h1940-latch.h>
#include <mach/fb.h>
#include <linux/platform_data/usb-s3c2410_udc.h>
#include <linux/platform_data/i2c-s3c2410.h>
#include <plat/gpio-cfg.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/pll.h>
#include <plat/pm.h>
#include <linux/platform_data/mmc-s3cmci.h>
#include <linux/platform_data/touchscreen-s3c2410.h>
#include <linux/platform_data/usb-s3c2410_udc.h>
#include <sound/uda1380.h>
#include <mach/fb.h>
#include <mach/hardware.h>
#include <mach/regs-clock.h>
#include <mach/regs-gpio.h>
#include <mach/regs-lcd.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/gpio-cfg.h>
#include <plat/pll.h>
#include <plat/pm.h>
#include <plat/regs-serial.h>
#include "common.h"
#include "h1940.h"
#define H1940_LATCH ((void __force __iomem *)0xF8000000)

27
arch/arm/mach-s3c24xx/mach-osiris.c
View File

@ -1,5 +1,4 @@
/* linux/arch/arm/mach-s3c2440/mach-osiris.c
*
/*
* Copyright (c) 2005-2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
@ -25,22 +24,12 @@
#include <linux/i2c/tps65010.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/osiris-map.h>
#include <mach/osiris-cpld.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <plat/cpu-freq.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <linux/platform_data/i2c-s3c2410.h>
@ -49,12 +38,20 @@
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>
#include <plat/gpio-cfg.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/cpu-freq.h>
#include <plat/devs.h>
#include <plat/gpio-cfg.h>
#include <plat/regs-serial.h>
#include <mach/hardware.h>
#include <mach/regs-gpio.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include "common.h"
#include "osiris.h"
/* onboard perihperal map */

20
arch/arm/mach-s3c24xx/mach-otom.c
View File

@ -1,4 +1,4 @@
/* linux/arch/arm/mach-s3c2410/mach-otom.c
/*
*
* Copyright (c) 2004 Nex Vision
* Guillaume GOURAT <guillaume.gourat@nexvision.fr>
@ -6,7 +6,6 @@
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/kernel.h>
@ -19,26 +18,25 @@
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/platform_data/i2c-s3c2410.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/otom-map.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <plat/s3c2410.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <linux/platform_data/i2c-s3c2410.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/regs-serial.h>
#include <plat/s3c2410.h>
#include "common.h"
#include "otom.h"
static struct map_desc otom11_iodesc[] __initdata = {
/* Device area */

35
arch/arm/mach-s3c24xx/mach-rx1950.c
View File

@ -1,5 +1,4 @@
/* linux/arch/arm/mach-s3c2440/mach-rx1950.c
*
/*
* Copyright (c) 2006-2009 Victor Chukhantsev, Denis Grigoriev,
* Copyright (c) 2007-2010 Vasily Khoruzhick
*
@ -37,31 +36,31 @@
#include <linux/mmc/host.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach-types.h>
#include <mach/regs-gpio.h>
#include <mach/regs-lcd.h>
#include <mach/h1940.h>
#include <mach/fb.h>
#include <plat/clock.h>
#include <plat/regs-serial.h>
#include <plat/regs-iic.h>
#include <linux/platform_data/mmc-s3cmci.h>
#include <linux/platform_data/usb-s3c2410_udc.h>
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <linux/platform_data/i2c-s3c2410.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/pm.h>
#include <plat/irq.h>
#include <linux/platform_data/mmc-s3cmci.h>
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <linux/platform_data/touchscreen-s3c2410.h>
#include <linux/platform_data/usb-s3c2410_udc.h>
#include <sound/uda1380.h>
#include <mach/fb.h>
#include <mach/regs-gpio.h>
#include <mach/regs-lcd.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/pm.h>
#include <plat/regs-iic.h>
#include <plat/regs-serial.h>
#include "common.h"
#include "h1940.h"
#define LCD_PWM_PERIOD 192960
#define LCD_PWM_DUTY 127353

16
arch/arm/mach-s3c24xx/mach-rx3715.c
View File

@ -31,27 +31,27 @@
#include <linux/mtd/partitions.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
#include <mach/fb.h>
#include <mach/hardware.h>
#include <mach/regs-gpio.h>
#include <mach/regs-lcd.h>
#include <mach/h1940.h>
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <mach/fb.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/pm.h>
#include <plat/regs-serial.h>
#include "common.h"
#include "h1940.h"
static struct map_desc rx3715_iodesc[] __initdata = {
/* dump ISA space somewhere unused */

1
arch/arm/mach-s3c24xx/mach-smdk2413.c
View File

@ -37,7 +37,6 @@
#include <mach/regs-gpio.h>
#include <mach/regs-lcd.h>
#include <mach/idle.h>
#include <linux/platform_data/usb-s3c2410_udc.h>
#include <linux/platform_data/i2c-s3c2410.h>
#include <mach/fb.h>

1
arch/arm/mach-s3c24xx/mach-smdk2416.c
View File

@ -39,7 +39,6 @@
#include <mach/regs-lcd.h>
#include <mach/regs-s3c2443-clock.h>
#include <mach/idle.h>
#include <linux/platform_data/leds-s3c24xx.h>
#include <linux/platform_data/i2c-s3c2410.h>

1
arch/arm/mach-s3c24xx/mach-smdk2440.c
View File

@ -35,7 +35,6 @@
#include <mach/regs-gpio.h>
#include <mach/regs-lcd.h>
#include <mach/idle.h>
#include <mach/fb.h>
#include <linux/platform_data/i2c-s3c2410.h>

1
arch/arm/mach-s3c24xx/mach-smdk2443.c
View File

@ -35,7 +35,6 @@
#include <mach/regs-gpio.h>
#include <mach/regs-lcd.h>
#include <mach/idle.h>
#include <mach/fb.h>
#include <linux/platform_data/i2c-s3c2410.h>

39
arch/arm/mach-s3c24xx/mach-vr1000.c
View File

@ -1,5 +1,4 @@
/* linux/arch/arm/mach-s3c2410/mach-vr1000.c
*
/*
* Copyright (c) 2003-2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
@ -32,27 +31,25 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/bast-map.h>
#include <mach/vr1000-map.h>
#include <mach/vr1000-irq.h>
#include <mach/vr1000-cpld.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <linux/platform_data/leds-s3c24xx.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <linux/platform_data/i2c-s3c2410.h>
#include <linux/platform_data/asoc-s3c24xx_simtec.h>
#include "simtec.h"
#include <mach/hardware.h>
#include <mach/regs-gpio.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/regs-serial.h>
#include "bast.h"
#include "common.h"
#include "simtec.h"
#include "vr1000.h"
/* macros for virtual address mods for the io space entries */
#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
@ -143,7 +140,7 @@ static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
static struct plat_serial8250_port serial_platform_data[] = {
[0] = {
.mapbase = VR1000_SERIAL_MAPBASE(0),
.irq = IRQ_VR1000_SERIAL + 0,
.irq = VR1000_IRQ_SERIAL + 0,
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
.iotype = UPIO_MEM,
.regshift = 0,
@ -151,7 +148,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
},
[1] = {
.mapbase = VR1000_SERIAL_MAPBASE(1),
.irq = IRQ_VR1000_SERIAL + 1,
.irq = VR1000_IRQ_SERIAL + 1,
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
.iotype = UPIO_MEM,
.regshift = 0,
@ -159,7 +156,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
},
[2] = {
.mapbase = VR1000_SERIAL_MAPBASE(2),
.irq = IRQ_VR1000_SERIAL + 2,
.irq = VR1000_IRQ_SERIAL + 2,
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
.iotype = UPIO_MEM,
.regshift = 0,
@ -167,7 +164,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
},
[3] = {
.mapbase = VR1000_SERIAL_MAPBASE(3),
.irq = IRQ_VR1000_SERIAL + 3,
.irq = VR1000_IRQ_SERIAL + 3,
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
.iotype = UPIO_MEM,
.regshift = 0,
@ -189,14 +186,14 @@ static struct platform_device serial_device = {
static struct resource vr1000_dm9k0_resource[] = {
[0] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000, 4),
[1] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0x40, 0x40),
[2] = DEFINE_RES_NAMED(IRQ_VR1000_DM9000A, 1, NULL, IORESOURCE_IRQ \
[2] = DEFINE_RES_NAMED(VR1000_IRQ_DM9000A, 1, NULL, IORESOURCE_IRQ \
| IORESOURCE_IRQ_HIGHLEVEL),
};
static struct resource vr1000_dm9k1_resource[] = {
[0] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0x80, 4),
[1] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0xC0, 0x40),
[2] = DEFINE_RES_NAMED(IRQ_VR1000_DM9000N, 1, NULL, IORESOURCE_IRQ \
[2] = DEFINE_RES_NAMED(VR1000_IRQ_DM9000N, 1, NULL, IORESOURCE_IRQ \
| IORESOURCE_IRQ_HIGHLEVEL),
};

1
arch/arm/mach-s3c24xx/mach-vstms.c
View File

@ -36,7 +36,6 @@
#include <mach/regs-gpio.h>
#include <mach/regs-lcd.h>
#include <mach/idle.h>
#include <mach/fb.h>
#include <linux/platform_data/i2c-s3c2410.h>

23
arch/arm/mach-s3c24xx/include/mach/osiris-map.h → arch/arm/mach-s3c24xx/osiris.h
View File

@ -1,9 +1,9 @@
/* arch/arm/mach-s3c2410/include/mach/osiris-map.h
*
/*
* Copyright 2005 Simtec Electronics
* http://www.simtec.co.uk/products/
* Ben Dooks <ben@simtec.co.uk>
*
* OSIRIS - CPLD control constants
* OSIRIS - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
@ -11,10 +11,21 @@
* published by the Free Software Foundation.
*/
/* needs arch/map.h including with this */
#ifndef __MACH_S3C24XX_OSIRIS_H
#define __MACH_S3C24XX_OSIRIS_H __FILE__
#ifndef __ASM_ARCH_OSIRISMAP_H
#define __ASM_ARCH_OSIRISMAP_H
/* CTRL0 - NAND WP control */
#define OSIRIS_CTRL0_NANDSEL (0x3)
#define OSIRIS_CTRL0_BOOT_INT (1<<3)
#define OSIRIS_CTRL0_PCMCIA (1<<4)
#define OSIRIS_CTRL0_FIX8 (1<<5)
#define OSIRIS_CTRL0_PCMCIA_nWAIT (1<<6)
#define OSIRIS_CTRL0_PCMCIA_nIOIS16 (1<<7)
#define OSIRIS_CTRL1_FIX8 (1<<0)
#define OSIRIS_ID_REVMASK (0x7)
/* start peripherals off after the S3C2410 */
@ -39,4 +50,4 @@
#define OSIRIS_VA_IDREG OSIRIS_IOADDR(0x00700000)
#define OSIRIS_PA_IDREG (OSIRIS_PA_CPLD + (7<<23))
#endif /* __ASM_ARCH_OSIRISMAP_H */
#endif /* __MACH_S3C24XX_OSIRIS_H */

20
arch/arm/mach-s3c24xx/include/mach/otom-map.h → arch/arm/mach-s3c24xx/otom.h
View File

@ -1,5 +1,4 @@
/* arch/arm/mach-s3c2410/include/mach/otom-map.h
*
/*
* (c) 2005 Guillaume GOURAT / NexVision
* guillaume.gourat@nexvision.fr
*
@ -10,21 +9,20 @@
* published by the Free Software Foundation.
*/
/* needs arch/map.h including with this */
/* ok, we've used up to 0x01300000, now we need to find space for the
/*
* ok, we've used up to 0x01300000, now we need to find space for the
* peripherals that live in the nGCS[x] areas, which are quite numerous
* in their space.
*/
#ifndef __ASM_ARCH_OTOMMAP_H
#define __ASM_ARCH_OTOMMAP_H
#ifndef __MACH_S3C24XX_OTOM_H
#define __MACH_S3C24XX_OTOM_H __FILE__
#define OTOM_PA_CS8900A_BASE (S3C2410_CS3 + 0x01000000) /* nGCS3 +0x01000000 */
#define OTOM_VA_CS8900A_BASE S3C2410_ADDR(0x04000000) /* 0xF4000000 */
#define OTOM_PA_CS8900A_BASE (S3C2410_CS3 + 0x01000000) /* nGCS3 +0x01000000 */
#define OTOM_VA_CS8900A_BASE S3C2410_ADDR(0x04000000) /* 0xF4000000 */
/* physical offset addresses for the peripherals */
#define OTOM_PA_FLASH0_BASE (S3C2410_CS0) /* Bank 0 */
#define OTOM_PA_FLASH0_BASE (S3C2410_CS0)
#endif /* __ASM_ARCH_OTOMMAP_H */
#endif /* __MACH_S3C24XX_OTOM_H */

6
arch/arm/mach-s3c24xx/pm-s3c2410.c
View File

@ -29,16 +29,16 @@
#include <linux/gpio.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <mach/hardware.h>
#include <mach/regs-gpio.h>
#include <mach/h1940.h>
#include <plat/cpu.h>
#include <plat/pm.h>
#include "h1940.h"
static void s3c2410_pm_prepare(void)
{
/* ensure at least GSTATUS3 has the resume address */

8
arch/arm/mach-s3c24xx/pm-s3c2412.c
View File

@ -21,19 +21,19 @@
#include <linux/platform_device.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/cacheflush.h>
#include <asm/irq.h>
#include <mach/regs-power.h>
#include <mach/hardware.h>
#include <mach/regs-gpio.h>
#include <mach/regs-dsc.h>
#include <mach/regs-power.h>
#include <plat/cpu.h>
#include <plat/pm.h>
#include <plat/s3c2412.h>
#include "regs-dsc.h"
extern void s3c2412_sleep_enter(void);
static int s3c2412_cpu_suspend(unsigned long arg)

0
arch/arm/mach-s3c24xx/include/mach/regs-dsc.h → arch/arm/mach-s3c24xx/regs-dsc.h
View File

31
arch/arm/mach-s3c24xx/s3c2412.c
View File

@ -1,5 +1,4 @@
/* linux/arch/arm/mach-s3c2412/s3c2412.c
*
/*
* Copyright (c) 2006 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
@ -28,28 +27,30 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include <asm/proc-fns.h>
#include <asm/irq.h>
#include <asm/system_misc.h>
#include <plat/cpu-freq.h>
#include <mach/hardware.h>
#include <mach/regs-clock.h>
#include <plat/regs-serial.h>
#include <mach/regs-power.h>
#include <mach/regs-gpio.h>
#include <mach/regs-dsc.h>
#include <plat/regs-spi.h>
#include <mach/regs-s3c2412.h>
#include <mach/regs-power.h>
#include <plat/s3c2412.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/pm.h>
#include <plat/pll.h>
#include <plat/cpu.h>
#include <plat/cpu-freq.h>
#include <plat/devs.h>
#include <plat/nand-core.h>
#include <plat/pll.h>
#include <plat/pm.h>
#include <plat/regs-serial.h>
#include <plat/regs-spi.h>
#include <plat/s3c2412.h>
#include "regs-dsc.h"
#define S3C2412_SWRST (S3C24XX_VA_CLKPWR + 0x30)
#define S3C2412_SWRST_RESET (0x533C2412)
#ifndef CONFIG_CPU_S3C2412_ONLY
void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;

3
arch/arm/mach-s3c24xx/s3c244x.c
View File

@ -36,7 +36,6 @@
#include <mach/regs-clock.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <mach/regs-dsc.h>
#include <plat/s3c2410.h>
#include <plat/s3c244x.h>
@ -48,6 +47,8 @@
#include <plat/nand-core.h>
#include <plat/watchdog-reset.h>
#include "regs-dsc.h"
static struct map_desc s3c244x_iodesc[] __initdata = {
IODESC_ENT(CLKPWR),
IODESC_ENT(TIMER),

5
arch/arm/mach-s3c24xx/simtec-audio.c
View File

@ -17,16 +17,13 @@
#include <linux/device.h>
#include <linux/io.h>
#include <mach/bast-map.h>
#include <mach/bast-irq.h>
#include <mach/bast-cpld.h>
#include <mach/hardware.h>
#include <mach/regs-gpio.h>
#include <linux/platform_data/asoc-s3c24xx_simtec.h>
#include <plat/devs.h>
#include "bast.h"
#include "simtec.h"
/* platform ops for audio */

3
arch/arm/mach-s3c24xx/simtec-nor.c
View File

@ -27,9 +27,8 @@
#include <asm/mach/irq.h>
#include <mach/map.h>
#include <mach/bast-map.h>
#include <mach/bast-cpld.h>
#include "bast.h"
#include "simtec.h"
static void simtec_nor_vpp(struct platform_device *pdev, int vpp)

8
arch/arm/mach-s3c24xx/simtec-usb.c
View File

@ -28,15 +28,13 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/bast-map.h>
#include <mach/bast-irq.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <linux/platform_data/usb-ohci-s3c2410.h>
#include <plat/devs.h>
#include "bast.h"
#include "simtec.h"
/* control power and monitor over-current events on various Simtec
@ -79,7 +77,7 @@ static void usb_simtec_enableoc(struct s3c2410_hcd_info *info, int on)
int ret;
if (on) {
ret = request_irq(IRQ_USBOC, usb_simtec_ocirq,
ret = request_irq(BAST_IRQ_USBOC, usb_simtec_ocirq,
IRQF_DISABLED | IRQF_TRIGGER_RISING |
IRQF_TRIGGER_FALLING,
"USB Over-current", info);
@ -87,7 +85,7 @@ static void usb_simtec_enableoc(struct s3c2410_hcd_info *info, int on)
printk(KERN_ERR "failed to request usb oc irq\n");
}
} else {
free_irq(IRQ_USBOC, info);
free_irq(BAST_IRQ_USBOC, info);
}
}

118
arch/arm/mach-s3c24xx/vr1000.h Normal file
View File

@ -0,0 +1,118 @@
/* arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h
*
* Copyright (c) 2003 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* VR1000 - CPLD control constants
* Machine VR1000 - IRQ Number definitions
* Machine VR1000 - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __MACH_S3C24XX_VR1000_H
#define __MACH_S3C24XX_VR1000_H __FILE__
#define VR1000_CPLD_CTRL2_RAMWEN (0x04) /* SRAM Write Enable */
/* irq numbers to onboard peripherals */
#define VR1000_IRQ_USBOC IRQ_EINT19
#define VR1000_IRQ_IDE0 IRQ_EINT16
#define VR1000_IRQ_IDE1 IRQ_EINT17
#define VR1000_IRQ_SERIAL IRQ_EINT12
#define VR1000_IRQ_DM9000A IRQ_EINT10
#define VR1000_IRQ_DM9000N IRQ_EINT9
#define VR1000_IRQ_SMALERT IRQ_EINT8
/* map */
#define VR1000_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000))
/* we put the CPLD registers next, to get them out of the way */
#define VR1000_VA_CTRL1 VR1000_IOADDR(0x00000000) /* 0x01300000 */
#define VR1000_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
#define VR1000_VA_CTRL2 VR1000_IOADDR(0x00100000) /* 0x01400000 */
#define VR1000_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
#define VR1000_VA_CTRL3 VR1000_IOADDR(0x00200000) /* 0x01500000 */
#define VR1000_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
#define VR1000_VA_CTRL4 VR1000_IOADDR(0x00300000) /* 0x01600000 */
#define VR1000_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
/* next, we have the PC104 ISA interrupt registers */
#define VR1000_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
#define VR1000_VA_PC104_IRQREQ VR1000_IOADDR(0x00400000)
#define VR1000_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
#define VR1000_VA_PC104_IRQRAW VR1000_IOADDR(0x00500000)
#define VR1000_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
#define VR1000_VA_PC104_IRQMASK VR1000_IOADDR(0x00600000)
/*
* 0xE0000000 contains the IO space that is split by speed and
* whether the access is for 8 or 16bit IO... this ensures that
* the correct access is made
*
* 0x10000000 of space, partitioned as so:
*
* 0x00000000 to 0x04000000 8bit, slow
* 0x04000000 to 0x08000000 16bit, slow
* 0x08000000 to 0x0C000000 16bit, net
* 0x0C000000 to 0x10000000 16bit, fast
*
* each of these spaces has the following in:
*
* 0x02000000 to 0x02100000 1MB IDE primary channel
* 0x02100000 to 0x02200000 1MB IDE primary channel aux
* 0x02200000 to 0x02400000 1MB IDE secondary channel
* 0x02300000 to 0x02400000 1MB IDE secondary channel aux
* 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controllers
* 0x02600000 to 0x02700000 1MB
*
* the phyiscal layout of the zones are:
* nGCS2 - 8bit, slow
* nGCS3 - 16bit, slow
* nGCS4 - 16bit, net
* nGCS5 - 16bit, fast
*/
#define VR1000_VA_MULTISPACE (0xE0000000)
#define VR1000_VA_ISAIO (VR1000_VA_MULTISPACE + 0x00000000)
#define VR1000_VA_ISAMEM (VR1000_VA_MULTISPACE + 0x01000000)
#define VR1000_VA_IDEPRI (VR1000_VA_MULTISPACE + 0x02000000)
#define VR1000_VA_IDEPRIAUX (VR1000_VA_MULTISPACE + 0x02100000)
#define VR1000_VA_IDESEC (VR1000_VA_MULTISPACE + 0x02200000)
#define VR1000_VA_IDESECAUX (VR1000_VA_MULTISPACE + 0x02300000)
#define VR1000_VA_ASIXNET (VR1000_VA_MULTISPACE + 0x02400000)
#define VR1000_VA_DM9000 (VR1000_VA_MULTISPACE + 0x02500000)
#define VR1000_VA_SUPERIO (VR1000_VA_MULTISPACE + 0x02600000)
/* physical offset addresses for the peripherals */
#define VR1000_PA_IDEPRI (0x02000000)
#define VR1000_PA_IDEPRIAUX (0x02800000)
#define VR1000_PA_IDESEC (0x03000000)
#define VR1000_PA_IDESECAUX (0x03800000)
#define VR1000_PA_DM9000 (0x05000000)
#define VR1000_PA_SERIAL (0x11800000)
#define VR1000_VA_SERIAL (VR1000_IOADDR(0x00700000))
/* VR1000 ram is in CS1, with A26..A24 = 2_101 */
#define VR1000_PA_SRAM (S3C2410_CS1 | 0x05000000)
/* some configurations for the peripherals */
#define VR1000_DM9000_CS VR1000_VAM_CS4
#endif /* __MACH_S3C24XX_VR1000_H */

3
arch/arm/mach-s3c64xx/clock.c
View File

@ -23,7 +23,6 @@
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-sys.h>
#include <mach/regs-clock.h>
#include <plat/cpu.h>
@ -33,6 +32,8 @@
#include <plat/clock-clksrc.h>
#include <plat/pll.h>
#include "regs-sys.h"
/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
* ext_xtal_mux for want of an actual name from the manual.
*/

4
arch/arm/mach-s3c64xx/cpuidle.c
View File

@ -20,8 +20,8 @@
#include <mach/map.h>
#include <mach/regs-sys.h>
#include <mach/regs-syscon-power.h>
#include "regs-sys.h"
#include "regs-syscon-power.h"
static int s3c64xx_enter_idle(struct cpuidle_device *dev,
struct cpuidle_driver *drv,

0
arch/arm/mach-s3c64xx/include/mach/crag6410.h → arch/arm/mach-s3c64xx/crag6410.h
View File

4
arch/arm/mach-s3c64xx/dma.c
View File

@ -28,10 +28,10 @@
#include <mach/map.h>
#include <mach/irqs.h>
#include <mach/regs-sys.h>
#include <asm/hardware/pl080.h>
#include "regs-sys.h"
/* dma channel state information */
struct s3c64xx_dmac {

31
arch/arm/mach-s3c64xx/include/mach/regs-sys.h
View File

@ -1,31 +0,0 @@
/* arch/arm/plat-s3c64xx/include/plat/regs-sys.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C64XX system register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PLAT_REGS_SYS_H
#define __PLAT_REGS_SYS_H __FILE__
#define S3C_SYSREG(x) (S3C_VA_SYS + (x))
#define S3C64XX_AHB_CON0 S3C_SYSREG(0x100)
#define S3C64XX_AHB_CON1 S3C_SYSREG(0x104)
#define S3C64XX_AHB_CON2 S3C_SYSREG(0x108)
#define S3C64XX_SDMA_SEL S3C_SYSREG(0x110)
#define S3C64XX_OTHERS S3C_SYSREG(0x900)
#define S3C64XX_OTHERS_USBMASK (1 << 16)
#define S3C64XX_OTHERS_SYNCMUXSEL (1 << 6)
#endif /* _PLAT_REGS_SYS_H */

2
arch/arm/mach-s3c64xx/mach-anw6410.c
View File

@ -49,9 +49,9 @@
#include <plat/devs.h>
#include <plat/cpu.h>
#include <mach/regs-gpio.h>
#include <mach/regs-modem.h>
#include "common.h"
#include "regs-modem.h"
/* DM9000 */
#define ANW6410_PA_DM9000 (0x18000000)

2
arch/arm/mach-s3c64xx/mach-crag6410-module.c
View File

@ -29,7 +29,7 @@
#include <linux/platform_data/spi-s3c64xx.h>
#include <mach/crag6410.h>
#include "crag6410.h"
static struct s3c64xx_spi_csinfo wm0010_spi_csinfo = {
.line = S3C64XX_GPC(3),

9
arch/arm/mach-s3c64xx/mach-crag6410.c
View File

@ -49,12 +49,7 @@
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-sys.h>
#include <mach/regs-gpio.h>
#include <mach/regs-modem.h>
#include <mach/crag6410.h>
#include <mach/regs-gpio-memport.h>
#include <plat/regs-serial.h>
#include <plat/fb.h>
@ -71,6 +66,10 @@
#include <plat/pm.h>
#include "common.h"
#include "crag6410.h"
#include "regs-gpio-memport.h"
#include "regs-modem.h"
#include "regs-sys.h"
/* serial port setup */

4
arch/arm/mach-s3c64xx/mach-mini6410.c
View File

@ -30,8 +30,6 @@
#include <mach/map.h>
#include <mach/regs-gpio.h>
#include <mach/regs-modem.h>
#include <mach/regs-srom.h>
#include <plat/adc.h>
#include <plat/cpu.h>
@ -45,6 +43,8 @@
#include <video/samsung_fimd.h>
#include "common.h"
#include "regs-modem.h"
#include "regs-srom.h"
#define UCON S3C2410_UCON_DEFAULT
#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)

4
arch/arm/mach-s3c64xx/mach-real6410.c
View File

@ -31,8 +31,6 @@
#include <mach/map.h>
#include <mach/regs-gpio.h>
#include <mach/regs-modem.h>
#include <mach/regs-srom.h>
#include <plat/adc.h>
#include <plat/cpu.h>
@ -46,6 +44,8 @@
#include <video/samsung_fimd.h>
#include "common.h"
#include "regs-modem.h"
#include "regs-srom.h"
#define UCON S3C2410_UCON_DEFAULT
#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)

2
arch/arm/mach-s3c64xx/mach-smartq.c
View File

@ -25,7 +25,6 @@
#include <mach/map.h>
#include <mach/regs-gpio.h>
#include <mach/regs-modem.h>
#include <plat/clock.h>
#include <plat/cpu.h>
@ -41,6 +40,7 @@
#include <video/platform_lcd.h>
#include "common.h"
#include "regs-modem.h"
#define UCON S3C2410_UCON_DEFAULT
#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)

6
arch/arm/mach-s3c64xx/mach-smdk6410.c
View File

@ -56,10 +56,7 @@
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
#include <mach/regs-modem.h>
#include <mach/regs-gpio.h>
#include <mach/regs-sys.h>
#include <mach/regs-srom.h>
#include <linux/platform_data/ata-samsung_cf.h>
#include <linux/platform_data/i2c-s3c2410.h>
#include <plat/fb.h>
@ -74,6 +71,9 @@
#include <plat/backlight.h>
#include "common.h"
#include "regs-modem.h"
#include "regs-srom.h"
#include "regs-sys.h"
#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB

9
arch/arm/mach-s3c64xx/pm.c
View File

@ -26,12 +26,13 @@
#include <plat/pm.h>
#include <plat/wakeup-mask.h>
#include <mach/regs-sys.h>
#include <mach/regs-gpio.h>
#include <mach/regs-clock.h>
#include <mach/regs-syscon-power.h>
#include <mach/regs-gpio-memport.h>
#include <mach/regs-modem.h>
#include "regs-gpio-memport.h"
#include "regs-modem.h"
#include "regs-sys.h"
#include "regs-syscon-power.h"
struct s3c64xx_pm_domain {
char *const name;

9
arch/arm/mach-s3c64xx/include/mach/regs-gpio-memport.h → arch/arm/mach-s3c64xx/regs-gpio-memport.h
View File

@ -1,5 +1,4 @@
/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio-memport.h
*
/*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
@ -8,8 +7,8 @@
* S3C64XX - GPIO memory port register definitions
*/
#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H
#define __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H __FILE__
#ifndef __MACH_S3C64XX_REGS_GPIO_MEMPORT_H
#define __MACH_S3C64XX_REGS_GPIO_MEMPORT_H __FILE__
#define S3C64XX_MEM0CONSTOP S3C64XX_GPIOREG(0x1B0)
#define S3C64XX_MEM1CONSTOP S3C64XX_GPIOREG(0x1B4)
@ -21,5 +20,5 @@
#define S3C64XX_MEM0DRVCON S3C64XX_GPIOREG(0x1D0)
#define S3C64XX_MEM1DRVCON S3C64XX_GPIOREG(0x1D4)
#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H */
#endif /* __MACH_S3C64XX_REGS_GPIO_MEMPORT_H */

11
arch/arm/mach-s3c64xx/include/mach/regs-modem.h → arch/arm/mach-s3c64xx/regs-modem.h
View File

@ -1,5 +1,4 @@
/* arch/arm/plat-s3c64xx/include/plat/regs-modem.h
*
/*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
@ -12,10 +11,10 @@
* published by the Free Software Foundation.
*/
#ifndef __PLAT_S3C64XX_REGS_MODEM_H
#define __PLAT_S3C64XX_REGS_MODEM_H __FILE__
#ifndef __MACH_S3C64XX_REGS_MODEM_H
#define __MACH_S3C64XX_REGS_MODEM_H __FILE__
#define S3C64XX_MODEMREG(x) (S3C64XX_VA_MODEM + (x))
#define S3C64XX_MODEMREG(x) (S3C64XX_VA_MODEM + (x))
#define S3C64XX_MODEM_INT2AP S3C64XX_MODEMREG(0x0)
#define S3C64XX_MODEM_INT2MODEM S3C64XX_MODEMREG(0x4)
@ -28,4 +27,4 @@
#define MIFPCON_INT2M_LEVEL (1 << 4)
#define MIFPCON_LCD_BYPASS (1 << 3)
#endif /* __PLAT_S3C64XX_REGS_MODEM_H */
#endif /* __MACH_S3C64XX_REGS_MODEM_H */

11
arch/arm/mach-s3c64xx/include/mach/regs-srom.h → arch/arm/mach-s3c64xx/regs-srom.h
View File

@ -1,5 +1,4 @@
/* arch/arm/plat-s3c64xx/include/plat/regs-srom.h
*
/*
* Copyright 2009 Andy Green <andy@warmcat.com>
*
* S3C64XX SROM definitions
@ -9,8 +8,8 @@
* published by the Free Software Foundation.
*/
#ifndef __PLAT_REGS_SROM_H
#define __PLAT_REGS_SROM_H __FILE__
#ifndef __MACH_S3C64XX_REGS_SROM_H
#define __MACH_S3C64XX_REGS_SROM_H __FILE__
#define S3C64XX_SROMREG(x) (S3C_VA_MEM + (x))
@ -29,7 +28,7 @@
#define S3C64XX_SROM_BW__DATAWIDTH__SHIFT 0
#define S3C64XX_SROM_BW__WAITENABLE__SHIFT 2
#define S3C64XX_SROM_BW__BYTEENABLE__SHIFT 3
#define S3C64XX_SROM_BW__CS_MASK 0xf
#define S3C64XX_SROM_BW__CS_MASK 0xf
#define S3C64XX_SROM_BW__NCS0__SHIFT 0
#define S3C64XX_SROM_BW__NCS1__SHIFT 4
@ -56,4 +55,4 @@
#define S3C64XX_SROM_BCX__TACS__SHIFT 28
#define S3C64XX_SROM_BCX__TACS__MASK 0xf
#endif /* _PLAT_REGS_SROM_H */
#endif /* __MACH_S3C64XX_REGS_SROM_H */

30
arch/arm/mach-s3c64xx/regs-sys.h Normal file
View File

@ -0,0 +1,30 @@
/*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C64XX system register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __MACH_S3C64XX_REGS_SYS_H
#define __MACH_S3C64XX_REGS_SYS_H __FILE__
#define S3C_SYSREG(x) (S3C_VA_SYS + (x))
#define S3C64XX_AHB_CON0 S3C_SYSREG(0x100)
#define S3C64XX_AHB_CON1 S3C_SYSREG(0x104)
#define S3C64XX_AHB_CON2 S3C_SYSREG(0x108)
#define S3C64XX_SDMA_SEL S3C_SYSREG(0x110)
#define S3C64XX_OTHERS S3C_SYSREG(0x900)
#define S3C64XX_OTHERS_USBMASK (1 << 16)
#define S3C64XX_OTHERS_SYNCMUXSEL (1 << 6)
#endif /* __MACH_S3C64XX_REGS_SYS_H */

9
arch/arm/mach-s3c64xx/include/mach/regs-syscon-power.h → arch/arm/mach-s3c64xx/regs-syscon-power.h
View File

@ -1,5 +1,4 @@
/* arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h
*
/*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
@ -12,8 +11,8 @@
* published by the Free Software Foundation.
*/
#ifndef __PLAT_S3C64XX_REGS_SYSCON_POWER_H
#define __PLAT_S3C64XX_REGS_SYSCON_POWER_H __FILE__
#ifndef __MACH_S3C64XX_REGS_SYSCON_POWER_H
#define __MACH_S3C64XX_REGS_SYSCON_POWER_H __FILE__
#define S3C64XX_PWR_CFG S3C_SYSREG(0x804)
@ -113,4 +112,4 @@
#define S3C64XX_INFORM2 S3C_SYSREG(0xA08)
#define S3C64XX_INFORM3 S3C_SYSREG(0xA0C)
#endif /* __PLAT_S3C64XX_REGS_SYSCON_POWER_H */
#endif /* __MACH_S3C64XX_REGS_SYSCON_POWER_H */

3
arch/arm/mach-s3c64xx/setup-usb-phy.c
View File

@ -15,11 +15,12 @@
#include <linux/io.h>
#include <linux/platform_device.h>
#include <mach/map.h>
#include <mach/regs-sys.h>
#include <plat/cpu.h>
#include <plat/regs-usb-hsotg-phy.h>
#include <plat/usb-phy.h>
#include "regs-sys.h"
static int s3c_usb_otgphy_init(struct platform_device *pdev)
{
struct clk *xusbxti;

2
arch/arm/mach-s5p64x0/clock-s5p6440.c
View File

@ -23,7 +23,6 @@
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/s5p64x0-clock.h>
#include <plat/cpu-freq.h>
#include <plat/clock.h>
@ -32,6 +31,7 @@
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
#include "clock.h"
#include "common.h"
static u32 epll_div[][5] = {

2
arch/arm/mach-s5p64x0/clock-s5p6450.c
View File

@ -23,7 +23,6 @@
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/s5p64x0-clock.h>
#include <plat/cpu-freq.h>
#include <plat/clock.h>
@ -32,6 +31,7 @@
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
#include "clock.h"
#include "common.h"
static struct clksrc_clk clk_mout_dpll = {

9
arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h → arch/arm/mach-s5p64x0/clock.h
View File

@ -1,5 +1,4 @@
/* linux/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
*
/*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
@ -10,8 +9,8 @@
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H __FILE__
#ifndef __MACH_S5P64X0_CLOCK_H
#define __MACH_S5P64X0_CLOCK_H __FILE__
#include <linux/clk.h>
@ -36,4 +35,4 @@ extern int s5p64x0_mem_ctrl(struct clk *clk, int enable);
extern int s5p64x0_clk48m_ctrl(struct clk *clk, int enable);
#endif /* __ASM_ARCH_CLOCK_H */
#endif /* __MACH_S5P64X0_CLOCK_H */

508
arch/arm/mach-s5p64x0/gpiolib.c
View File

@ -1,508 +0,0 @@
/* linux/arch/arm/mach-s5p64x0/gpiolib.c
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P64X0 - GPIOlib support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <mach/map.h>
#include <mach/regs-gpio.h>
#include <mach/regs-clock.h>
#include <plat/cpu.h>
#include <plat/gpio-core.h>
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-helpers.h>
/*
* S5P6440 GPIO bank summary:
*
* Bank GPIOs Style SlpCon ExtInt Group
* A 6 4Bit Yes 1
* B 7 4Bit Yes 1
* C 8 4Bit Yes 2
* F 2 2Bit Yes 4 [1]
* G 7 4Bit Yes 5
* H 10 4Bit[2] Yes 6
* I 16 2Bit Yes None
* J 12 2Bit Yes None
* N 16 2Bit No IRQ_EINT
* P 8 2Bit Yes 8
* R 15 4Bit[2] Yes 8
*
* S5P6450 GPIO bank summary:
*
* Bank GPIOs Style SlpCon ExtInt Group
* A 6 4Bit Yes 1
* B 7 4Bit Yes 1
* C 8 4Bit Yes 2
* D 8 4Bit Yes None
* F 2 2Bit Yes None
* G 14 4Bit[2] Yes 5
* H 10 4Bit[2] Yes 6
* I 16 2Bit Yes None
* J 12 2Bit Yes None
* K 5 4Bit Yes None
* N 16 2Bit No IRQ_EINT
* P 11 2Bit Yes 8
* Q 14 2Bit Yes None
* R 15 4Bit[2] Yes None
* S 8 2Bit Yes None
*
* [1] BANKF pins 14,15 do not form part of the external interrupt sources
* [2] BANK has two control registers, GPxCON0 and GPxCON1
*/
static int s5p64x0_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
unsigned int offset)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
void __iomem *regcon = base;
unsigned long con;
unsigned long flags;
switch (offset) {
case 6:
offset += 1;
case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
regcon -= 4;
break;
default:
offset -= 7;
break;
}
s3c_gpio_lock(ourchip, flags);
con = __raw_readl(regcon);
con &= ~(0xf << con_4bit_shift(offset));
__raw_writel(con, regcon);
s3c_gpio_unlock(ourchip, flags);
return 0;
}
static int s5p64x0_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
void __iomem *regcon = base;
unsigned long con;
unsigned long dat;
unsigned long flags;
unsigned con_offset = offset;
switch (con_offset) {
case 6:
con_offset += 1;
case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
regcon -= 4;
break;
default:
con_offset -= 7;
break;
}
s3c_gpio_lock(ourchip, flags);
con = __raw_readl(regcon);
con &= ~(0xf << con_4bit_shift(con_offset));
con |= 0x1 << con_4bit_shift(con_offset);
dat = __raw_readl(base + GPIODAT_OFF);
if (value)
dat |= 1 << offset;
else
dat &= ~(1 << offset);
__raw_writel(con, regcon);
__raw_writel(dat, base + GPIODAT_OFF);
s3c_gpio_unlock(ourchip, flags);
return 0;
}
int s5p64x0_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int cfg)
{
void __iomem *reg = chip->base;
unsigned int shift;
u32 con;
switch (off) {
case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
shift = (off & 7) * 4;
reg -= 4;
break;
case 6:
shift = ((off + 1) & 7) * 4;
reg -= 4;
default:
shift = ((off + 1) & 7) * 4;
break;
}
if (s3c_gpio_is_cfg_special(cfg)) {
cfg &= 0xf;
cfg <<= shift;
}
con = __raw_readl(reg);
con &= ~(0xf << shift);
con |= cfg;
__raw_writel(con, reg);
return 0;
}
static struct s3c_gpio_cfg s5p64x0_gpio_cfgs[] = {
{
.cfg_eint = 0,
}, {
.cfg_eint = 7,
}, {
.cfg_eint = 3,
.set_config = s5p64x0_gpio_setcfg_4bit_rbank,
}, {
.cfg_eint = 0,
.set_config = s3c_gpio_setcfg_s3c24xx,
.get_config = s3c_gpio_getcfg_s3c24xx,
}, {
.cfg_eint = 2,
.set_config = s3c_gpio_setcfg_s3c24xx,
.get_config = s3c_gpio_getcfg_s3c24xx,
}, {
.cfg_eint = 3,
.set_config = s3c_gpio_setcfg_s3c24xx,
.get_config = s3c_gpio_getcfg_s3c24xx,
},
};
static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
{
.base = S5P64X0_GPA_BASE,
.config = &s5p64x0_gpio_cfgs[1],
.chip = {
.base = S5P6440_GPA(0),
.ngpio = S5P6440_GPIO_A_NR,
.label = "GPA",
},
}, {
.base = S5P64X0_GPB_BASE,
.config = &s5p64x0_gpio_cfgs[1],
.chip = {
.base = S5P6440_GPB(0),
.ngpio = S5P6440_GPIO_B_NR,
.label = "GPB",
},
}, {
.base = S5P64X0_GPC_BASE,
.config = &s5p64x0_gpio_cfgs[1],
.chip = {
.base = S5P6440_GPC(0),
.ngpio = S5P6440_GPIO_C_NR,
.label = "GPC",
},
}, {
.base = S5P64X0_GPG_BASE,
.config = &s5p64x0_gpio_cfgs[1],
.chip = {
.base = S5P6440_GPG(0),
.ngpio = S5P6440_GPIO_G_NR,
.label = "GPG",
},
},
};
static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
{
.base = S5P64X0_GPH_BASE + 0x4,
.config = &s5p64x0_gpio_cfgs[1],
.chip = {
.base = S5P6440_GPH(0),
.ngpio = S5P6440_GPIO_H_NR,
.label = "GPH",
},
},
};
static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = {
{
.base = S5P64X0_GPR_BASE + 0x4,
.config = &s5p64x0_gpio_cfgs[2],
.chip = {
.base = S5P6440_GPR(0),
.ngpio = S5P6440_GPIO_R_NR,
.label = "GPR",
},
},
};
static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
{
.base = S5P64X0_GPF_BASE,
.config = &s5p64x0_gpio_cfgs[5],
.chip = {
.base = S5P6440_GPF(0),
.ngpio = S5P6440_GPIO_F_NR,
.label = "GPF",
},
}, {
.base = S5P64X0_GPI_BASE,
.config = &s5p64x0_gpio_cfgs[3],
.chip = {
.base = S5P6440_GPI(0),
.ngpio = S5P6440_GPIO_I_NR,
.label = "GPI",
},
}, {
.base = S5P64X0_GPJ_BASE,
.config = &s5p64x0_gpio_cfgs[3],
.chip = {
.base = S5P6440_GPJ(0),
.ngpio = S5P6440_GPIO_J_NR,
.label = "GPJ",
},
}, {
.base = S5P64X0_GPN_BASE,
.config = &s5p64x0_gpio_cfgs[4],
.chip = {
.base = S5P6440_GPN(0),
.ngpio = S5P6440_GPIO_N_NR,
.label = "GPN",
},
}, {
.base = S5P64X0_GPP_BASE,
.config = &s5p64x0_gpio_cfgs[5],
.chip = {
.base = S5P6440_GPP(0),
.ngpio = S5P6440_GPIO_P_NR,
.label = "GPP",
},
},
};
static struct s3c_gpio_chip s5p6450_gpio_4bit[] = {
{
.base = S5P64X0_GPA_BASE,
.config = &s5p64x0_gpio_cfgs[1],
.chip = {
.base = S5P6450_GPA(0),
.ngpio = S5P6450_GPIO_A_NR,
.label = "GPA",
},
}, {
.base = S5P64X0_GPB_BASE,
.config = &s5p64x0_gpio_cfgs[1],
.chip = {
.base = S5P6450_GPB(0),
.ngpio = S5P6450_GPIO_B_NR,
.label = "GPB",
},
}, {
.base = S5P64X0_GPC_BASE,
.config = &s5p64x0_gpio_cfgs[1],
.chip = {
.base = S5P6450_GPC(0),
.ngpio = S5P6450_GPIO_C_NR,
.label = "GPC",
},
}, {
.base = S5P6450_GPD_BASE,
.config = &s5p64x0_gpio_cfgs[1],
.chip = {
.base = S5P6450_GPD(0),
.ngpio = S5P6450_GPIO_D_NR,
.label = "GPD",
},
}, {
.base = S5P6450_GPK_BASE,
.config = &s5p64x0_gpio_cfgs[1],
.chip = {
.base = S5P6450_GPK(0),
.ngpio = S5P6450_GPIO_K_NR,
.label = "GPK",
},
},
};
static struct s3c_gpio_chip s5p6450_gpio_4bit2[] = {
{
.base = S5P64X0_GPG_BASE + 0x4,
.config = &s5p64x0_gpio_cfgs[1],
.chip = {
.base = S5P6450_GPG(0),
.ngpio = S5P6450_GPIO_G_NR,
.label = "GPG",
},
}, {
.base = S5P64X0_GPH_BASE + 0x4,
.config = &s5p64x0_gpio_cfgs[1],
.chip = {
.base = S5P6450_GPH(0),
.ngpio = S5P6450_GPIO_H_NR,
.label = "GPH",
},
},
};
static struct s3c_gpio_chip s5p6450_gpio_rbank_4bit2[] = {
{
.base = S5P64X0_GPR_BASE + 0x4,
.config = &s5p64x0_gpio_cfgs[2],
.chip = {
.base = S5P6450_GPR(0),
.ngpio = S5P6450_GPIO_R_NR,
.label = "GPR",
},
},
};
static struct s3c_gpio_chip s5p6450_gpio_2bit[] = {
{
.base = S5P64X0_GPF_BASE,
.config = &s5p64x0_gpio_cfgs[5],
.chip = {
.base = S5P6450_GPF(0),
.ngpio = S5P6450_GPIO_F_NR,
.label = "GPF",
},
}, {
.base = S5P64X0_GPI_BASE,
.config = &s5p64x0_gpio_cfgs[3],
.chip = {
.base = S5P6450_GPI(0),
.ngpio = S5P6450_GPIO_I_NR,
.label = "GPI",
},
}, {
.base = S5P64X0_GPJ_BASE,
.config = &s5p64x0_gpio_cfgs[3],
.chip = {
.base = S5P6450_GPJ(0),
.ngpio = S5P6450_GPIO_J_NR,
.label = "GPJ",
},
}, {
.base = S5P64X0_GPN_BASE,
.config = &s5p64x0_gpio_cfgs[4],
.chip = {
.base = S5P6450_GPN(0),
.ngpio = S5P6450_GPIO_N_NR,
.label = "GPN",
},
}, {
.base = S5P64X0_GPP_BASE,
.config = &s5p64x0_gpio_cfgs[5],
.chip = {
.base = S5P6450_GPP(0),
.ngpio = S5P6450_GPIO_P_NR,
.label = "GPP",
},
}, {
.base = S5P6450_GPQ_BASE,
.config = &s5p64x0_gpio_cfgs[4],
.chip = {
.base = S5P6450_GPQ(0),
.ngpio = S5P6450_GPIO_Q_NR,
.label = "GPQ",
},
}, {
.base = S5P6450_GPS_BASE,
.config = &s5p64x0_gpio_cfgs[5],
.chip = {
.base = S5P6450_GPS(0),
.ngpio = S5P6450_GPIO_S_NR,
.label = "GPS",
},
},
};
void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
{
for (; nr_chips > 0; nr_chips--, chipcfg++) {
if (!chipcfg->set_config)
chipcfg->set_config = s3c_gpio_setcfg_s3c64xx_4bit;
if (!chipcfg->get_config)
chipcfg->get_config = s3c_gpio_getcfg_s3c64xx_4bit;
if (!chipcfg->set_pull)
chipcfg->set_pull = s3c_gpio_setpull_updown;
if (!chipcfg->get_pull)
chipcfg->get_pull = s3c_gpio_getpull_updown;
}
}
static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
int nr_chips)
{
for (; nr_chips > 0; nr_chips--, chip++) {
chip->chip.direction_input = s5p64x0_gpiolib_rbank_4bit2_input;
chip->chip.direction_output =
s5p64x0_gpiolib_rbank_4bit2_output;
s3c_gpiolib_add(chip);
}
}
static int __init s5p64x0_gpiolib_init(void)
{
s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs,
ARRAY_SIZE(s5p64x0_gpio_cfgs));
if (soc_is_s5p6450()) {
samsung_gpiolib_add_2bit_chips(s5p6450_gpio_2bit,
ARRAY_SIZE(s5p6450_gpio_2bit));
samsung_gpiolib_add_4bit_chips(s5p6450_gpio_4bit,
ARRAY_SIZE(s5p6450_gpio_4bit));
samsung_gpiolib_add_4bit2_chips(s5p6450_gpio_4bit2,
ARRAY_SIZE(s5p6450_gpio_4bit2));
s5p64x0_gpio_add_rbank_4bit2(s5p6450_gpio_rbank_4bit2,
ARRAY_SIZE(s5p6450_gpio_rbank_4bit2));
} else {
samsung_gpiolib_add_2bit_chips(s5p6440_gpio_2bit,
ARRAY_SIZE(s5p6440_gpio_2bit));
samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit,
ARRAY_SIZE(s5p6440_gpio_4bit));
samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
ARRAY_SIZE(s5p6440_gpio_4bit2));
s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2,
ARRAY_SIZE(s5p6440_gpio_rbank_4bit2));
}
return 0;
}
core_initcall(s5p64x0_gpiolib_init);

3
arch/arm/mach-s5p64x0/include/mach/i2c.h → arch/arm/mach-s5p64x0/i2c.h
View File

@ -1,5 +1,4 @@
/* linux/arch/arm/mach-s5p64x0/include/mach/i2c.h
*
/*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*

2
arch/arm/mach-s5p64x0/mach-smdk6440.c
View File

@ -37,7 +37,6 @@
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/i2c.h>
#include <mach/regs-gpio.h>
#include <plat/regs-serial.h>
@ -55,6 +54,7 @@
#include <plat/sdhci.h>
#include "common.h"
#include "i2c.h"
#define SMDK6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \

2
arch/arm/mach-s5p64x0/mach-smdk6450.c
View File

@ -37,7 +37,6 @@
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/i2c.h>
#include <mach/regs-gpio.h>
#include <plat/regs-serial.h>
@ -55,6 +54,7 @@
#include <plat/sdhci.h>
#include "common.h"
#include "i2c.h"
#define SMDK6450_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \

2
arch/arm/mach-s5p64x0/setup-i2c0.c
View File

@ -21,7 +21,7 @@ struct platform_device; /* don't need the contents */
#include <plat/gpio-cfg.h>
#include <linux/platform_data/i2c-s3c2410.h>
#include <mach/i2c.h>
#include "i2c.h"
void s5p6440_i2c0_cfg_gpio(struct platform_device *dev)
{

2
arch/arm/mach-s5p64x0/setup-i2c1.c
View File

@ -21,7 +21,7 @@ struct platform_device; /* don't need the contents */
#include <plat/gpio-cfg.h>
#include <linux/platform_data/i2c-s3c2410.h>
#include <mach/i2c.h>
#include "i2c.h"
void s5p6440_i2c1_cfg_gpio(struct platform_device *dev)
{

3
arch/arm/mach-s5pv210/dev-audio.c
View File

@ -18,7 +18,8 @@
#include <mach/map.h>
#include <mach/dma.h>
#include <mach/irqs.h>
#include <mach/regs-audss.h>
#define S5PV210_AUDSS_INT_MEM (0xC0000000)
static int s5pv210_cfg_i2s(struct platform_device *pdev)
{

18
arch/arm/mach-s5pv210/include/mach/regs-audss.h
View File

@ -1,18 +0,0 @@
/* arch/arm/mach-s5pv210/include/mach/regs-audss.h
*
* Copyright (c) 2011 Samsung Electronics
* http://www.samsung.com
*
* S5PV210 Audio SubSystem clock register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PLAT_REGS_AUDSS_H
#define __PLAT_REGS_AUDSS_H __FILE__
#define S5PV210_AUDSS_INT_MEM (0xC0000000)
#endif /* _PLAT_REGS_AUDSS_H */

15
arch/arm/mach-s5pv210/include/mach/regs-sys.h
View File

@ -1,15 +0,0 @@
/* arch/arm/mach-s5pv210/include/mach/regs-sys.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5PV210 - System registers definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S5PV210_USB_PHY_CON (S3C_VA_SYS + 0xE80C)
#define S5PV210_USB_PHY0_EN (1 << 0)
#define S5PV210_USB_PHY1_EN (1 << 1)

7
arch/arm/mach-s5pv210/setup-usb-phy.c
View File

@ -12,12 +12,17 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <mach/map.h>
#include <mach/regs-sys.h>
#include <plat/cpu.h>
#include <plat/regs-usb-hsotg-phy.h>
#include <plat/usb-phy.h>
#define S5PV210_USB_PHY_CON (S3C_VA_SYS + 0xE80C)
#define S5PV210_USB_PHY0_EN (1 << 0)
#define S5PV210_USB_PHY1_EN (1 << 1)
static int s5pv210_usb_otgphy_init(struct platform_device *pdev)
{
struct clk *xusbxti;

13
arch/arm/plat-samsung/include/plat/gpio-core.h
View File

@ -106,7 +106,18 @@ static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int chi
#else
/* machine specific code should provide samsung_gpiolib_getchip */
#include <mach/gpio-track.h>
extern struct samsung_gpio_chip s3c24xx_gpios[];
static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int pin)
{
struct samsung_gpio_chip *chip;
if (pin > S3C_GPIO_END)
return NULL;
chip = &s3c24xx_gpios[pin/32];
return ((pin - chip->chip.base) < chip->chip.ngpio) ? chip : NULL;
}
static inline void s3c_gpiolib_track(struct samsung_gpio_chip *chip) { }
#endif

1
arch/arm/plat-samsung/include/plat/gpio-fns.h
View File

@ -1 +0,0 @@
#include <plat/gpio-cfg.h>

4
drivers/cpufreq/exynos-cpufreq.c
View File

@ -18,10 +18,10 @@
#include <linux/cpufreq.h>
#include <linux/suspend.h>
#include <mach/cpufreq.h>
#include <plat/cpu.h>
#include "exynos-cpufreq.h"
static struct exynos_dvfs_info *exynos_info;
static struct regulator *arm_regulator;

3
arch/arm/mach-exynos/include/mach/cpufreq.h → drivers/cpufreq/exynos-cpufreq.h
View File

@ -1,5 +1,4 @@
/* linux/arch/arm/mach-exynos/include/mach/cpufreq.h
*
/*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*

3
drivers/cpufreq/exynos4210-cpufreq.c
View File

@ -18,7 +18,8 @@
#include <linux/cpufreq.h>
#include <mach/regs-clock.h>
#include <mach/cpufreq.h>
#include "exynos-cpufreq.h"
#define CPUFREQ_LEVEL_END L5

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