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atmel_spi: clean up SPIv1 quirk handling
Currently, we have a flag called "new_1" which is basically equivalent to cpu_is_at91rm9200(). The latter is also called directly a few places. Clean up this mess by introducing a atmel_spi_v2() function for determining the controller version, and move all version dependent code over to use it. This allows us to remove the new_1 flag. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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@ -30,13 +30,6 @@
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* The core SPI transfer engine just talks to a register bank to set up
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* DMA transfers; transfer queue progress is driven by IRQs. The clock
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* framework provides the base clock, subdivided for each spi_device.
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*
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* Newer controllers, marked with "new_1" flag, have:
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* - CR.LASTXFER
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* - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
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* - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
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* - SPI_CSRx.CSAAT
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* - SPI_CSRx.SBCR allows faster clocking
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*/
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struct atmel_spi {
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spinlock_t lock;
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@ -45,7 +38,6 @@ struct atmel_spi {
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int irq;
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struct clk *clk;
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struct platform_device *pdev;
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unsigned new_1:1;
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struct spi_device *stay;
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u8 stopping;
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@ -62,6 +54,23 @@ struct atmel_spi {
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#define BUFFER_SIZE PAGE_SIZE
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#define INVALID_DMA_ADDRESS 0xffffffff
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/*
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* Version 2 of the SPI controller has
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* - CR.LASTXFER
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* - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
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* - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
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* - SPI_CSRx.CSAAT
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* - SPI_CSRx.SBCR allows faster clocking
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*
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* We can determine the controller version by reading the VERSION
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* register, but I haven't checked that it exists on all chips, and
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* this is cheaper anyway.
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*/
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static bool atmel_spi_is_v2(void)
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{
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return !cpu_is_at91rm9200();
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}
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/*
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* Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
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* they assume that spi slave device state will not change on deselect, so
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@ -105,7 +114,7 @@ static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
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gpio, active ? " (high)" : "",
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mr);
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if (!(cpu_is_at91rm9200() && spi->chip_select == 0))
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if (atmel_spi_is_v2() || spi->chip_select != 0)
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gpio_set_value(gpio, active);
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spi_writel(as, MR, mr);
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}
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@ -129,7 +138,7 @@ static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
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gpio, active ? " (low)" : "",
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mr);
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if (!(cpu_is_at91rm9200() && spi->chip_select == 0))
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if (atmel_spi_is_v2() || spi->chip_select != 0)
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gpio_set_value(gpio, !active);
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}
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@ -536,19 +545,16 @@ static int atmel_spi_setup(struct spi_device *spi)
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}
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/* see notes above re chipselect */
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if (cpu_is_at91rm9200()
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if (!atmel_spi_is_v2()
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&& spi->chip_select == 0
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&& (spi->mode & SPI_CS_HIGH)) {
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dev_dbg(&spi->dev, "setup: can't be active-high\n");
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return -EINVAL;
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}
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/*
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* Pre-new_1 chips start out at half the peripheral
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* bus speed.
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*/
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/* v1 chips start out at half the peripheral bus speed. */
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bus_hz = clk_get_rate(as->clk);
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if (!as->new_1)
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if (!atmel_spi_is_v2())
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bus_hz /= 2;
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if (spi->max_speed_hz) {
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@ -755,8 +761,6 @@ static int __init atmel_spi_probe(struct platform_device *pdev)
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goto out_free_buffer;
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as->irq = irq;
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as->clk = clk;
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if (!cpu_is_at91rm9200())
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as->new_1 = 1;
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ret = request_irq(irq, atmel_spi_interrupt, 0,
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pdev->dev.bus_id, master);
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