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https://github.com/FEX-Emu/linux.git
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[POWERPC] Use 4kB iommu pages even on 64kB-page systems
The 10Gigabit ethernet device drivers appear to be able to chew up all 256MB of TCE mappings on pSeries systems, as evidenced by numerous error messages: iommu_alloc failed, tbl c0000000010d5c48 vaddr c0000000d875eff0 npages 1 Some experimentation indicates that this is essentially because one 1500 byte ethernet MTU gets mapped as a 64K DMA region when the large 64K pages are enabled. Thus, it doesn't take much to exhaust all of the available DMA mappings for a high-speed card. This patch changes the iommu allocator to work with its own unique, distinct page size. Although the patch is long, its actually quite simple: it just #defines a distinct IOMMU_PAGE_SIZE and then uses this in all the places that matter. As a side effect, it also dramatically improves network performance on platforms with H-calls on iommu translation inserts/removes (since we no longer call it 16 times for a 1500 bytes packet when the iommu HW is still 4k). In the future, we might want to make the IOMMU_PAGE_SIZE a variable in the iommu_table instance, thus allowing support for different HW page sizes in the iommu itself. Signed-off-by: Linas Vepstas <linas@austin.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Linas Vepstas
Paul Mackerras
parent
dd6c89f686
commit
5d2efba64b
@ -47,6 +47,17 @@ static int novmerge = 0;
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static int novmerge = 1;
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#endif
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static inline unsigned long iommu_num_pages(unsigned long vaddr,
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unsigned long slen)
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{
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unsigned long npages;
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npages = IOMMU_PAGE_ALIGN(vaddr + slen) - (vaddr & IOMMU_PAGE_MASK);
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npages >>= IOMMU_PAGE_SHIFT;
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return npages;
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}
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static int __init setup_iommu(char *str)
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{
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if (!strcmp(str, "novmerge"))
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@ -178,10 +189,10 @@ static dma_addr_t iommu_alloc(struct iommu_table *tbl, void *page,
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}
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entry += tbl->it_offset; /* Offset into real TCE table */
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ret = entry << PAGE_SHIFT; /* Set the return dma address */
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ret = entry << IOMMU_PAGE_SHIFT; /* Set the return dma address */
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/* Put the TCEs in the HW table */
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ppc_md.tce_build(tbl, entry, npages, (unsigned long)page & PAGE_MASK,
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ppc_md.tce_build(tbl, entry, npages, (unsigned long)page & IOMMU_PAGE_MASK,
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direction);
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@ -203,7 +214,7 @@ static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
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unsigned long entry, free_entry;
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unsigned long i;
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entry = dma_addr >> PAGE_SHIFT;
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entry = dma_addr >> IOMMU_PAGE_SHIFT;
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free_entry = entry - tbl->it_offset;
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if (((free_entry + npages) > tbl->it_size) ||
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@ -270,7 +281,7 @@ int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
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/* Init first segment length for backout at failure */
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outs->dma_length = 0;
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DBG("mapping %d elements:\n", nelems);
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DBG("sg mapping %d elements:\n", nelems);
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spin_lock_irqsave(&(tbl->it_lock), flags);
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@ -285,9 +296,8 @@ int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
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}
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/* Allocate iommu entries for that segment */
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vaddr = (unsigned long)page_address(s->page) + s->offset;
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npages = PAGE_ALIGN(vaddr + slen) - (vaddr & PAGE_MASK);
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npages >>= PAGE_SHIFT;
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entry = iommu_range_alloc(tbl, npages, &handle, mask >> PAGE_SHIFT, 0);
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npages = iommu_num_pages(vaddr, slen);
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entry = iommu_range_alloc(tbl, npages, &handle, mask >> IOMMU_PAGE_SHIFT, 0);
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DBG(" - vaddr: %lx, size: %lx\n", vaddr, slen);
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@ -301,14 +311,14 @@ int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
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/* Convert entry to a dma_addr_t */
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entry += tbl->it_offset;
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dma_addr = entry << PAGE_SHIFT;
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dma_addr |= s->offset;
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dma_addr = entry << IOMMU_PAGE_SHIFT;
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dma_addr |= (s->offset & ~IOMMU_PAGE_MASK);
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DBG(" - %lx pages, entry: %lx, dma_addr: %lx\n",
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DBG(" - %lu pages, entry: %lx, dma_addr: %lx\n",
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npages, entry, dma_addr);
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/* Insert into HW table */
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ppc_md.tce_build(tbl, entry, npages, vaddr & PAGE_MASK, direction);
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ppc_md.tce_build(tbl, entry, npages, vaddr & IOMMU_PAGE_MASK, direction);
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/* If we are in an open segment, try merging */
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if (segstart != s) {
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@ -323,7 +333,7 @@ int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
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DBG(" can't merge, new segment.\n");
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} else {
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outs->dma_length += s->length;
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DBG(" merged, new len: %lx\n", outs->dma_length);
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DBG(" merged, new len: %ux\n", outs->dma_length);
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}
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}
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@ -367,9 +377,8 @@ int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
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if (s->dma_length != 0) {
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unsigned long vaddr, npages;
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vaddr = s->dma_address & PAGE_MASK;
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npages = (PAGE_ALIGN(s->dma_address + s->dma_length) - vaddr)
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>> PAGE_SHIFT;
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vaddr = s->dma_address & IOMMU_PAGE_MASK;
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npages = iommu_num_pages(s->dma_address, s->dma_length);
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__iommu_free(tbl, vaddr, npages);
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s->dma_address = DMA_ERROR_CODE;
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s->dma_length = 0;
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@ -398,8 +407,7 @@ void iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
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if (sglist->dma_length == 0)
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break;
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npages = (PAGE_ALIGN(dma_handle + sglist->dma_length)
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- (dma_handle & PAGE_MASK)) >> PAGE_SHIFT;
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npages = iommu_num_pages(dma_handle,sglist->dma_length);
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__iommu_free(tbl, dma_handle, npages);
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sglist++;
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}
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@ -532,12 +540,11 @@ dma_addr_t iommu_map_single(struct iommu_table *tbl, void *vaddr,
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BUG_ON(direction == DMA_NONE);
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uaddr = (unsigned long)vaddr;
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npages = PAGE_ALIGN(uaddr + size) - (uaddr & PAGE_MASK);
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npages >>= PAGE_SHIFT;
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npages = iommu_num_pages(uaddr, size);
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if (tbl) {
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dma_handle = iommu_alloc(tbl, vaddr, npages, direction,
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mask >> PAGE_SHIFT, 0);
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mask >> IOMMU_PAGE_SHIFT, 0);
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if (dma_handle == DMA_ERROR_CODE) {
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if (printk_ratelimit()) {
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printk(KERN_INFO "iommu_alloc failed, "
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@ -545,7 +552,7 @@ dma_addr_t iommu_map_single(struct iommu_table *tbl, void *vaddr,
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tbl, vaddr, npages);
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}
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} else
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dma_handle |= (uaddr & ~PAGE_MASK);
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dma_handle |= (uaddr & ~IOMMU_PAGE_MASK);
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}
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return dma_handle;
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@ -554,11 +561,14 @@ dma_addr_t iommu_map_single(struct iommu_table *tbl, void *vaddr,
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void iommu_unmap_single(struct iommu_table *tbl, dma_addr_t dma_handle,
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size_t size, enum dma_data_direction direction)
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{
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unsigned int npages;
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BUG_ON(direction == DMA_NONE);
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if (tbl)
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iommu_free(tbl, dma_handle, (PAGE_ALIGN(dma_handle + size) -
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(dma_handle & PAGE_MASK)) >> PAGE_SHIFT);
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if (tbl) {
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npages = iommu_num_pages(dma_handle, size);
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iommu_free(tbl, dma_handle, npages);
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}
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}
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/* Allocates a contiguous real buffer and creates mappings over it.
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@ -570,11 +580,11 @@ void *iommu_alloc_coherent(struct iommu_table *tbl, size_t size,
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{
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void *ret = NULL;
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dma_addr_t mapping;
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unsigned int npages, order;
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unsigned int order;
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unsigned int nio_pages, io_order;
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struct page *page;
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size = PAGE_ALIGN(size);
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npages = size >> PAGE_SHIFT;
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order = get_order(size);
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/*
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@ -598,8 +608,10 @@ void *iommu_alloc_coherent(struct iommu_table *tbl, size_t size,
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memset(ret, 0, size);
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/* Set up tces to cover the allocated range */
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mapping = iommu_alloc(tbl, ret, npages, DMA_BIDIRECTIONAL,
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mask >> PAGE_SHIFT, order);
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nio_pages = size >> IOMMU_PAGE_SHIFT;
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io_order = get_iommu_order(size);
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mapping = iommu_alloc(tbl, ret, nio_pages, DMA_BIDIRECTIONAL,
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mask >> IOMMU_PAGE_SHIFT, io_order);
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if (mapping == DMA_ERROR_CODE) {
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free_pages((unsigned long)ret, order);
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return NULL;
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@ -611,12 +623,13 @@ void *iommu_alloc_coherent(struct iommu_table *tbl, size_t size,
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void iommu_free_coherent(struct iommu_table *tbl, size_t size,
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void *vaddr, dma_addr_t dma_handle)
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{
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unsigned int npages;
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if (tbl) {
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unsigned int nio_pages;
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size = PAGE_ALIGN(size);
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nio_pages = size >> IOMMU_PAGE_SHIFT;
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iommu_free(tbl, dma_handle, nio_pages);
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size = PAGE_ALIGN(size);
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npages = size >> PAGE_SHIFT;
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iommu_free(tbl, dma_handle, npages);
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free_pages((unsigned long)vaddr, get_order(size));
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}
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}
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@ -92,9 +92,9 @@ static struct iommu_table *vio_build_iommu_table(struct vio_dev *dev)
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&tbl->it_index, &offset, &size);
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/* TCE table size - measured in tce entries */
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tbl->it_size = size >> PAGE_SHIFT;
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tbl->it_size = size >> IOMMU_PAGE_SHIFT;
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/* offset for VIO should always be 0 */
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tbl->it_offset = offset >> PAGE_SHIFT;
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tbl->it_offset = offset >> IOMMU_PAGE_SHIFT;
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tbl->it_busno = 0;
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tbl->it_type = TCE_VB;
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@ -43,9 +43,6 @@ static void tce_build_iSeries(struct iommu_table *tbl, long index, long npages,
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u64 rc;
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u64 tce, rpn;
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index <<= TCE_PAGE_FACTOR;
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npages <<= TCE_PAGE_FACTOR;
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while (npages--) {
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rpn = virt_to_abs(uaddr) >> TCE_SHIFT;
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tce = (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
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@ -75,9 +72,6 @@ static void tce_free_iSeries(struct iommu_table *tbl, long index, long npages)
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{
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u64 rc;
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npages <<= TCE_PAGE_FACTOR;
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index <<= TCE_PAGE_FACTOR;
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while (npages--) {
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rc = HvCallXm_setTce((u64)tbl->it_index, (u64)index, 0);
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if (rc)
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@ -136,10 +130,9 @@ void iommu_table_getparms_iSeries(unsigned long busno,
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panic("PCI_DMA: parms->size is zero, parms is 0x%p", parms);
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/* itc_size is in pages worth of table, it_size is in # of entries */
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tbl->it_size = ((parms->itc_size * TCE_PAGE_SIZE) /
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TCE_ENTRY_SIZE) >> TCE_PAGE_FACTOR;
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tbl->it_size = (parms->itc_size * TCE_PAGE_SIZE) / TCE_ENTRY_SIZE;
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tbl->it_busno = parms->itc_busno;
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tbl->it_offset = parms->itc_offset >> TCE_PAGE_FACTOR;
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tbl->it_offset = parms->itc_offset;
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tbl->it_index = parms->itc_index;
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tbl->it_blocksize = 1;
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tbl->it_type = virtbus ? TCE_VB : TCE_PCI;
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@ -57,9 +57,6 @@ static void tce_build_pSeries(struct iommu_table *tbl, long index,
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u64 *tcep;
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u64 rpn;
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index <<= TCE_PAGE_FACTOR;
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npages <<= TCE_PAGE_FACTOR;
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proto_tce = TCE_PCI_READ; // Read allowed
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if (direction != DMA_TO_DEVICE)
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@ -82,9 +79,6 @@ static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
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{
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u64 *tcep;
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npages <<= TCE_PAGE_FACTOR;
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index <<= TCE_PAGE_FACTOR;
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tcep = ((u64 *)tbl->it_base) + index;
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while (npages--)
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@ -95,7 +89,6 @@ static unsigned long tce_get_pseries(struct iommu_table *tbl, long index)
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{
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u64 *tcep;
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index <<= TCE_PAGE_FACTOR;
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tcep = ((u64 *)tbl->it_base) + index;
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return *tcep;
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@ -109,9 +102,6 @@ static void tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum,
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u64 proto_tce, tce;
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u64 rpn;
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tcenum <<= TCE_PAGE_FACTOR;
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npages <<= TCE_PAGE_FACTOR;
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rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
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proto_tce = TCE_PCI_READ;
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if (direction != DMA_TO_DEVICE)
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@ -146,7 +136,7 @@ static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
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u64 rpn;
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long l, limit;
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if (TCE_PAGE_FACTOR == 0 && npages == 1)
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if (npages == 1)
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return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
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direction);
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@ -164,9 +154,6 @@ static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
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__get_cpu_var(tce_page) = tcep;
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}
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tcenum <<= TCE_PAGE_FACTOR;
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npages <<= TCE_PAGE_FACTOR;
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rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
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proto_tce = TCE_PCI_READ;
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if (direction != DMA_TO_DEVICE)
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@ -207,9 +194,6 @@ static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages
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{
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u64 rc;
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tcenum <<= TCE_PAGE_FACTOR;
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npages <<= TCE_PAGE_FACTOR;
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while (npages--) {
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rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, 0);
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@ -229,9 +213,6 @@ static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long n
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{
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u64 rc;
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tcenum <<= TCE_PAGE_FACTOR;
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npages <<= TCE_PAGE_FACTOR;
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rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages);
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if (rc && printk_ratelimit()) {
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@ -248,7 +229,6 @@ static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum)
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u64 rc;
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unsigned long tce_ret;
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tcenum <<= TCE_PAGE_FACTOR;
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rc = plpar_tce_get((u64)tbl->it_index, (u64)tcenum << 12, &tce_ret);
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if (rc && printk_ratelimit()) {
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@ -289,7 +269,7 @@ static void iommu_table_setparms(struct pci_controller *phb,
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tbl->it_busno = phb->bus->number;
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/* Units of tce entries */
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tbl->it_offset = phb->dma_window_base_cur >> PAGE_SHIFT;
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tbl->it_offset = phb->dma_window_base_cur >> IOMMU_PAGE_SHIFT;
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/* Test if we are going over 2GB of DMA space */
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if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) {
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@ -300,7 +280,7 @@ static void iommu_table_setparms(struct pci_controller *phb,
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phb->dma_window_base_cur += phb->dma_window_size;
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/* Set the tce table size - measured in entries */
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tbl->it_size = phb->dma_window_size >> PAGE_SHIFT;
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tbl->it_size = phb->dma_window_size >> IOMMU_PAGE_SHIFT;
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tbl->it_index = 0;
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tbl->it_blocksize = 16;
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@ -325,8 +305,8 @@ static void iommu_table_setparms_lpar(struct pci_controller *phb,
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tbl->it_base = 0;
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tbl->it_blocksize = 16;
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tbl->it_type = TCE_PCI;
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tbl->it_offset = offset >> PAGE_SHIFT;
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tbl->it_size = size >> PAGE_SHIFT;
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tbl->it_offset = offset >> IOMMU_PAGE_SHIFT;
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tbl->it_size = size >> IOMMU_PAGE_SHIFT;
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}
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static void iommu_bus_setup_pSeries(struct pci_bus *bus)
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@ -522,8 +502,6 @@ static void iommu_dev_setup_pSeriesLP(struct pci_dev *dev)
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const void *dma_window = NULL;
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struct pci_dn *pci;
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DBG("iommu_dev_setup_pSeriesLP, dev %p (%s)\n", dev, pci_name(dev));
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/* dev setup for LPAR is a little tricky, since the device tree might
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* contain the dma-window properties per-device and not neccesarily
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* for the bus. So we need to search upwards in the tree until we
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@ -532,6 +510,9 @@ static void iommu_dev_setup_pSeriesLP(struct pci_dev *dev)
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*/
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dn = pci_device_to_OF_node(dev);
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DBG("iommu_dev_setup_pSeriesLP, dev %p (%s) %s\n",
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dev, pci_name(dev), dn->full_name);
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for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table;
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pdn = pdn->parent) {
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dma_window = get_property(pdn, "ibm,dma-window", NULL);
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@ -72,7 +72,6 @@
|
||||
|
||||
#define DART_PAGE_SHIFT 12
|
||||
#define DART_PAGE_SIZE (1 << DART_PAGE_SHIFT)
|
||||
#define DART_PAGE_FACTOR (PAGE_SHIFT - DART_PAGE_SHIFT)
|
||||
|
||||
|
||||
#endif /* _POWERPC_SYSDEV_DART_H */
|
||||
|
||||
@ -156,9 +156,6 @@ static void dart_build(struct iommu_table *tbl, long index,
|
||||
|
||||
DBG("dart: build at: %lx, %lx, addr: %x\n", index, npages, uaddr);
|
||||
|
||||
index <<= DART_PAGE_FACTOR;
|
||||
npages <<= DART_PAGE_FACTOR;
|
||||
|
||||
dp = ((unsigned int*)tbl->it_base) + index;
|
||||
|
||||
/* On U3, all memory is contigous, so we can move this
|
||||
@ -199,9 +196,6 @@ static void dart_free(struct iommu_table *tbl, long index, long npages)
|
||||
|
||||
DBG("dart: free at: %lx, %lx\n", index, npages);
|
||||
|
||||
index <<= DART_PAGE_FACTOR;
|
||||
npages <<= DART_PAGE_FACTOR;
|
||||
|
||||
dp = ((unsigned int *)tbl->it_base) + index;
|
||||
|
||||
while (npages--)
|
||||
@ -281,7 +275,7 @@ static void iommu_table_dart_setup(void)
|
||||
iommu_table_dart.it_busno = 0;
|
||||
iommu_table_dart.it_offset = 0;
|
||||
/* it_size is in number of entries */
|
||||
iommu_table_dart.it_size = (dart_tablesize / sizeof(u32)) >> DART_PAGE_FACTOR;
|
||||
iommu_table_dart.it_size = dart_tablesize / sizeof(u32);
|
||||
|
||||
/* Initialize the common IOMMU code */
|
||||
iommu_table_dart.it_base = (unsigned long)dart_vbase;
|
||||
|
||||
@ -22,17 +22,35 @@
|
||||
#define _ASM_IOMMU_H
|
||||
#ifdef __KERNEL__
|
||||
|
||||
#include <asm/types.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <asm/types.h>
|
||||
#include <asm/bitops.h>
|
||||
|
||||
#define IOMMU_PAGE_SHIFT 12
|
||||
#define IOMMU_PAGE_SIZE (ASM_CONST(1) << IOMMU_PAGE_SHIFT)
|
||||
#define IOMMU_PAGE_MASK (~((1 << IOMMU_PAGE_SHIFT) - 1))
|
||||
#define IOMMU_PAGE_ALIGN(addr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/* Pure 2^n version of get_order */
|
||||
static __inline__ __attribute_const__ int get_iommu_order(unsigned long size)
|
||||
{
|
||||
return __ilog2((size - 1) >> IOMMU_PAGE_SHIFT) + 1;
|
||||
}
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
|
||||
/*
|
||||
* IOMAP_MAX_ORDER defines the largest contiguous block
|
||||
* of dma space we can get. IOMAP_MAX_ORDER = 13
|
||||
* allows up to 2**12 pages (4096 * 4096) = 16 MB
|
||||
*/
|
||||
#define IOMAP_MAX_ORDER 13
|
||||
#define IOMAP_MAX_ORDER 13
|
||||
|
||||
struct iommu_table {
|
||||
unsigned long it_busno; /* Bus number this table belongs to */
|
||||
|
||||
@ -22,6 +22,8 @@
|
||||
#define _ASM_POWERPC_TCE_H
|
||||
#ifdef __KERNEL__
|
||||
|
||||
#include <asm/iommu.h>
|
||||
|
||||
/*
|
||||
* Tces come in two formats, one for the virtual bus and a different
|
||||
* format for PCI
|
||||
@ -33,7 +35,6 @@
|
||||
|
||||
#define TCE_SHIFT 12
|
||||
#define TCE_PAGE_SIZE (1 << TCE_SHIFT)
|
||||
#define TCE_PAGE_FACTOR (PAGE_SHIFT - TCE_SHIFT)
|
||||
|
||||
#define TCE_ENTRY_SIZE 8 /* each TCE is 64 bits */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user