mirror of
https://github.com/FEX-Emu/linux.git
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Merge branch 'work/fifomerge'
This commit is contained in:
Tomi Valkeinen
commit
5e36097889
@ -105,6 +105,9 @@ static struct {
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struct ovl_priv_data ovl_priv_data_array[MAX_DSS_OVERLAYS];
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struct mgr_priv_data mgr_priv_data_array[MAX_DSS_MANAGERS];
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bool fifo_merge_dirty;
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bool fifo_merge;
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bool irq_enabled;
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} dss_data;
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@ -585,11 +588,40 @@ static void dss_mgr_write_regs(struct omap_overlay_manager *mgr)
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}
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}
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static void dss_write_regs_common(void)
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{
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const int num_mgrs = omap_dss_get_num_overlay_managers();
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int i;
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if (!dss_data.fifo_merge_dirty)
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return;
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for (i = 0; i < num_mgrs; ++i) {
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struct omap_overlay_manager *mgr;
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struct mgr_priv_data *mp;
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mgr = omap_dss_get_overlay_manager(i);
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mp = get_mgr_priv(mgr);
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if (mp->enabled) {
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if (dss_data.fifo_merge_dirty) {
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dispc_enable_fifomerge(dss_data.fifo_merge);
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dss_data.fifo_merge_dirty = false;
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}
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if (mp->updating)
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mp->shadow_info_dirty = true;
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}
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}
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}
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static void dss_write_regs(void)
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{
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const int num_mgrs = omap_dss_get_num_overlay_managers();
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int i;
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dss_write_regs_common();
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for (i = 0; i < num_mgrs; ++i) {
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struct omap_overlay_manager *mgr;
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struct mgr_priv_data *mp;
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@ -659,6 +691,8 @@ void dss_mgr_start_update(struct omap_overlay_manager *mgr)
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dss_mgr_write_regs(mgr);
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dss_write_regs_common();
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mp->updating = true;
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if (!dss_data.irq_enabled && need_isr())
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@ -859,11 +893,20 @@ static void dss_apply_ovl_fifo_thresholds(struct omap_overlay *ovl,
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op->extra_info_dirty = true;
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}
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static void dss_ovl_setup_fifo(struct omap_overlay *ovl)
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static void dss_apply_fifo_merge(bool use_fifo_merge)
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{
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if (dss_data.fifo_merge == use_fifo_merge)
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return;
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dss_data.fifo_merge = use_fifo_merge;
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dss_data.fifo_merge_dirty = true;
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}
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static void dss_ovl_setup_fifo(struct omap_overlay *ovl,
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bool use_fifo_merge)
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{
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struct ovl_priv_data *op = get_ovl_priv(ovl);
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struct omap_dss_device *dssdev;
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u32 size, burst_size;
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u32 fifo_low, fifo_high;
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if (!op->enabled && !op->enabling)
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@ -871,33 +914,14 @@ static void dss_ovl_setup_fifo(struct omap_overlay *ovl)
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dssdev = ovl->manager->device;
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size = dispc_ovl_get_fifo_size(ovl->id);
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burst_size = dispc_ovl_get_burst_size(ovl->id);
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switch (dssdev->type) {
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case OMAP_DISPLAY_TYPE_DPI:
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case OMAP_DISPLAY_TYPE_DBI:
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case OMAP_DISPLAY_TYPE_SDI:
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case OMAP_DISPLAY_TYPE_VENC:
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case OMAP_DISPLAY_TYPE_HDMI:
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default_get_overlay_fifo_thresholds(ovl->id, size,
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burst_size, &fifo_low, &fifo_high);
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break;
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#ifdef CONFIG_OMAP2_DSS_DSI
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case OMAP_DISPLAY_TYPE_DSI:
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dsi_get_overlay_fifo_thresholds(ovl->id, size,
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burst_size, &fifo_low, &fifo_high);
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break;
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#endif
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default:
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BUG();
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}
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dispc_ovl_compute_fifo_thresholds(ovl->id, &fifo_low, &fifo_high,
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use_fifo_merge);
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dss_apply_ovl_fifo_thresholds(ovl, fifo_low, fifo_high);
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}
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static void dss_mgr_setup_fifos(struct omap_overlay_manager *mgr)
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static void dss_mgr_setup_fifos(struct omap_overlay_manager *mgr,
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bool use_fifo_merge)
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{
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struct omap_overlay *ovl;
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struct mgr_priv_data *mp;
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@ -908,10 +932,10 @@ static void dss_mgr_setup_fifos(struct omap_overlay_manager *mgr)
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return;
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list_for_each_entry(ovl, &mgr->overlays, list)
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dss_ovl_setup_fifo(ovl);
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dss_ovl_setup_fifo(ovl, use_fifo_merge);
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}
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static void dss_setup_fifos(void)
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static void dss_setup_fifos(bool use_fifo_merge)
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{
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const int num_mgrs = omap_dss_get_num_overlay_managers();
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struct omap_overlay_manager *mgr;
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@ -919,15 +943,91 @@ static void dss_setup_fifos(void)
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for (i = 0; i < num_mgrs; ++i) {
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mgr = omap_dss_get_overlay_manager(i);
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dss_mgr_setup_fifos(mgr);
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dss_mgr_setup_fifos(mgr, use_fifo_merge);
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}
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}
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static int get_num_used_managers(void)
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{
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const int num_mgrs = omap_dss_get_num_overlay_managers();
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struct omap_overlay_manager *mgr;
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struct mgr_priv_data *mp;
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int i;
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int enabled_mgrs;
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enabled_mgrs = 0;
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for (i = 0; i < num_mgrs; ++i) {
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mgr = omap_dss_get_overlay_manager(i);
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mp = get_mgr_priv(mgr);
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if (!mp->enabled)
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continue;
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enabled_mgrs++;
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}
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return enabled_mgrs;
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}
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static int get_num_used_overlays(void)
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{
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const int num_ovls = omap_dss_get_num_overlays();
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struct omap_overlay *ovl;
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struct ovl_priv_data *op;
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struct mgr_priv_data *mp;
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int i;
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int enabled_ovls;
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enabled_ovls = 0;
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for (i = 0; i < num_ovls; ++i) {
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ovl = omap_dss_get_overlay(i);
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op = get_ovl_priv(ovl);
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if (!op->enabled && !op->enabling)
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continue;
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mp = get_mgr_priv(ovl->manager);
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if (!mp->enabled)
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continue;
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enabled_ovls++;
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}
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return enabled_ovls;
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}
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static bool get_use_fifo_merge(void)
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{
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int enabled_mgrs = get_num_used_managers();
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int enabled_ovls = get_num_used_overlays();
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if (!dss_has_feature(FEAT_FIFO_MERGE))
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return false;
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/*
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* In theory the only requirement for fifomerge is enabled_ovls <= 1.
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* However, if we have two managers enabled and set/unset the fifomerge,
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* we need to set the GO bits in particular sequence for the managers,
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* and wait in between.
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*
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* This is rather difficult as new apply calls can happen at any time,
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* so we simplify the problem by requiring also that enabled_mgrs <= 1.
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* In practice this shouldn't matter, because when only one overlay is
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* enabled, most likely only one output is enabled.
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*/
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return enabled_mgrs <= 1 && enabled_ovls <= 1;
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}
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int dss_mgr_enable(struct omap_overlay_manager *mgr)
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{
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struct mgr_priv_data *mp = get_mgr_priv(mgr);
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unsigned long flags;
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int r;
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bool fifo_merge;
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mutex_lock(&apply_lock);
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@ -945,11 +1045,23 @@ int dss_mgr_enable(struct omap_overlay_manager *mgr)
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goto err;
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}
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dss_setup_fifos();
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/* step 1: setup fifos/fifomerge before enabling the manager */
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fifo_merge = get_use_fifo_merge();
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dss_setup_fifos(fifo_merge);
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dss_apply_fifo_merge(fifo_merge);
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dss_write_regs();
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dss_set_go_bits();
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spin_unlock_irqrestore(&data_lock, flags);
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/* wait until fifo config is in */
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wait_pending_extra_info_updates();
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/* step 2: enable the manager */
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spin_lock_irqsave(&data_lock, flags);
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if (!mgr_manual_update(mgr))
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mp->updating = true;
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@ -974,6 +1086,7 @@ void dss_mgr_disable(struct omap_overlay_manager *mgr)
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{
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struct mgr_priv_data *mp = get_mgr_priv(mgr);
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unsigned long flags;
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bool fifo_merge;
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mutex_lock(&apply_lock);
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@ -988,8 +1101,16 @@ void dss_mgr_disable(struct omap_overlay_manager *mgr)
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mp->updating = false;
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mp->enabled = false;
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fifo_merge = get_use_fifo_merge();
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dss_setup_fifos(fifo_merge);
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dss_apply_fifo_merge(fifo_merge);
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dss_write_regs();
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dss_set_go_bits();
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spin_unlock_irqrestore(&data_lock, flags);
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wait_pending_extra_info_updates();
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out:
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mutex_unlock(&apply_lock);
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}
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@ -1241,6 +1362,7 @@ int dss_ovl_enable(struct omap_overlay *ovl)
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{
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struct ovl_priv_data *op = get_ovl_priv(ovl);
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unsigned long flags;
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bool fifo_merge;
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int r;
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mutex_lock(&apply_lock);
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@ -1266,7 +1388,22 @@ int dss_ovl_enable(struct omap_overlay *ovl)
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goto err2;
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}
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dss_setup_fifos();
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/* step 1: configure fifos/fifomerge for currently enabled ovls */
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fifo_merge = get_use_fifo_merge();
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dss_setup_fifos(fifo_merge);
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dss_apply_fifo_merge(fifo_merge);
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dss_write_regs();
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dss_set_go_bits();
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spin_unlock_irqrestore(&data_lock, flags);
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/* wait for fifo configs to go in */
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wait_pending_extra_info_updates();
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/* step 2: enable the overlay */
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spin_lock_irqsave(&data_lock, flags);
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op->enabling = false;
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dss_apply_ovl_enable(ovl, true);
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@ -1276,6 +1413,9 @@ int dss_ovl_enable(struct omap_overlay *ovl)
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spin_unlock_irqrestore(&data_lock, flags);
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/* wait for overlay to be enabled */
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wait_pending_extra_info_updates();
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mutex_unlock(&apply_lock);
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return 0;
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@ -1291,6 +1431,7 @@ int dss_ovl_disable(struct omap_overlay *ovl)
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{
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struct ovl_priv_data *op = get_ovl_priv(ovl);
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unsigned long flags;
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bool fifo_merge;
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int r;
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mutex_lock(&apply_lock);
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@ -1305,14 +1446,34 @@ int dss_ovl_disable(struct omap_overlay *ovl)
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goto err;
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}
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/* step 1: disable the overlay */
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spin_lock_irqsave(&data_lock, flags);
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dss_apply_ovl_enable(ovl, false);
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dss_write_regs();
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dss_set_go_bits();
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spin_unlock_irqrestore(&data_lock, flags);
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/* wait for the overlay to be disabled */
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wait_pending_extra_info_updates();
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/* step 2: configure fifos/fifomerge */
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spin_lock_irqsave(&data_lock, flags);
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fifo_merge = get_use_fifo_merge();
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dss_setup_fifos(fifo_merge);
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dss_apply_fifo_merge(fifo_merge);
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dss_write_regs();
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dss_set_go_bits();
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spin_unlock_irqrestore(&data_lock, flags);
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/* wait for fifo config to go in */
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wait_pending_extra_info_updates();
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mutex_unlock(&apply_lock);
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return 0;
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@ -909,7 +909,7 @@ static void dispc_configure_burst_sizes(void)
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dispc_ovl_set_burst_size(i, burst_size);
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}
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u32 dispc_ovl_get_burst_size(enum omap_plane plane)
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static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
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{
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unsigned unit = dss_feat_get_burst_size_unit();
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/* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
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@ -1018,7 +1018,7 @@ static void dispc_read_plane_fifo_sizes(void)
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}
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}
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u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
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static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
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{
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return dispc.fifo_size[plane];
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}
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@ -1039,13 +1039,13 @@ void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
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dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
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dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
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|
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DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
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DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
|
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plane,
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REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
|
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lo_start, lo_end),
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lo_start, lo_end) * unit,
|
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REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
|
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hi_start, hi_end),
|
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low, high);
|
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hi_start, hi_end) * unit,
|
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low * unit, high * unit);
|
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|
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dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
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FLD_VAL(high, hi_start, hi_end) |
|
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@ -1054,10 +1054,53 @@ void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
|
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|
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void dispc_enable_fifomerge(bool enable)
|
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{
|
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if (!dss_has_feature(FEAT_FIFO_MERGE)) {
|
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WARN_ON(enable);
|
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return;
|
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}
|
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|
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DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
|
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REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
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}
|
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|
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void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
|
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u32 *fifo_low, u32 *fifo_high, bool use_fifomerge)
|
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{
|
||||
/*
|
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* All sizes are in bytes. Both the buffer and burst are made of
|
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* buffer_units, and the fifo thresholds must be buffer_unit aligned.
|
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*/
|
||||
|
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unsigned buf_unit = dss_feat_get_buffer_size_unit();
|
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unsigned ovl_fifo_size, total_fifo_size, burst_size;
|
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int i;
|
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|
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burst_size = dispc_ovl_get_burst_size(plane);
|
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ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
|
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|
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if (use_fifomerge) {
|
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total_fifo_size = 0;
|
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for (i = 0; i < omap_dss_get_num_overlays(); ++i)
|
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total_fifo_size += dispc_ovl_get_fifo_size(i);
|
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} else {
|
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total_fifo_size = ovl_fifo_size;
|
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}
|
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|
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/*
|
||||
* We use the same low threshold for both fifomerge and non-fifomerge
|
||||
* cases, but for fifomerge we calculate the high threshold using the
|
||||
* combined fifo size
|
||||
*/
|
||||
|
||||
if (dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
|
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*fifo_low = ovl_fifo_size - burst_size * 2;
|
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*fifo_high = total_fifo_size - burst_size;
|
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} else {
|
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*fifo_low = ovl_fifo_size - burst_size;
|
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*fifo_high = total_fifo_size - buf_unit;
|
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}
|
||||
}
|
||||
|
||||
static void dispc_ovl_set_fir(enum omap_plane plane,
|
||||
int hinc, int vinc,
|
||||
enum omap_color_component color_comp)
|
||||
|
||||
@ -279,16 +279,6 @@ void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
|
||||
}
|
||||
EXPORT_SYMBOL(omapdss_default_get_resolution);
|
||||
|
||||
void default_get_overlay_fifo_thresholds(enum omap_plane plane,
|
||||
u32 fifo_size, u32 burst_size,
|
||||
u32 *fifo_low, u32 *fifo_high)
|
||||
{
|
||||
unsigned buf_unit = dss_feat_get_buffer_size_unit();
|
||||
|
||||
*fifo_high = fifo_size - buf_unit;
|
||||
*fifo_low = fifo_size - burst_size;
|
||||
}
|
||||
|
||||
int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev)
|
||||
{
|
||||
switch (dssdev->type) {
|
||||
|
||||
@ -4524,14 +4524,6 @@ int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
|
||||
}
|
||||
EXPORT_SYMBOL(omapdss_dsi_enable_te);
|
||||
|
||||
void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
|
||||
u32 fifo_size, u32 burst_size,
|
||||
u32 *fifo_low, u32 *fifo_high)
|
||||
{
|
||||
*fifo_high = fifo_size - burst_size;
|
||||
*fifo_low = fifo_size - burst_size * 2;
|
||||
}
|
||||
|
||||
int dsi_init_display(struct omap_dss_device *dssdev)
|
||||
{
|
||||
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
|
||||
|
||||
@ -202,9 +202,6 @@ void dss_uninit_device(struct platform_device *pdev,
|
||||
struct omap_dss_device *dssdev);
|
||||
bool dss_use_replication(struct omap_dss_device *dssdev,
|
||||
enum omap_color_mode mode);
|
||||
void default_get_overlay_fifo_thresholds(enum omap_plane plane,
|
||||
u32 fifo_size, u32 burst_size,
|
||||
u32 *fifo_low, u32 *fifo_high);
|
||||
|
||||
/* manager */
|
||||
int dss_init_overlay_managers(struct platform_device *pdev);
|
||||
@ -313,9 +310,6 @@ int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
|
||||
int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
|
||||
bool enable_hsdiv);
|
||||
void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes);
|
||||
void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
|
||||
u32 fifo_size, u32 burst_size,
|
||||
u32 *fifo_low, u32 *fifo_high);
|
||||
void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev);
|
||||
void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev);
|
||||
struct platform_device *dsi_get_dsidev_from_id(int module);
|
||||
@ -429,8 +423,8 @@ int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
|
||||
|
||||
|
||||
void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
|
||||
u32 dispc_ovl_get_fifo_size(enum omap_plane plane);
|
||||
u32 dispc_ovl_get_burst_size(enum omap_plane plane);
|
||||
void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
|
||||
u32 *fifo_low, u32 *fifo_high, bool use_fifomerge);
|
||||
int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
|
||||
bool ilace, bool replication);
|
||||
int dispc_ovl_enable(enum omap_plane plane, bool enable);
|
||||
|
||||
@ -370,7 +370,8 @@ static const struct omap_dss_features omap3430_dss_features = {
|
||||
FEAT_LINEBUFFERSPLIT | FEAT_RESIZECONF |
|
||||
FEAT_DSI_PLL_FREQSEL | FEAT_DSI_REVERSE_TXCLKESC |
|
||||
FEAT_VENC_REQUIRES_TV_DAC_CLK | FEAT_CPR | FEAT_PRELOAD |
|
||||
FEAT_FIR_COEF_V | FEAT_ALPHA_FIXED_ZORDER,
|
||||
FEAT_FIR_COEF_V | FEAT_ALPHA_FIXED_ZORDER | FEAT_FIFO_MERGE |
|
||||
FEAT_OMAP3_DSI_FIFO_BUG,
|
||||
|
||||
.num_mgrs = 2,
|
||||
.num_ovls = 3,
|
||||
@ -394,7 +395,8 @@ static const struct omap_dss_features omap3630_dss_features = {
|
||||
FEAT_ROWREPEATENABLE | FEAT_LINEBUFFERSPLIT |
|
||||
FEAT_RESIZECONF | FEAT_DSI_PLL_PWR_BUG |
|
||||
FEAT_DSI_PLL_FREQSEL | FEAT_CPR | FEAT_PRELOAD |
|
||||
FEAT_FIR_COEF_V | FEAT_ALPHA_FIXED_ZORDER,
|
||||
FEAT_FIR_COEF_V | FEAT_ALPHA_FIXED_ZORDER | FEAT_FIFO_MERGE |
|
||||
FEAT_OMAP3_DSI_FIFO_BUG,
|
||||
|
||||
.num_mgrs = 2,
|
||||
.num_ovls = 3,
|
||||
@ -419,7 +421,7 @@ static const struct omap_dss_features omap4430_es1_0_dss_features = {
|
||||
FEAT_DSI_DCS_CMD_CONFIG_VC | FEAT_DSI_VC_OCP_WIDTH |
|
||||
FEAT_DSI_GNQ | FEAT_HANDLE_UV_SEPARATE | FEAT_ATTR2 |
|
||||
FEAT_CPR | FEAT_PRELOAD | FEAT_FIR_COEF_V |
|
||||
FEAT_ALPHA_FREE_ZORDER,
|
||||
FEAT_ALPHA_FREE_ZORDER | FEAT_FIFO_MERGE,
|
||||
|
||||
.num_mgrs = 3,
|
||||
.num_ovls = 4,
|
||||
@ -443,7 +445,8 @@ static const struct omap_dss_features omap4_dss_features = {
|
||||
FEAT_DSI_DCS_CMD_CONFIG_VC | FEAT_DSI_VC_OCP_WIDTH |
|
||||
FEAT_DSI_GNQ | FEAT_HDMI_CTS_SWMODE |
|
||||
FEAT_HANDLE_UV_SEPARATE | FEAT_ATTR2 | FEAT_CPR |
|
||||
FEAT_PRELOAD | FEAT_FIR_COEF_V | FEAT_ALPHA_FREE_ZORDER,
|
||||
FEAT_PRELOAD | FEAT_FIR_COEF_V | FEAT_ALPHA_FREE_ZORDER |
|
||||
FEAT_FIFO_MERGE,
|
||||
|
||||
.num_mgrs = 3,
|
||||
.num_ovls = 4,
|
||||
|
||||
@ -58,6 +58,9 @@ enum dss_feat_id {
|
||||
FEAT_FIR_COEF_V = 1 << 25,
|
||||
FEAT_ALPHA_FIXED_ZORDER = 1 << 26,
|
||||
FEAT_ALPHA_FREE_ZORDER = 1 << 27,
|
||||
FEAT_FIFO_MERGE = 1 << 28,
|
||||
/* An unknown HW bug causing the normal FIFO thresholds not to work */
|
||||
FEAT_OMAP3_DSI_FIFO_BUG = 1 << 29,
|
||||
};
|
||||
|
||||
/* DSS register field id */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user