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V4L/DVB: dm1105: use macro for read/write registers
This is for better readability and smaller size of code lines. Also it is for future improvements like GPIO handling. Signed-off-by: Igor M. Liplianin <liplianin@me.by> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Igor M. Liplianin
Mauro Carvalho Chehab
parent
34d2f9bf18
commit
5eb3291fe8
@ -311,6 +311,22 @@ struct dm1105_dev {
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#define dm_io_mem(reg) ((unsigned long)(&dev->io_mem[reg]))
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#define dm_readb(reg) inb(dm_io_mem(reg))
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#define dm_writeb(reg, value) outb((value), (dm_io_mem(reg)))
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#define dm_readw(reg) inw(dm_io_mem(reg))
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#define dm_writew(reg, value) outw((value), (dm_io_mem(reg)))
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#define dm_readl(reg) inl(dm_io_mem(reg))
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#define dm_writel(reg, value) outl((value), (dm_io_mem(reg)))
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#define dm_andorl(reg, mask, value) \
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outl((inl(dm_io_mem(reg)) & ~(mask)) |\
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((value) & (mask)), (dm_io_mem(reg)))
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#define dm_setl(reg, bit) dm_andorl((reg), (bit), (bit))
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#define dm_clearl(reg, bit) dm_andorl((reg), (bit), 0)
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static int dm1105_i2c_xfer(struct i2c_adapter *i2c_adap,
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struct i2c_msg *msgs, int num)
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{
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@ -321,19 +337,19 @@ static int dm1105_i2c_xfer(struct i2c_adapter *i2c_adap,
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dev = i2c_adap->algo_data;
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for (i = 0; i < num; i++) {
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outb(0x00, dm_io_mem(DM1105_I2CCTR));
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dm_writeb(DM1105_I2CCTR, 0x00);
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if (msgs[i].flags & I2C_M_RD) {
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/* read bytes */
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addr = msgs[i].addr << 1;
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addr |= 1;
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outb(addr, dm_io_mem(DM1105_I2CDAT));
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dm_writeb(DM1105_I2CDAT, addr);
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for (byte = 0; byte < msgs[i].len; byte++)
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outb(0, dm_io_mem(DM1105_I2CDAT + byte + 1));
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dm_writeb(DM1105_I2CDAT + byte + 1, 0);
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outb(0x81 + msgs[i].len, dm_io_mem(DM1105_I2CCTR));
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dm_writeb(DM1105_I2CCTR, 0x81 + msgs[i].len);
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for (j = 0; j < 55; j++) {
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mdelay(10);
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status = inb(dm_io_mem(DM1105_I2CSTS));
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status = dm_readb(DM1105_I2CSTS);
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if ((status & 0xc0) == 0x40)
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break;
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}
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@ -341,7 +357,7 @@ static int dm1105_i2c_xfer(struct i2c_adapter *i2c_adap,
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return -1;
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for (byte = 0; byte < msgs[i].len; byte++) {
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rc = inb(dm_io_mem(DM1105_I2CDAT + byte + 1));
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rc = dm_readb(DM1105_I2CDAT + byte + 1);
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if (rc < 0)
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goto err;
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msgs[i].buf[byte] = rc;
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@ -352,16 +368,16 @@ static int dm1105_i2c_xfer(struct i2c_adapter *i2c_adap,
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len = msgs[i].len - 1;
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k = 1;
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do {
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outb(msgs[i].addr << 1, dm_io_mem(DM1105_I2CDAT));
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outb(0xf7, dm_io_mem(DM1105_I2CDAT + 1));
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dm_writeb(DM1105_I2CDAT, msgs[i].addr << 1);
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dm_writeb(DM1105_I2CDAT + 1, 0xf7);
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for (byte = 0; byte < (len > 48 ? 48 : len); byte++) {
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data = msgs[i].buf[k + byte];
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outb(data, dm_io_mem(DM1105_I2CDAT + byte + 2));
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dm_writeb(DM1105_I2CDAT + byte + 2, data);
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}
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outb(0x82 + (len > 48 ? 48 : len), dm_io_mem(DM1105_I2CCTR));
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dm_writeb(DM1105_I2CCTR, 0x82 + (len > 48 ? 48 : len));
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for (j = 0; j < 25; j++) {
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mdelay(10);
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status = inb(dm_io_mem(DM1105_I2CSTS));
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status = dm_readb(DM1105_I2CSTS);
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if ((status & 0xc0) == 0x40)
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break;
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}
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@ -374,15 +390,15 @@ static int dm1105_i2c_xfer(struct i2c_adapter *i2c_adap,
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} while (len > 0);
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} else {
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/* write bytes */
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outb(msgs[i].addr<<1, dm_io_mem(DM1105_I2CDAT));
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dm_writeb(DM1105_I2CDAT, msgs[i].addr << 1);
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for (byte = 0; byte < msgs[i].len; byte++) {
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data = msgs[i].buf[byte];
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outb(data, dm_io_mem(DM1105_I2CDAT + byte + 1));
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dm_writeb(DM1105_I2CDAT + byte + 1, data);
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}
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outb(0x81 + msgs[i].len, dm_io_mem(DM1105_I2CCTR));
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dm_writeb(DM1105_I2CCTR, 0x81 + msgs[i].len);
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for (j = 0; j < 25; j++) {
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mdelay(10);
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status = inb(dm_io_mem(DM1105_I2CSTS));
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status = dm_readb(DM1105_I2CSTS);
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if ((status & 0xc0) == 0x40)
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break;
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}
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@ -437,20 +453,20 @@ static int dm1105_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
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lnb_18v = DM1105_LNB_18V;
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}
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outl(lnb_mask, dm_io_mem(DM1105_GPIOCTR));
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dm_writel(DM1105_GPIOCTR, lnb_mask);
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if (voltage == SEC_VOLTAGE_18)
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outl(lnb_18v , dm_io_mem(DM1105_GPIOVAL));
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dm_writel(DM1105_GPIOVAL, lnb_18v);
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else if (voltage == SEC_VOLTAGE_13)
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outl(lnb_13v, dm_io_mem(DM1105_GPIOVAL));
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dm_writel(DM1105_GPIOVAL, lnb_13v);
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else
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outl(lnb_off, dm_io_mem(DM1105_GPIOVAL));
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dm_writel(DM1105_GPIOVAL, lnb_off);
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return 0;
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}
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static void dm1105_set_dma_addr(struct dm1105_dev *dev)
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{
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outl(cpu_to_le32(dev->dma_addr), dm_io_mem(DM1105_STADR));
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dm_writel(DM1105_STADR, cpu_to_le32(dev->dma_addr));
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}
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static int __devinit dm1105_dma_map(struct dm1105_dev *dev)
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@ -472,14 +488,14 @@ static void dm1105_dma_unmap(struct dm1105_dev *dev)
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static void dm1105_enable_irqs(struct dm1105_dev *dev)
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{
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outb(INTMAK_ALLMASK, dm_io_mem(DM1105_INTMAK));
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outb(1, dm_io_mem(DM1105_CR));
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dm_writeb(DM1105_INTMAK, INTMAK_ALLMASK);
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dm_writeb(DM1105_CR, 1);
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}
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static void dm1105_disable_irqs(struct dm1105_dev *dev)
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{
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outb(INTMAK_IRM, dm_io_mem(DM1105_INTMAK));
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outb(0, dm_io_mem(DM1105_CR));
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dm_writeb(DM1105_INTMAK, INTMAK_IRM);
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dm_writeb(DM1105_CR, 0);
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}
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static int dm1105_start_feed(struct dvb_demux_feed *f)
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@ -533,7 +549,7 @@ static void dm1105_dmx_buffer(struct work_struct *work)
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/* bad packet found */
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if ((dev->PacketErrorCount >= 2) &&
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(dev->dmarst == 0)) {
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outb(1, dm_io_mem(DM1105_RST));
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dm_writeb(DM1105_RST, 1);
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dev->wrp = 0;
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dev->PacketErrorCount = 0;
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dev->dmarst = 0;
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@ -556,18 +572,17 @@ static irqreturn_t dm1105_irq(int irq, void *dev_id)
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struct dm1105_dev *dev = dev_id;
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/* Read-Write INSTS Ack's Interrupt for DM1105 chip 16.03.2008 */
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unsigned int intsts = inb(dm_io_mem(DM1105_INTSTS));
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outb(intsts, dm_io_mem(DM1105_INTSTS));
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unsigned int intsts = dm_readb(DM1105_INTSTS);
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dm_writeb(DM1105_INTSTS, intsts);
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switch (intsts) {
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case INTSTS_TSIRQ:
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case (INTSTS_TSIRQ | INTSTS_IR):
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dev->nextwrp = inl(dm_io_mem(DM1105_WRP)) -
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inl(dm_io_mem(DM1105_STADR));
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dev->nextwrp = dm_readl(DM1105_WRP) - dm_readl(DM1105_STADR);
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queue_work(dev->wq, &dev->work);
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break;
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case INTSTS_IR:
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dev->ir.ir_command = inl(dm_io_mem(DM1105_IRCODE));
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dev->ir.ir_command = dm_readl(DM1105_IRCODE);
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schedule_work(&dev->ir.work);
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break;
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}
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@ -626,24 +641,24 @@ static int __devinit dm1105_hw_init(struct dm1105_dev *dev)
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{
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dm1105_disable_irqs(dev);
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outb(0, dm_io_mem(DM1105_HOST_CTR));
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dm_writeb(DM1105_HOST_CTR, 0);
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/*DATALEN 188,*/
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outb(188, dm_io_mem(DM1105_DTALENTH));
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dm_writeb(DM1105_DTALENTH, 188);
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/*TS_STRT TS_VALP MSBFIRST TS_MODE ALPAS TSPES*/
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outw(0xc10a, dm_io_mem(DM1105_TSCTR));
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dm_writew(DM1105_TSCTR, 0xc10a);
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/* map DMA and set address */
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dm1105_dma_map(dev);
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dm1105_set_dma_addr(dev);
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/* big buffer */
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outl(5*DM1105_DMA_BYTES, dm_io_mem(DM1105_RLEN));
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outb(47, dm_io_mem(DM1105_INTCNT));
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dm_writel(DM1105_RLEN, 5 * DM1105_DMA_BYTES);
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dm_writeb(DM1105_INTCNT, 47);
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/* IR NEC mode enable */
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outb((DM1105_IR_EN | DM1105_SYS_CHK), dm_io_mem(DM1105_IRCTR));
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outb(0, dm_io_mem(DM1105_IRMODE));
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outw(0, dm_io_mem(DM1105_SYSTEMCODE));
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dm_writeb(DM1105_IRCTR, (DM1105_IR_EN | DM1105_SYS_CHK));
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dm_writeb(DM1105_IRMODE, 0);
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dm_writew(DM1105_SYSTEMCODE, 0);
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return 0;
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}
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@ -653,8 +668,8 @@ static void dm1105_hw_exit(struct dm1105_dev *dev)
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dm1105_disable_irqs(dev);
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/* IR disable */
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outb(0, dm_io_mem(DM1105_IRCTR));
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outb(INTMAK_NONEMASK, dm_io_mem(DM1105_INTMAK));
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dm_writeb(DM1105_IRCTR, 0);
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dm_writeb(DM1105_INTMAK, INTMAK_NONEMASK);
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dm1105_dma_unmap(dev);
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}
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