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remoteproc: qcom: q6v5-mss: Improve readability of reset_assert
Define AXI_GATING_VALID_OVERRIDE and fixup comments to improve readability of Q6 modem reset sequence on SC7180 SoCs. Reviewed-by: Evan Green <evgreen@chromium.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20200123131236.1078-3-sibis@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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@ -71,6 +71,7 @@
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#define NAV_AXI_HALTREQ_BIT BIT(0)
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#define NAV_AXI_HALTACK_BIT BIT(1)
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#define NAV_AXI_IDLE_BIT BIT(2)
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#define AXI_GATING_VALID_OVERRIDE BIT(0)
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#define HALT_ACK_TIMEOUT_US 100000
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#define NAV_HALT_ACK_TIMEOUT_US 200
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@ -415,16 +416,24 @@ static int q6v5_reset_assert(struct q6v5 *qproc)
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ret = reset_control_reset(qproc->mss_restart);
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reset_control_deassert(qproc->pdc_reset);
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} else if (qproc->has_halt_nav) {
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/* SWAR using CONN_BOX_SPARE_0 for pipeline glitch issue */
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/*
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* When the AXI pipeline is being reset with the Q6 modem partly
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* operational there is possibility of AXI valid signal to
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* glitch, leading to spurious transactions and Q6 hangs. A work
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* around is employed by asserting the AXI_GATING_VALID_OVERRIDE
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* BIT before triggering Q6 MSS reset. Both the HALTREQ and
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* AXI_GATING_VALID_OVERRIDE are withdrawn post MSS assert
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* followed by a MSS deassert, while holding the PDC reset.
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*/
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reset_control_assert(qproc->pdc_reset);
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regmap_update_bits(qproc->conn_map, qproc->conn_box,
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BIT(0), BIT(0));
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AXI_GATING_VALID_OVERRIDE, 1);
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regmap_update_bits(qproc->halt_nav_map, qproc->halt_nav,
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NAV_AXI_HALTREQ_BIT, 0);
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reset_control_assert(qproc->mss_restart);
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reset_control_deassert(qproc->pdc_reset);
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regmap_update_bits(qproc->conn_map, qproc->conn_box,
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BIT(0), 0);
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AXI_GATING_VALID_OVERRIDE, 0);
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ret = reset_control_deassert(qproc->mss_restart);
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} else {
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ret = reset_control_assert(qproc->mss_restart);
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