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MIPS: Alchemy: new userspace suspend interface for development boards.
Replace the current sysctl-based suspend interface with a new sysfs-
based one which also uses the Linux-2.6 suspend model.
To configure wakeup sources, a subtree for the demoboards is created
under /sys/power/db1x:
sys/
`-- power
`-- db1x
|-- gpio0
|-- gpio1
|-- gpio2
|-- gpio3
|-- gpio4
|-- gpio5
|-- gpio6
|-- gpio7
|-- timer
|-- timer_timeout
|-- wakemsk
`-- wakesrc
The nodes 'gpio[0-7]' and 'timer' configure the GPIO0..7 and M2
bits of the SYS_WAKEMSK (wakeup source enable) register. Writing '1'
enables a wakesource, 0 disables it.
The 'timer_timeout' node holds the timeout in seconds after which the
TOYMATCH2 event should wake the system.
The 'wakesrc' node holds the SYS_WAKESRC register after wakeup (in hex),
the 'wakemsk' node can be used to get/set the wakeup mask directly.
For example, to have the timer wake the system after 10 seconds of sleep,
the following must be done in userspace:
echo 10 > /sys/power/db1x/timer_timeout
echo 1 > /sys/power/db1x/timer
echo mem > /sys/power/sleep
This patch also removes the homebrew CPU frequency switching code. I don't
understand how it could have ever worked reliably; it does not communicate
the clock changes to peripheral devices other than uarts.
Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
create mode 100644 arch/mips/alchemy/devboards/pm.c
This commit is contained in:
Manuel Lauss
Ralf Baechle
parent
ac15dad061
commit
61f9c58da5
@ -37,8 +37,6 @@
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#include <asm/mach-pb1x00/pb1000.h>
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#endif
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static DEFINE_SPINLOCK(irq_lock);
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static int au1x_ic_settype(unsigned int irq, unsigned int flow_type);
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/* per-processor fixed function irqs */
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@ -611,45 +609,3 @@ void __init arch_init_irq(void)
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set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3);
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}
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unsigned long save_local_and_disable(int controller)
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{
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int i;
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unsigned long flags, mask;
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spin_lock_irqsave(&irq_lock, flags);
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if (controller) {
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mask = au_readl(IC1_MASKSET);
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for (i = 0; i < 32; i++)
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au1x_ic1_mask(i + AU1000_INTC1_INT_BASE);
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} else {
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mask = au_readl(IC0_MASKSET);
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for (i = 0; i < 32; i++)
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au1x_ic0_mask(i + AU1000_INTC0_INT_BASE);
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}
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spin_unlock_irqrestore(&irq_lock, flags);
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return mask;
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}
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void restore_local_and_enable(int controller, unsigned long mask)
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{
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int i;
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unsigned long flags, new_mask;
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spin_lock_irqsave(&irq_lock, flags);
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for (i = 0; i < 32; i++)
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if (mask & (1 << i)) {
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if (controller)
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au1x_ic1_unmask(i + AU1000_INTC1_INT_BASE);
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else
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au1x_ic0_unmask(i + AU1000_INTC0_INT_BASE);
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}
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if (controller)
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new_mask = au_readl(IC1_MASKSET);
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else
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new_mask = au_readl(IC0_MASKSET);
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spin_unlock_irqrestore(&irq_lock, flags);
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}
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@ -42,18 +42,6 @@
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#ifdef CONFIG_PM
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#define DEBUG 1
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#ifdef DEBUG
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#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__, ## args)
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#else
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#define DPRINTK(fmt, args...)
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#endif
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extern unsigned long save_local_and_disable(int controller);
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extern void restore_local_and_enable(int controller, unsigned long mask);
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static DEFINE_SPINLOCK(pm_lock);
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/*
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* We need to save/restore a bunch of core registers that are
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* either volatile or reset to some state across a processor sleep.
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@ -74,21 +62,6 @@ static unsigned int sleep_sys_clocks[5];
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static unsigned int sleep_sys_pinfunc;
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static unsigned int sleep_static_memctlr[4][3];
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/*
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* Define this to cause the value you write to /proc/sys/pm/sleep to
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* set the TOY timer for the amount of time you want to sleep.
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* This is done mainly for testing, but may be useful in other cases.
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* The value is number of 32KHz ticks to sleep.
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*/
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#define SLEEP_TEST_TIMEOUT 1
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#ifdef SLEEP_TEST_TIMEOUT
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static int sleep_ticks;
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static void wakeup_counter0_set(int ticks)
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{
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au_writel(au_readl(SYS_TOYREAD) + ticks, SYS_TOYMATCH2);
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au_sync();
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}
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#endif
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static void save_core_regs(void)
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{
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@ -234,13 +207,6 @@ static void restore_core_regs(void)
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#endif
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}
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unsigned long suspend_mode;
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void wakeup_from_suspend(void)
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{
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suspend_mode = 0;
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}
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void au_sleep(void)
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{
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save_core_regs();
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@ -248,279 +214,4 @@ void au_sleep(void)
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restore_core_regs();
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}
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static int pm_do_sleep(ctl_table *ctl, int write, struct file *file,
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void __user *buffer, size_t *len, loff_t *ppos)
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{
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unsigned long wakeup, flags;
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int ret;
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#ifdef SLEEP_TEST_TIMEOUT
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#define TMPBUFLEN2 16
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char buf[TMPBUFLEN2], *p;
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#endif
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spin_lock_irqsave(&pm_lock, flags);
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if (!write) {
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*len = 0;
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ret = 0;
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goto out_unlock;
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};
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#ifdef SLEEP_TEST_TIMEOUT
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if (*len > TMPBUFLEN2 - 1) {
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ret = -EFAULT;
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goto out_unlock;
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}
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if (copy_from_user(buf, buffer, *len)) {
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return -EFAULT;
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goto out_unlock;
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}
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buf[*len] = 0;
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p = buf;
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sleep_ticks = simple_strtoul(p, &p, 0);
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wakeup_counter0_set(sleep_ticks);
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#endif
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/**
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** The code below is all system dependent and we should probably
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** have a function call out of here to set this up. You need
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** to configure the GPIO or timer interrupts that will bring
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** you out of sleep.
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** For testing, the TOY counter wakeup is useful.
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**/
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#if 0
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au_writel(au_readl(SYS_PINSTATERD) & ~(1 << 11), SYS_PINSTATERD);
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/* GPIO 6 can cause a wake up event */
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wakeup = au_readl(SYS_WAKEMSK);
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wakeup &= ~(1 << 8); /* turn off match20 wakeup */
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wakeup |= 1 << 6; /* turn on GPIO 6 wakeup */
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#else
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/* For testing, allow match20 to wake us up. */
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wakeup = 1 << 8; /* turn on match20 wakeup */
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wakeup = 0;
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#endif
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au_writel(1, SYS_WAKESRC); /* clear cause */
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au_sync();
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au_writel(wakeup, SYS_WAKEMSK);
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au_sync();
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au_sleep();
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ret = 0;
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out_unlock:
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spin_unlock_irqrestore(&pm_lock, flags);
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return ret;
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}
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#if !defined(CONFIG_SOC_AU1200) && !defined(CONFIG_SOC_AU1550)
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/*
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* This is right out of init/main.c
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*/
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/*
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* This is the number of bits of precision for the loops_per_jiffy.
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* Each bit takes on average 1.5/HZ seconds. This (like the original)
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* is a little better than 1%.
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*/
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#define LPS_PREC 8
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static void au1000_calibrate_delay(void)
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{
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unsigned long ticks, loopbit;
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int lps_precision = LPS_PREC;
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loops_per_jiffy = 1 << 12;
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while (loops_per_jiffy <<= 1) {
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/* Wait for "start of" clock tick */
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ticks = jiffies;
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while (ticks == jiffies)
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/* nothing */ ;
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/* Go ... */
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ticks = jiffies;
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__delay(loops_per_jiffy);
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ticks = jiffies - ticks;
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if (ticks)
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break;
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}
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/*
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* Do a binary approximation to get loops_per_jiffy set to be equal
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* one clock (up to lps_precision bits)
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*/
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loops_per_jiffy >>= 1;
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loopbit = loops_per_jiffy;
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while (lps_precision-- && (loopbit >>= 1)) {
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loops_per_jiffy |= loopbit;
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ticks = jiffies;
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while (ticks == jiffies);
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ticks = jiffies;
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__delay(loops_per_jiffy);
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if (jiffies != ticks) /* longer than 1 tick */
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loops_per_jiffy &= ~loopbit;
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}
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}
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static int pm_do_freq(ctl_table *ctl, int write, struct file *file,
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void __user *buffer, size_t *len, loff_t *ppos)
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{
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int retval = 0, i;
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unsigned long val, pll;
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#define TMPBUFLEN 64
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#define MAX_CPU_FREQ 396
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char buf[TMPBUFLEN], *p;
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unsigned long flags, intc0_mask, intc1_mask;
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unsigned long old_baud_base, old_cpu_freq, old_clk, old_refresh;
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unsigned long new_baud_base, new_cpu_freq, new_clk, new_refresh;
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unsigned long baud_rate;
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spin_lock_irqsave(&pm_lock, flags);
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if (!write)
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*len = 0;
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else {
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/* Parse the new frequency */
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if (*len > TMPBUFLEN - 1) {
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spin_unlock_irqrestore(&pm_lock, flags);
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return -EFAULT;
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}
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if (copy_from_user(buf, buffer, *len)) {
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spin_unlock_irqrestore(&pm_lock, flags);
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return -EFAULT;
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}
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buf[*len] = 0;
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p = buf;
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val = simple_strtoul(p, &p, 0);
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if (val > MAX_CPU_FREQ) {
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spin_unlock_irqrestore(&pm_lock, flags);
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return -EFAULT;
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}
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pll = val / 12;
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if ((pll > 33) || (pll < 7)) { /* 396 MHz max, 84 MHz min */
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/* Revisit this for higher speed CPUs */
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spin_unlock_irqrestore(&pm_lock, flags);
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return -EFAULT;
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}
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old_baud_base = get_au1x00_uart_baud_base();
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old_cpu_freq = get_au1x00_speed();
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new_cpu_freq = pll * 12 * 1000000;
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new_baud_base = (new_cpu_freq / (2 * ((int)(au_readl(SYS_POWERCTRL)
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& 0x03) + 2) * 16));
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set_au1x00_speed(new_cpu_freq);
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set_au1x00_uart_baud_base(new_baud_base);
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old_refresh = au_readl(MEM_SDREFCFG) & 0x1ffffff;
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new_refresh = ((old_refresh * new_cpu_freq) / old_cpu_freq) |
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(au_readl(MEM_SDREFCFG) & ~0x1ffffff);
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au_writel(pll, SYS_CPUPLL);
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au_sync_delay(1);
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au_writel(new_refresh, MEM_SDREFCFG);
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au_sync_delay(1);
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for (i = 0; i < 4; i++)
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if (au_readl(UART_BASE + UART_MOD_CNTRL +
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i * 0x00100000) == 3) {
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old_clk = au_readl(UART_BASE + UART_CLK +
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i * 0x00100000);
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baud_rate = old_baud_base / old_clk;
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/*
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* We won't get an exact baud rate and the error
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* could be significant enough that our new
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* calculation will result in a clock that will
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* give us a baud rate that's too far off from
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* what we really want.
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*/
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if (baud_rate > 100000)
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baud_rate = 115200;
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else if (baud_rate > 50000)
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baud_rate = 57600;
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else if (baud_rate > 30000)
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baud_rate = 38400;
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else if (baud_rate > 17000)
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baud_rate = 19200;
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else
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baud_rate = 9600;
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new_clk = new_baud_base / baud_rate;
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au_writel(new_clk, UART_BASE + UART_CLK +
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i * 0x00100000);
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au_sync_delay(10);
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}
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}
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/*
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* We don't want _any_ interrupts other than match20. Otherwise our
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* au1000_calibrate_delay() calculation will be off, potentially a lot.
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*/
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intc0_mask = save_local_and_disable(0);
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intc1_mask = save_local_and_disable(1);
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val = 1 << (AU1000_TOY_MATCH2_INT - AU1000_INTC0_INT_BASE);
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au_writel(val, IC0_MASKSET); /* unmask */
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au_writel(val, IC0_WAKESET); /* enable wake-from-sleep */
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au_sync();
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spin_unlock_irqrestore(&pm_lock, flags);
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au1000_calibrate_delay();
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restore_local_and_enable(0, intc0_mask);
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restore_local_and_enable(1, intc1_mask);
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return retval;
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}
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#endif
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static struct ctl_table pm_table[] = {
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{
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.ctl_name = CTL_UNNUMBERED,
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.procname = "sleep",
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.data = NULL,
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.maxlen = 0,
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.mode = 0600,
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.proc_handler = &pm_do_sleep
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},
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#if !defined(CONFIG_SOC_AU1200) && !defined(CONFIG_SOC_AU1550)
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{
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.ctl_name = CTL_UNNUMBERED,
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.procname = "freq",
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.data = NULL,
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.maxlen = 0,
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.mode = 0600,
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.proc_handler = &pm_do_freq
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},
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#endif
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{}
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};
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static struct ctl_table pm_dir_table[] = {
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{
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.ctl_name = CTL_UNNUMBERED,
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.procname = "pm",
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.mode = 0555,
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.child = pm_table
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},
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{}
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};
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/*
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* Initialize power interface
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*/
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static int __init pm_init(void)
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{
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/* init TOY to tick at 1Hz. No need to wait for access bits
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* since there's plenty of time between here and the first
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* suspend cycle.
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*/
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if (au_readl(SYS_TOYTRIM) != 32767) {
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au_writel(32767, SYS_TOYTRIM);
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au_sync();
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}
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register_sysctl_table(pm_dir_table);
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return 0;
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}
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__initcall(pm_init);
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#endif /* CONFIG_PM */
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@ -3,6 +3,7 @@
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#
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obj-y += prom.o
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obj-$(CONFIG_PM) += pm.o
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obj-$(CONFIG_MIPS_PB1000) += pb1000/
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obj-$(CONFIG_MIPS_PB1100) += pb1100/
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obj-$(CONFIG_MIPS_PB1200) += pb1200/
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229
arch/mips/alchemy/devboards/pm.c
Normal file
229
arch/mips/alchemy/devboards/pm.c
Normal file
@ -0,0 +1,229 @@
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/*
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* Alchemy Development Board example suspend userspace interface.
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*
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* (c) 2008 Manuel Lauss <mano@roarinelk.homelinux.net>
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*/
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#include <linux/init.h>
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#include <linux/kobject.h>
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#include <linux/suspend.h>
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#include <linux/sysfs.h>
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#include <asm/mach-au1x00/au1000.h>
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/*
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* Generic suspend userspace interface for Alchemy development boards.
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* This code exports a few sysfs nodes under /sys/power/db1x/ which
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* can be used by userspace to en/disable all au1x-provided wakeup
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* sources and configure the timeout after which the the TOYMATCH2 irq
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* is to trigger a wakeup.
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*/
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static unsigned long db1x_pm_sleep_secs;
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static unsigned long db1x_pm_wakemsk;
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static unsigned long db1x_pm_last_wakesrc;
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static int db1x_pm_enter(suspend_state_t state)
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{
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/* enable GPIO based wakeup */
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au_writel(1, SYS_PININPUTEN);
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/* clear and setup wake cause and source */
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au_writel(0, SYS_WAKEMSK);
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au_sync();
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au_writel(0, SYS_WAKESRC);
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au_sync();
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au_writel(db1x_pm_wakemsk, SYS_WAKEMSK);
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au_sync();
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/* setup 1Hz-timer-based wakeup: wait for reg access */
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while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20)
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asm volatile ("nop");
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au_writel(au_readl(SYS_TOYREAD) + db1x_pm_sleep_secs, SYS_TOYMATCH2);
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au_sync();
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/* wait for value to really hit the register */
|
||||
while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20)
|
||||
asm volatile ("nop");
|
||||
|
||||
/* ...and now the sandman can come! */
|
||||
au_sleep();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int db1x_pm_begin(suspend_state_t state)
|
||||
{
|
||||
if (!db1x_pm_wakemsk) {
|
||||
printk(KERN_ERR "db1x: no wakeup source activated!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void db1x_pm_end(void)
|
||||
{
|
||||
/* read and store wakeup source, the clear the register. To
|
||||
* be able to clear it, WAKEMSK must be cleared first.
|
||||
*/
|
||||
db1x_pm_last_wakesrc = au_readl(SYS_WAKESRC);
|
||||
|
||||
au_writel(0, SYS_WAKEMSK);
|
||||
au_writel(0, SYS_WAKESRC);
|
||||
au_sync();
|
||||
|
||||
}
|
||||
|
||||
static struct platform_suspend_ops db1x_pm_ops = {
|
||||
.valid = suspend_valid_only_mem,
|
||||
.begin = db1x_pm_begin,
|
||||
.enter = db1x_pm_enter,
|
||||
.end = db1x_pm_end,
|
||||
};
|
||||
|
||||
#define ATTRCMP(x) (0 == strcmp(attr->attr.name, #x))
|
||||
|
||||
static ssize_t db1x_pmattr_show(struct kobject *kobj,
|
||||
struct kobj_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
int idx;
|
||||
|
||||
if (ATTRCMP(timer_timeout))
|
||||
return sprintf(buf, "%lu\n", db1x_pm_sleep_secs);
|
||||
|
||||
else if (ATTRCMP(timer))
|
||||
return sprintf(buf, "%u\n",
|
||||
!!(db1x_pm_wakemsk & SYS_WAKEMSK_M2));
|
||||
|
||||
else if (ATTRCMP(wakesrc))
|
||||
return sprintf(buf, "%lu\n", db1x_pm_last_wakesrc);
|
||||
|
||||
else if (ATTRCMP(gpio0) || ATTRCMP(gpio1) || ATTRCMP(gpio2) ||
|
||||
ATTRCMP(gpio3) || ATTRCMP(gpio4) || ATTRCMP(gpio5) ||
|
||||
ATTRCMP(gpio6) || ATTRCMP(gpio7)) {
|
||||
idx = (attr->attr.name)[4] - '0';
|
||||
return sprintf(buf, "%d\n",
|
||||
!!(db1x_pm_wakemsk & SYS_WAKEMSK_GPIO(idx)));
|
||||
|
||||
} else if (ATTRCMP(wakemsk)) {
|
||||
return sprintf(buf, "%08lx\n", db1x_pm_wakemsk);
|
||||
}
|
||||
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
static ssize_t db1x_pmattr_store(struct kobject *kobj,
|
||||
struct kobj_attribute *attr,
|
||||
const char *instr,
|
||||
size_t bytes)
|
||||
{
|
||||
unsigned long l;
|
||||
int tmp;
|
||||
|
||||
if (ATTRCMP(timer_timeout)) {
|
||||
tmp = strict_strtoul(instr, 0, &l);
|
||||
if (tmp)
|
||||
return tmp;
|
||||
|
||||
db1x_pm_sleep_secs = l;
|
||||
|
||||
} else if (ATTRCMP(timer)) {
|
||||
if (instr[0] != '0')
|
||||
db1x_pm_wakemsk |= SYS_WAKEMSK_M2;
|
||||
else
|
||||
db1x_pm_wakemsk &= ~SYS_WAKEMSK_M2;
|
||||
|
||||
} else if (ATTRCMP(gpio0) || ATTRCMP(gpio1) || ATTRCMP(gpio2) ||
|
||||
ATTRCMP(gpio3) || ATTRCMP(gpio4) || ATTRCMP(gpio5) ||
|
||||
ATTRCMP(gpio6) || ATTRCMP(gpio7)) {
|
||||
tmp = (attr->attr.name)[4] - '0';
|
||||
if (instr[0] != '0') {
|
||||
db1x_pm_wakemsk |= SYS_WAKEMSK_GPIO(tmp);
|
||||
} else {
|
||||
db1x_pm_wakemsk &= ~SYS_WAKEMSK_GPIO(tmp);
|
||||
}
|
||||
|
||||
} else if (ATTRCMP(wakemsk)) {
|
||||
tmp = strict_strtoul(instr, 0, &l);
|
||||
if (tmp)
|
||||
return tmp;
|
||||
|
||||
db1x_pm_wakemsk = l & 0x0000003f;
|
||||
|
||||
} else
|
||||
bytes = -ENOENT;
|
||||
|
||||
return bytes;
|
||||
}
|
||||
|
||||
#define ATTR(x) \
|
||||
static struct kobj_attribute x##_attribute = \
|
||||
__ATTR(x, 0664, db1x_pmattr_show, \
|
||||
db1x_pmattr_store);
|
||||
|
||||
ATTR(gpio0) /* GPIO-based wakeup enable */
|
||||
ATTR(gpio1)
|
||||
ATTR(gpio2)
|
||||
ATTR(gpio3)
|
||||
ATTR(gpio4)
|
||||
ATTR(gpio5)
|
||||
ATTR(gpio6)
|
||||
ATTR(gpio7)
|
||||
ATTR(timer) /* TOYMATCH2-based wakeup enable */
|
||||
ATTR(timer_timeout) /* timer-based wakeup timeout value, in seconds */
|
||||
ATTR(wakesrc) /* contents of SYS_WAKESRC after last wakeup */
|
||||
ATTR(wakemsk) /* direct access to SYS_WAKEMSK */
|
||||
|
||||
#define ATTR_LIST(x) & x ## _attribute.attr
|
||||
static struct attribute *db1x_pmattrs[] = {
|
||||
ATTR_LIST(gpio0),
|
||||
ATTR_LIST(gpio1),
|
||||
ATTR_LIST(gpio2),
|
||||
ATTR_LIST(gpio3),
|
||||
ATTR_LIST(gpio4),
|
||||
ATTR_LIST(gpio5),
|
||||
ATTR_LIST(gpio6),
|
||||
ATTR_LIST(gpio7),
|
||||
ATTR_LIST(timer),
|
||||
ATTR_LIST(timer_timeout),
|
||||
ATTR_LIST(wakesrc),
|
||||
ATTR_LIST(wakemsk),
|
||||
NULL, /* terminator */
|
||||
};
|
||||
|
||||
static struct attribute_group db1x_pmattr_group = {
|
||||
.name = "db1x",
|
||||
.attrs = db1x_pmattrs,
|
||||
};
|
||||
|
||||
/*
|
||||
* Initialize suspend interface
|
||||
*/
|
||||
static int __init pm_init(void)
|
||||
{
|
||||
/* init TOY to tick at 1Hz if not already done. No need to wait
|
||||
* for confirmation since there's plenty of time from here to
|
||||
* the next suspend cycle.
|
||||
*/
|
||||
if (au_readl(SYS_TOYTRIM) != 32767) {
|
||||
au_writel(32767, SYS_TOYTRIM);
|
||||
au_sync();
|
||||
}
|
||||
|
||||
db1x_pm_last_wakesrc = au_readl(SYS_WAKESRC);
|
||||
|
||||
au_writel(0, SYS_WAKESRC);
|
||||
au_sync();
|
||||
au_writel(0, SYS_WAKEMSK);
|
||||
au_sync();
|
||||
|
||||
suspend_set_ops(&db1x_pm_ops);
|
||||
|
||||
return sysfs_create_group(power_kobj, &db1x_pmattr_group);
|
||||
}
|
||||
|
||||
late_initcall(pm_init);
|
||||
@ -1560,6 +1560,10 @@ enum soc_au1200_ints {
|
||||
#define SYS_SLPPWR 0xB1900078
|
||||
#define SYS_SLEEP 0xB190007C
|
||||
|
||||
#define SYS_WAKEMSK_D2 (1 << 9)
|
||||
#define SYS_WAKEMSK_M2 (1 << 8)
|
||||
#define SYS_WAKEMSK_GPIO(x) (1 << (x))
|
||||
|
||||
/* Clock Controller */
|
||||
#define SYS_FREQCTRL0 0xB1900020
|
||||
# define SYS_FC_FRDIV2_BIT 22
|
||||
|
||||
Loading…
Reference in New Issue
Block a user