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ARM: tegra: migrate to new clock code

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Migrate Tegra clock support to drivers/clk/tegra, this involves
moving:
1. definition of tegra_cpu_car_ops to clk.c
2. definition of reset functions to clk-peripheral.c
3. change parent of cpu clock.
4. Remove legacy clock initialization.
5. Initialize clocks using DT.
6. Remove all instance of mach/clk.h

Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: use to_clk_periph_gate().]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
Prashant Gaikwad 2013-01-11 13:16:26 +05:30 committed by Stephen Warren
parent b08e8c0ecc
commit 61fd290d21
21 changed files with 73 additions and 142 deletions
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30
arch/arm/mach-tegra/board-dt-tegra20.c
View File

@ -42,7 +42,6 @@
#include <asm/setup.h>
#include "board.h"
#include "clock.h"
#include "common.h"
#include "iomap.h"
@ -104,37 +103,8 @@ static struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
{}
};
static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
/* name parent rate enabled */
{ "uarta", "pll_p", 216000000, true },
{ "uartd", "pll_p", 216000000, true },
{ "usbd", "clk_m", 12000000, false },
{ "usb2", "clk_m", 12000000, false },
{ "usb3", "clk_m", 12000000, false },
{ "pll_a", "pll_p_out1", 56448000, true },
{ "pll_a_out0", "pll_a", 11289600, true },
{ "cdev1", NULL, 0, true },
{ "blink", "clk_32k", 32768, true },
{ "i2s1", "pll_a_out0", 11289600, false},
{ "i2s2", "pll_a_out0", 11289600, false},
{ "sdmmc1", "pll_p", 48000000, false},
{ "sdmmc3", "pll_p", 48000000, false},
{ "sdmmc4", "pll_p", 48000000, false},
{ "spi", "pll_p", 20000000, false },
{ "sbc1", "pll_p", 100000000, false },
{ "sbc2", "pll_p", 100000000, false },
{ "sbc3", "pll_p", 100000000, false },
{ "sbc4", "pll_p", 100000000, false },
{ "host1x", "pll_c", 150000000, false },
{ "disp1", "pll_p", 600000000, false },
{ "disp2", "pll_p", 600000000, false },
{ NULL, NULL, 0, 0},
};
static void __init tegra_dt_init(void)
{
tegra_clk_init_from_table(tegra_dt_clk_init_table);
/*
* Finished with the static registrations now; fill in the missing
* devices

31
arch/arm/mach-tegra/board-dt-tegra30.c
View File

@ -35,7 +35,6 @@
#include <asm/hardware/gic.h>
#include "board.h"
#include "clock.h"
#include "common.h"
#include "iomap.h"
@ -67,38 +66,8 @@ static struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
{}
};
static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
/* name parent rate enabled */
{ "uarta", "pll_p", 408000000, true },
{ "pll_a", "pll_p_out1", 564480000, true },
{ "pll_a_out0", "pll_a", 11289600, true },
{ "extern1", "pll_a_out0", 0, true },
{ "clk_out_1", "extern1", 0, true },
{ "blink", "clk_32k", 32768, true },
{ "i2s0", "pll_a_out0", 11289600, false},
{ "i2s1", "pll_a_out0", 11289600, false},
{ "i2s2", "pll_a_out0", 11289600, false},
{ "i2s3", "pll_a_out0", 11289600, false},
{ "i2s4", "pll_a_out0", 11289600, false},
{ "sdmmc1", "pll_p", 48000000, false},
{ "sdmmc3", "pll_p", 48000000, false},
{ "sdmmc4", "pll_p", 48000000, false},
{ "sbc1", "pll_p", 100000000, false},
{ "sbc2", "pll_p", 100000000, false},
{ "sbc3", "pll_p", 100000000, false},
{ "sbc4", "pll_p", 100000000, false},
{ "sbc5", "pll_p", 100000000, false},
{ "sbc6", "pll_p", 100000000, false},
{ "host1x", "pll_c", 150000000, false},
{ "disp1", "pll_p", 600000000, false},
{ "disp2", "pll_p", 600000000, false},
{ NULL, NULL, 0, 0},
};
static void __init tegra30_dt_init(void)
{
tegra_clk_init_from_table(tegra_dt_clk_init_table);
of_platform_populate(NULL, of_default_bus_match_table,
tegra30_auxdata_lookup, NULL);
}

19
arch/arm/mach-tegra/clock.c
View File

@ -31,9 +31,6 @@
#include "board.h"
#include "clock.h"
/* Global data of Tegra CPU CAR ops */
struct tegra_cpu_car_ops *tegra_cpu_car_ops;
/*
* Locking:
*
@ -131,22 +128,6 @@ void tegra_clk_init_from_table(struct tegra_clk_init_table *table)
tegra_clk_init_one_from_table(table);
}
void tegra_periph_reset_deassert(struct clk *c)
{
struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
BUG_ON(!clk->reset);
clk->reset(__clk_get_hw(c), false);
}
EXPORT_SYMBOL(tegra_periph_reset_deassert);
void tegra_periph_reset_assert(struct clk *c)
{
struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
BUG_ON(!clk->reset);
clk->reset(__clk_get_hw(c), true);
}
EXPORT_SYMBOL(tegra_periph_reset_assert);
/* Several extended clock configuration bits (e.g., clock routing, clock
* phase control) are included in PLL and peripheral clock source
* registers. */

44
arch/arm/mach-tegra/common.c
View File

@ -22,6 +22,7 @@
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/of_irq.h>
#include <linux/clk/tegra.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
@ -29,7 +30,6 @@
#include <mach/powergate.h>
#include "board.h"
#include "clock.h"
#include "common.h"
#include "fuse.h"
#include "iomap.h"
@ -65,6 +65,7 @@ static const struct of_device_id tegra_dt_irq_match[] __initconst = {
void __init tegra_dt_init_irq(void)
{
tegra_clocks_init();
tegra_init_irq();
of_irq_init(tegra_dt_irq_match);
}
@ -80,43 +81,6 @@ void tegra_assert_system_reset(char mode, const char *cmd)
writel_relaxed(reg, reset);
}
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
/* name parent rate enabled */
{ "clk_m", NULL, 0, true },
{ "pll_p", "clk_m", 216000000, true },
{ "pll_p_out1", "pll_p", 28800000, true },
{ "pll_p_out2", "pll_p", 48000000, true },
{ "pll_p_out3", "pll_p", 72000000, true },
{ "pll_p_out4", "pll_p", 24000000, true },
{ "pll_c", "clk_m", 600000000, true },
{ "pll_c_out1", "pll_c", 120000000, true },
{ "sclk", "pll_c_out1", 120000000, true },
{ "hclk", "sclk", 120000000, true },
{ "pclk", "hclk", 60000000, true },
{ "csite", NULL, 0, true },
{ "emc", NULL, 0, true },
{ "cpu", NULL, 0, true },
{ NULL, NULL, 0, 0},
};
#endif
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
/* name parent rate enabled */
{ "clk_m", NULL, 0, true },
{ "pll_p", "pll_ref", 408000000, true },
{ "pll_p_out1", "pll_p", 9600000, true },
{ "pll_p_out4", "pll_p", 102000000, true },
{ "sclk", "pll_p_out4", 102000000, true },
{ "hclk", "sclk", 102000000, true },
{ "pclk", "hclk", 51000000, true },
{ "csite", NULL, 0, true },
{ NULL, NULL, 0, 0},
};
#endif
static void __init tegra_init_cache(void)
{
#ifdef CONFIG_CACHE_L2X0
@ -141,8 +105,6 @@ void __init tegra20_init_early(void)
tegra_cpu_reset_handler_init();
tegra_apb_io_init();
tegra_init_fuse();
tegra2_init_clocks();
tegra_clk_init_from_table(tegra20_clk_init_table);
tegra_init_cache();
tegra_pmc_init();
tegra_powergate_init();
@ -155,8 +117,6 @@ void __init tegra30_init_early(void)
tegra_cpu_reset_handler_init();
tegra_apb_io_init();
tegra_init_fuse();
tegra30_init_clocks();
tegra_clk_init_from_table(tegra30_clk_init_table);
tegra_init_cache();
tegra_pmc_init();
tegra_powergate_init();

2
arch/arm/mach-tegra/cpu-tegra.c
View File

@ -266,7 +266,7 @@ static int __init tegra_cpufreq_init(void)
if (IS_ERR(pll_x_clk))
return PTR_ERR(pll_x_clk);
pll_p_clk = clk_get_sys(NULL, "pll_p");
pll_p_clk = clk_get_sys(NULL, "pll_p_cclk");
if (IS_ERR(pll_p_clk))
return PTR_ERR(pll_p_clk);

3
arch/arm/mach-tegra/include/mach/clk.h
View File

@ -31,9 +31,6 @@ enum tegra_clk_ex_param {
TEGRA_CLK_PLLD_MIPI_MUX_SEL,
};
void tegra_periph_reset_deassert(struct clk *c);
void tegra_periph_reset_assert(struct clk *c);
#ifndef CONFIG_COMMON_CLK
unsigned long clk_get_rate_all_locked(struct clk *c);
#endif

2
arch/arm/mach-tegra/pcie.c
View File

@ -33,11 +33,11 @@
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/export.h>
#include <linux/clk/tegra.h>
#include <asm/sizes.h>
#include <asm/mach/pci.h>
#include <mach/clk.h>
#include <mach/powergate.h>
#include "board.h"

2
arch/arm/mach-tegra/powergate.c
View File

@ -26,8 +26,8 @@
#include <linux/io.h>
#include <linux/seq_file.h>
#include <linux/spinlock.h>
#include <linux/clk/tegra.h>
#include <mach/clk.h>
#include <mach/powergate.h>
#include "fuse.h"

38
drivers/clk/tegra/clk-periph.c
View File

@ -110,6 +110,44 @@ static void clk_periph_disable(struct clk_hw *hw)
gate_ops->disable(gate_hw);
}
void tegra_periph_reset_deassert(struct clk *c)
{
struct clk_hw *hw = __clk_get_hw(c);
struct tegra_clk_periph *periph = to_clk_periph(hw);
struct tegra_clk_periph_gate *gate;
if (periph->magic != TEGRA_CLK_PERIPH_MAGIC) {
gate = to_clk_periph_gate(hw);
if (gate->magic != TEGRA_CLK_PERIPH_GATE_MAGIC) {
WARN_ON(1);
return;
}
} else {
gate = &periph->gate;
}
tegra_periph_reset(gate, 0);
}
void tegra_periph_reset_assert(struct clk *c)
{
struct clk_hw *hw = __clk_get_hw(c);
struct tegra_clk_periph *periph = to_clk_periph(hw);
struct tegra_clk_periph_gate *gate;
if (periph->magic != TEGRA_CLK_PERIPH_MAGIC) {
gate = to_clk_periph_gate(hw);
if (gate->magic != TEGRA_CLK_PERIPH_GATE_MAGIC) {
WARN_ON(1);
return;
}
} else {
gate = &periph->gate;
}
tegra_periph_reset(gate, 1);
}
const struct clk_ops tegra_clk_periph_ops = {
.get_parent = clk_periph_get_parent,
.set_parent = clk_periph_set_parent,

16
drivers/clk/tegra/clk.c
View File

@ -16,9 +16,14 @@
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/clk/tegra.h>
#include "clk.h"
/* Global data of Tegra CPU CAR ops */
struct tegra_cpu_car_ops *tegra_cpu_car_ops;
void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
struct clk *clks[], int clk_max)
{
@ -67,3 +72,14 @@ void __init tegra_init_from_table(struct tegra_clk_init_table *tbl,
}
}
}
static const struct of_device_id tegra_dt_clk_match[] = {
{ .compatible = "nvidia,tegra20-car", .data = tegra20_clock_init },
{ .compatible = "nvidia,tegra30-car", .data = tegra30_clock_init },
{ }
};
void __init tegra_clocks_init(void)
{
of_clk_init(tegra_dt_clk_match);
}

2
drivers/dma/tegra20-apb-dma.c
View File

@ -31,8 +31,8 @@
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/clk/tegra.h>
#include <mach/clk.h>
#include "dmaengine.h"
#define TEGRA_APBDMA_GENERAL 0x0

3
drivers/gpu/drm/tegra/dc.c
View File

@ -12,8 +12,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <mach/clk.h>
#include <linux/clk/tegra.h>
#include "drm.h"
#include "dc.h"

1
drivers/gpu/drm/tegra/drm.c
View File

@ -11,7 +11,6 @@
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <mach/clk.h>
#include <linux/dma-mapping.h>
#include <asm/dma-iommu.h>

3
drivers/gpu/drm/tegra/hdmi.c
View File

@ -14,8 +14,7 @@
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <mach/clk.h>
#include <linux/clk/tegra.h>
#include "hdmi.h"
#include "drm.h"

3
drivers/i2c/busses/i2c-tegra.c
View File

@ -29,11 +29,10 @@
#include <linux/of_i2c.h>
#include <linux/of_device.h>
#include <linux/module.h>
#include <linux/clk/tegra.h>
#include <asm/unaligned.h>
#include <mach/clk.h>
#define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
#define BYTES_PER_FIFO_WORD 4

2
drivers/input/keyboard/tegra-kbc.c
View File

@ -30,7 +30,7 @@
#include <linux/clk.h>
#include <linux/slab.h>
#include <linux/input/tegra_kbc.h>
#include <mach/clk.h>
#include <linux/clk/tegra.h>
#define KBC_MAX_DEBOUNCE_CNT 0x3ffu

2
drivers/spi/spi-tegra20-sflash.c
View File

@ -34,7 +34,7 @@
#include <linux/of_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi-tegra.h>
#include <mach/clk.h>
#include <linux/clk/tegra.h>
#define SPI_COMMAND 0x000
#define SPI_GO BIT(30)

2
drivers/spi/spi-tegra20-slink.c
View File

@ -35,7 +35,7 @@
#include <linux/of_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi-tegra.h>
#include <mach/clk.h>
#include <linux/clk/tegra.h>
#define SLINK_COMMAND 0x000
#define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0)

3
drivers/staging/nvec/nvec.c
View File

@ -37,8 +37,7 @@
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <mach/clk.h>
#include <linux/clk/tegra.h>
#include "nvec.h"

5
include/linux/clk/tegra.h
View File

@ -17,6 +17,8 @@
#ifndef __LINUX_CLK_TEGRA_H_
#define __LINUX_CLK_TEGRA_H_
#include <linux/clk.h>
/*
* Tegra CPU clock and reset control ops
*
@ -120,5 +122,8 @@ static inline void tegra_cpu_clock_resume(void)
void tegra20_cpu_car_ops_init(void);
void tegra30_cpu_car_ops_init(void);
void tegra_periph_reset_deassert(struct clk *c);
void tegra_periph_reset_assert(struct clk *c);
void tegra_clocks_init(void);
#endif /* __LINUX_CLK_TEGRA_H_ */

2
sound/soc/tegra/tegra30_ahub.c
View File

@ -25,7 +25,7 @@
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <mach/clk.h>
#include <linux/clk/tegra.h>
#include <sound/soc.h>
#include "tegra30_ahub.h"