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sh: pci: Start unifying the SH7780 PCIC initialization.
This starts moving out the common initialization bits from the various fixup paths in to the shared init path. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Paul Mundt
parent
a6d377b696
commit
62c7ae87cb
@ -22,33 +22,15 @@ int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
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{
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return irq_tab[slot];
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}
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int pci_fixup_pcic(struct pci_channel *chan)
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{
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pci_write_reg(chan, 0x000043ff, SH4_PCIINTM);
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pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);
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pci_write_reg(chan, 0xfbb00047, SH7780_PCICMD);
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pci_write_reg(chan, 0x00000000, SH7780_PCIIBAR);
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pci_write_reg(chan, 0x00011912, SH7780_PCISVID);
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pci_write_reg(chan, 0x08000000, SH7780_PCICSCR0);
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pci_write_reg(chan, 0x0000001b, SH7780_PCICSAR0);
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pci_write_reg(chan, 0xfd000000, SH7780_PCICSCR1);
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pci_write_reg(chan, 0x0000000f, SH7780_PCICSAR1);
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pci_write_reg(chan, 0xfd000000, SH7780_PCIMBR0);
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pci_write_reg(chan, 0x00fc0000, SH7780_PCIMBMR0);
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#ifdef CONFIG_32BIT
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pci_write_reg(chan, 0xc0000000, SH7780_PCIMBR2);
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pci_write_reg(chan, 0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2);
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#endif
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/* Set IOBR for windows containing area specified in pci.h */
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pci_write_reg(chan, chan->io_resource->start & ~(SH7780_PCI_IO_SIZE-1),
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SH7780_PCIIOBR);
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pci_write_reg(chan, ((SH7780_PCI_IO_SIZE-1) & (7<<18)),
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SH7780_PCIIOBMR);
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return 0;
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}
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@ -35,40 +35,18 @@ int pci_fixup_pcic(struct pci_channel *chan)
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{
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/* Enable all interrupts, so we know what to fix */
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pci_write_reg(chan, 0x0000C3FF, SH7780_PCIIMR);
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pci_write_reg(chan, 0x0000380F, SH7780_PCIAINTM);
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/* Set up standard PCI config registers */
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pci_write_reg(chan, 0xFB00, SH7780_PCISTATUS);
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pci_write_reg(chan, 0x0047, SH7780_PCICMD);
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pci_write_reg(chan, 0x00, SH7780_PCIPIF);
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pci_write_reg(chan, 0x1912, SH7780_PCISVID);
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pci_write_reg(chan, 0x0001, SH7780_PCISID);
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pci_write_reg(chan, 0x08000000, SH7780_PCIMBAR0); /* PCI */
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pci_write_reg(chan, 0x08000000, SH7780_PCILAR0); /* SHwy */
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pci_write_reg(chan, 0x07F00001, SH7780_PCILSR); /* size 128M w/ MBAR */
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pci_write_reg(chan, 0x08000000, SH4_PCILAR0); /* SHwy */
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pci_write_reg(chan, 0x07F00001, SH4_PCILSR0); /* size 128M w/ MBAR */
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pci_write_reg(chan, 0x00000000, SH7780_PCIMBAR1);
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pci_write_reg(chan, 0x00000000, SH7780_PCILAR1);
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pci_write_reg(chan, 0x00000000, SH7780_PCILSR1);
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pci_write_reg(chan, 0x00000000, SH4_PCILAR1);
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pci_write_reg(chan, 0x00000000, SH4_PCILSR1);
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pci_write_reg(chan, 0xAB000801, SH7780_PCIIBAR);
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/*
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* Set the MBR so PCI address is one-to-one with window,
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* meaning all calls go straight through... use ifdef to
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* catch erroneous assumption.
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*/
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pci_write_reg(chan, 0xFD000000 , SH7780_PCIMBR0);
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pci_write_reg(chan, 0x00FC0000 , SH7780_PCIMBMR0); /* 16M */
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/* Set IOBR for window containing area specified in pci.h */
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pci_write_reg(chan, chan->io_resource->start & ~(SH7780_PCI_IO_SIZE-1),
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SH7780_PCIIOBR);
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pci_write_reg(chan, (SH7780_PCI_IO_SIZE-1) & (7 << 18),
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SH7780_PCIIOBMR);
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pci_write_reg(chan, 0xA5000C01, SH7780_PCICR);
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pci_write_reg(chan, 0xA5000C01, SH4_PCICR);
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return 0;
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}
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@ -1,19 +1,12 @@
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/*
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* Low-Level PCI Support for the SH7780
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* Low-Level PCI Support for the SH7780
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*
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* Dustin McIntire (dustin@sensoria.com)
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* Derived from arch/i386/kernel/pci-*.c which bore the message:
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* (c) 1999--2000 Martin Mares <mj@ucw.cz>
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*
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* Ported to the new API by Paul Mundt <lethal@linux-sh.org>
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* With cleanup by Paul van Gool <pvangool@mimotech.com>
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*
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* May be copied or modified under the terms of the GNU General Public
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* License. See linux/COPYING for more information.
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* Copyright (C) 2005 - 2009 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#undef DEBUG
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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@ -117,13 +110,8 @@ int __init pcibios_init_platform(void)
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pci_cache_line_size = pci_read_reg(chan, SH7780_PCICLS) / 4;
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/* set the command/status bits to:
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* Wait Cycle Control + Parity Enable + Bus Master +
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* Mem space enable
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*/
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pci_write_reg(chan, 0x00000046, SH7780_PCICMD);
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/* Set IO and Mem windows to local address
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/*
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* Set IO and Mem windows to local address
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* Make PCI and local address the same for easy 1 to 1 mapping
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*/
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pci_write_reg(chan, sh7780_pci_map.window0.size - 0xfffff, SH4_PCILSR0);
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@ -131,9 +119,33 @@ int __init pcibios_init_platform(void)
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pci_write_reg(chan, sh7780_pci_map.window0.base, SH4_PCILAR0);
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pci_write_reg(chan, sh7780_pci_map.window0.base, SH7780_PCIMBAR0);
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pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);
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/* Set up standard PCI config registers */
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__raw_writew(0xFB00, chan->reg_base + SH7780_PCISTATUS);
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__raw_writew(0x0047, chan->reg_base + SH7780_PCICMD);
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__raw_writew(0x1912, chan->reg_base + SH7780_PCISVID);
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__raw_writew(0x0001, chan->reg_base + SH7780_PCISID);
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__raw_writeb(0x00, chan->reg_base + SH7780_PCIPIF);
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/* Apply any last-minute PCIC fixups */
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pci_fixup_pcic(chan);
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pci_write_reg(chan, 0xfd000000, SH7780_PCIMBR0);
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pci_write_reg(chan, 0x00fc0000, SH7780_PCIMBMR0);
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#ifdef CONFIG_32BIT
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pci_write_reg(chan, 0xc0000000, SH7780_PCIMBR2);
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pci_write_reg(chan, 0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2);
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#endif
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/* Set IOBR for windows containing area specified in pci.h */
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pci_write_reg(chan, chan->io_resource->start & ~(SH7780_PCI_IO_SIZE-1),
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SH7780_PCIIOBR);
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pci_write_reg(chan, ((SH7780_PCI_IO_SIZE-1) & (7<<18)),
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SH7780_PCIIOBMR);
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/* SH7780 init done, set central function init complete */
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/* use round robin mode to stop a device starving/overruning */
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word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO;
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@ -65,11 +65,6 @@
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#define SH7780_PCIPMCSR_BSE 0x046
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#define SH7780_PCICDD 0x047
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#define SH7780_PCICR 0x100 /* PCI Control Register */
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#define SH7780_PCILSR 0x104 /* PCI Local Space Register0 */
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#define SH7780_PCILSR1 0x108 /* PCI Local Space Register1 */
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#define SH7780_PCILAR0 0x10C /* PCI Local Address Register1 */
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#define SH7780_PCILAR1 0x110 /* PCI Local Address Register1 */
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#define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
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#define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
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#define SH7780_PCIAIR 0x11C /* Error Address Register */
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