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drm/amd/powerplay: update all printk to pr_* on smumgr

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Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Huang Rui 2016-12-26 15:09:33 +08:00 committed by Alex Deucher
parent b5c11b8e37
commit 634a24d8af
10 changed files with 45 additions and 45 deletions
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28
drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
View File

@ -70,7 +70,7 @@ static int cz_send_msg_to_smc_async(struct pp_smumgr *smumgr,
result = SMUM_WAIT_FIELD_UNEQUAL(smumgr,
SMU_MP1_SRBM2P_RESP_0, CONTENT, 0);
if (result != 0) {
printk(KERN_ERR "[ powerplay ] cz_send_msg_to_smc_async failed\n");
pr_err("cz_send_msg_to_smc_async failed\n");
return result;
}
@ -100,12 +100,12 @@ static int cz_set_smc_sram_address(struct pp_smumgr *smumgr,
return -EINVAL;
if (0 != (3 & smc_address)) {
printk(KERN_ERR "[ powerplay ] SMC address must be 4 byte aligned\n");
pr_err("SMC address must be 4 byte aligned\n");
return -EINVAL;
}
if (limit <= (smc_address + 3)) {
printk(KERN_ERR "[ powerplay ] SMC address beyond the SMC RAM area\n");
pr_err("SMC address beyond the SMC RAM area\n");
return -EINVAL;
}
@ -147,7 +147,7 @@ static int cz_request_smu_load_fw(struct pp_smumgr *smumgr)
uint32_t smc_address;
if (!smumgr->reload_fw) {
printk(KERN_INFO "[ powerplay ] skip reloading...\n");
pr_info("skip reloading...\n");
return 0;
}
@ -198,7 +198,7 @@ static int cz_check_fw_load_finish(struct pp_smumgr *smumgr,
}
if (i >= smumgr->usec_timeout) {
printk(KERN_ERR "[ powerplay ] SMU check loaded firmware failed.\n");
pr_err("SMU check loaded firmware failed.\n");
return -EINVAL;
}
@ -267,13 +267,13 @@ static int cz_start_smu(struct pp_smumgr *smumgr)
ret = cz_request_smu_load_fw(smumgr);
if (ret)
printk(KERN_ERR "[ powerplay] SMU firmware load failed\n");
pr_err("SMU firmware load failed\n");
cz_check_fw_load_finish(smumgr, fw_to_check);
ret = cz_load_mec_firmware(smumgr);
if (ret)
printk(KERN_ERR "[ powerplay ] Mec Firmware load failed\n");
pr_err("Mec Firmware load failed\n");
return ret;
}
@ -406,7 +406,7 @@ static int cz_smu_populate_single_scratch_task(
break;
if (i >= cz_smu->scratch_buffer_length) {
printk(KERN_ERR "[ powerplay ] Invalid Firmware Type\n");
pr_err("Invalid Firmware Type\n");
return -EINVAL;
}
@ -443,7 +443,7 @@ static int cz_smu_populate_single_ucode_load_task(
break;
if (i >= cz_smu->driver_buffer_length) {
printk(KERN_ERR "[ powerplay ] Invalid Firmware Type\n");
pr_err("Invalid Firmware Type\n");
return -EINVAL;
}
@ -774,7 +774,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
UCODE_ID_RLC_SCRATCH_SIZE_BYTE,
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
printk(KERN_ERR "[ powerplay ] Error when Populate Firmware Entry.\n");
pr_err("Error when Populate Firmware Entry.\n");
return -1;
}
@ -782,14 +782,14 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE,
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
printk(KERN_ERR "[ powerplay ] Error when Populate Firmware Entry.\n");
pr_err("Error when Populate Firmware Entry.\n");
return -1;
}
if (0 != cz_smu_populate_single_scratch_entry(smumgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE,
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
printk(KERN_ERR "[ powerplay ] Error when Populate Firmware Entry.\n");
pr_err("Error when Populate Firmware Entry.\n");
return -1;
}
@ -797,7 +797,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
sizeof(struct SMU8_MultimediaPowerLogData),
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
printk(KERN_ERR "[ powerplay ] Error when Populate Firmware Entry.\n");
pr_err("Error when Populate Firmware Entry.\n");
return -1;
}
@ -805,7 +805,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE,
sizeof(struct SMU8_Fusion_ClkTable),
&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
printk(KERN_ERR "[ powerplay ] Error when Populate Firmware Entry.\n");
pr_err("Error when Populate Firmware Entry.\n");
return -1;
}
cz_smu_construct_toc(smumgr);

4
drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
View File

@ -2131,7 +2131,7 @@ uint32_t fiji_get_offsetof(uint32_t type, uint32_t member)
return offsetof(SMU73_Discrete_DpmTable, LowSclkInterruptThreshold);
}
}
printk(KERN_WARNING "can't get the offset of type %x member %x\n", type, member);
pr_warning("can't get the offset of type %x member %x\n", type, member);
return 0;
}
@ -2156,7 +2156,7 @@ uint32_t fiji_get_mac_definition(uint32_t value)
return SMU73_MAX_LEVELS_MVDD;
}
printk(KERN_WARNING "can't get the mac of %x\n", value);
pr_warning("can't get the mac of %x\n", value);
return 0;
}

8
drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
View File

@ -179,7 +179,7 @@ static int fiji_setup_pwr_virus(struct pp_smumgr *smumgr)
result = 0;
break;
default:
printk(KERN_ERR "Table Exit with Invalid Command!");
pr_err("Table Exit with Invalid Command!");
priv->avfs.AvfsBtcStatus = AVFS_BTC_VIRUS_FAIL;
result = -1;
break;
@ -202,13 +202,13 @@ static int fiji_start_avfs_btc(struct pp_smumgr *smumgr)
priv->avfs.AvfsBtcStatus = AVFS_BTC_COMPLETED_UNSAVED;
result = 0;
} else {
printk(KERN_ERR "[AVFS][fiji_start_avfs_btc] Attempt"
pr_err("[AVFS][fiji_start_avfs_btc] Attempt"
" to Enable AVFS Failed!");
smum_send_msg_to_smc(smumgr, PPSMC_MSG_DisableAvfs);
result = -1;
}
} else {
printk(KERN_ERR "[AVFS][fiji_start_avfs_btc] "
pr_err("[AVFS][fiji_start_avfs_btc] "
"PerformBTC SMU msg failed");
result = -1;
}
@ -384,7 +384,7 @@ static int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started)
case AVFS_BTC_NOTSUPPORTED: /* Do nothing */
break;
default:
printk(KERN_ERR "[AVFS] Something is broken. See log!");
pr_err("[AVFS] Something is broken. See log!");
break;
}
return 0;

8
drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
View File

@ -1545,7 +1545,7 @@ static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
if (0 != result) {
smu_data->smc_state_table.GraphicsBootLevel = 0;
printk(KERN_ERR "[ powerplay ] VBIOS did not find boot engine clock value \
pr_err("VBIOS did not find boot engine clock value \
in dependency table. Using Graphics DPM level 0!");
result = 0;
}
@ -1556,7 +1556,7 @@ static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
if (0 != result) {
smu_data->smc_state_table.MemoryBootLevel = 0;
printk(KERN_ERR "[ powerplay ] VBIOS did not find boot engine clock value \
pr_err("VBIOS did not find boot engine clock value \
in dependency table. Using Memory DPM level 0!");
result = 0;
}
@ -2146,7 +2146,7 @@ uint32_t iceland_get_offsetof(uint32_t type, uint32_t member)
return offsetof(SMU71_Discrete_DpmTable, LowSclkInterruptThreshold);
}
}
printk(KERN_WARNING "can't get the offset of type %x member %x\n", type, member);
pr_warning("can't get the offset of type %x member %x\n", type, member);
return 0;
}
@ -2169,7 +2169,7 @@ uint32_t iceland_get_mac_definition(uint32_t value)
return SMU71_MAX_LEVELS_MVDD;
}
printk(KERN_WARNING "can't get the mac of %x\n", value);
pr_warning("can't get the mac of %x\n", value);
return 0;
}

2
drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
View File

@ -176,7 +176,7 @@ static int iceland_start_smu(struct pp_smumgr *smumgr)
return result;
if (!smu7_is_smc_ram_running(smumgr)) {
printk("smu not running, upload firmware again \n");
pr_info("smu not running, upload firmware again \n");
result = iceland_smu_upload_firmware_image(smumgr);
if (result)
return result;

4
drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
View File

@ -2180,7 +2180,7 @@ uint32_t polaris10_get_offsetof(uint32_t type, uint32_t member)
return offsetof(SMU74_Discrete_DpmTable, LowSclkInterruptThreshold);
}
}
printk(KERN_WARNING "can't get the offset of type %x member %x\n", type, member);
pr_warning("can't get the offset of type %x member %x\n", type, member);
return 0;
}
@ -2207,7 +2207,7 @@ uint32_t polaris10_get_mac_definition(uint32_t value)
return SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
}
printk(KERN_WARNING "can't get the mac of %x\n", value);
pr_warning("can't get the mac of %x\n", value);
return 0;
}

8
drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
View File

@ -84,7 +84,7 @@ static int polaris10_setup_pwr_virus(struct pp_smumgr *smumgr)
break;
default:
printk("Table Exit with Invalid Command!");
pr_info("Table Exit with Invalid Command!");
smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
result = -1;
break;
@ -102,7 +102,7 @@ static int polaris10_perform_btc(struct pp_smumgr *smumgr)
if (0 != smu_data->avfs.avfs_btc_param) {
if (0 != smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
printk("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed");
pr_info("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed");
result = -1;
}
}
@ -189,7 +189,7 @@ polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
return -1);
if (smu_data->avfs.avfs_btc_param > 1) {
printk("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");
pr_info("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");
smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
PP_ASSERT_WITH_CODE(-1 == polaris10_setup_pwr_virus(smumgr),
"[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ",
@ -208,7 +208,7 @@ polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
break;
default:
printk("[AVFS] Something is broken. See log!");
pr_info("[AVFS] Something is broken. See log!");
break;
}

12
drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
View File

@ -175,7 +175,7 @@ int smu7_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP);
if (ret != 1)
printk("\n failed to send pre message %x ret is %d \n", msg, ret);
pr_info("\n failed to send pre message %x ret is %d \n", msg, ret);
cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
@ -184,7 +184,7 @@ int smu7_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP);
if (ret != 1)
printk("\n failed to send message %x ret is %d \n", msg, ret);
pr_info("\n failed to send message %x ret is %d \n", msg, ret);
return 0;
}
@ -225,7 +225,7 @@ int smu7_send_msg_to_smc_offset(struct pp_smumgr *smumgr)
SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP))
printk("Failed to send Message.\n");
pr_info("Failed to send Message.\n");
return 0;
}
@ -347,7 +347,7 @@ static uint32_t smu7_get_mask_for_firmware_type(uint32_t fw_type)
result = UCODE_ID_RLC_G_MASK;
break;
default:
printk("UCode type is out of range! \n");
pr_info("UCode type is out of range! \n");
result = 0;
}
@ -396,7 +396,7 @@ int smu7_request_smu_load_fw(struct pp_smumgr *smumgr)
struct SMU_DRAMData_TOC *toc;
if (!smumgr->reload_fw) {
printk(KERN_INFO "[ powerplay ] skip reloading...\n");
pr_info("skip reloading...\n");
return 0;
}
@ -474,7 +474,7 @@ int smu7_request_smu_load_fw(struct pp_smumgr *smumgr)
smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low);
if (smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_LoadUcodes, fw_to_load))
printk(KERN_ERR "Fail to Request SMU Load uCode");
pr_err("Fail to Request SMU Load uCode");
return result;
}

14
drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
View File

@ -656,7 +656,7 @@ int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
}
} else {
if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask)
printk(KERN_ERR "[ powerplay ] Pcie Dpm Enablemask is 0 !");
pr_err("Pcie Dpm Enablemask is 0 !");
while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
@ -1503,7 +1503,7 @@ static int tonga_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
if (result != 0) {
smu_data->smc_state_table.GraphicsBootLevel = 0;
printk(KERN_ERR "[powerplay] VBIOS did not find boot engine "
pr_err("[powerplay] VBIOS did not find boot engine "
"clock value in dependency table. "
"Using Graphics DPM level 0 !");
result = 0;
@ -1515,7 +1515,7 @@ static int tonga_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
if (result != 0) {
smu_data->smc_state_table.MemoryBootLevel = 0;
printk(KERN_ERR "[powerplay] VBIOS did not find boot "
pr_err("[powerplay] VBIOS did not find boot "
"engine clock value in dependency table."
"Using Memory DPM level 0 !");
result = 0;
@ -1739,7 +1739,7 @@ static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr,
config = VR_SVI2_PLANE_2;
table->VRConfig |= config;
} else {
printk(KERN_ERR "[ powerplay ] VDDC and VDDGFX should "
pr_err("VDDC and VDDGFX should "
"be both on SVI2 control in splitted mode !\n");
}
} else {
@ -1752,7 +1752,7 @@ static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr,
config = VR_SVI2_PLANE_1;
table->VRConfig |= config;
} else {
printk(KERN_ERR "[ powerplay ] VDDC should be on "
pr_err("VDDC should be on "
"SVI2 control in merged mode !\n");
}
}
@ -2657,7 +2657,7 @@ uint32_t tonga_get_offsetof(uint32_t type, uint32_t member)
return offsetof(SMU72_Discrete_DpmTable, LowSclkInterruptThreshold);
}
}
printk(KERN_WARNING "can't get the offset of type %x member %x\n", type, member);
pr_warning("can't get the offset of type %x member %x\n", type, member);
return 0;
}
@ -2681,7 +2681,7 @@ uint32_t tonga_get_mac_definition(uint32_t value)
case SMU_MAX_LEVELS_MVDD:
return SMU72_MAX_LEVELS_MVDD;
}
printk(KERN_WARNING "can't get the mac value %x\n", value);
pr_warning("can't get the mac value %x\n", value);
return 0;
}

2
drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
View File

@ -84,7 +84,7 @@ static int tonga_start_in_protection_mode(struct pp_smumgr *smumgr)
/* Check pass/failed indicator */
if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device,
CGS_IND_REG__SMC, SMU_STATUS, SMU_PASS)) {
printk(KERN_ERR "[ powerplay ] SMU Firmware start failed\n");
pr_err("SMU Firmware start failed\n");
return -EINVAL;
}