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MIPS: Pistachio: Remove plat_setup_iocoherency

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The Pistachio SoC does not have an IOCU.  Hence, DMA is non-coherent.

Remove the function checking for iocoherency and select
CONFIG_DMA_NONCOHERENT in Kconfig

This code is probably accidentally inherited from Malta.

Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Reviewed-by: James Hartley <james.hartley@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13433/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Zubair Lutfullah Kakakhel 2016-06-03 09:35:00 +01:00 committed by Ralf Baechle
parent 666dc36764
commit 645c7827e6
2 changed files with 1 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/mips/Kconfig
View File

@ -384,7 +384,7 @@ config MACH_PISTACHIO
select CLKSRC_MIPS_GIC select CLKSRC_MIPS_GIC
select COMMON_CLK select COMMON_CLK
select CSRC_R4K select CSRC_R4K
select DMA_MAYBE_COHERENT select DMA_NONCOHERENT
select GPIOLIB select GPIOLIB
select IRQ_MIPS_CPU select IRQ_MIPS_CPU
select LIBFDT select LIBFDT

25
arch/mips/pistachio/init.c
View File

@ -60,29 +60,6 @@ const char *get_system_type(void)
return sys_type; return sys_type;
} }
static void __init plat_setup_iocoherency(void)
{
/*
* Kernel has been configured with software coherency
* but we might choose to turn it off and use hardware
* coherency instead.
*/
if (mips_cm_numiocu() != 0) {
/* Nothing special needs to be done to enable coherency */
pr_info("CMP IOCU detected\n");
hw_coherentio = 1;
if (coherentio == 0)
pr_info("Hardware DMA cache coherency disabled\n");
else
pr_info("Hardware DMA cache coherency enabled\n");
} else {
if (coherentio == 1)
pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
else
pr_info("Software DMA cache coherency enabled\n");
}
}
void __init *plat_get_fdt(void) void __init *plat_get_fdt(void)
{ {
if (fw_arg0 != -2) if (fw_arg0 != -2)
@ -93,8 +70,6 @@ void __init *plat_get_fdt(void)
void __init plat_mem_setup(void) void __init plat_mem_setup(void)
{ {
__dt_setup_arch(plat_get_fdt()); __dt_setup_arch(plat_get_fdt());
plat_setup_iocoherency();
} }
#define DEFAULT_CPC_BASE_ADDR 0x1bde0000 #define DEFAULT_CPC_BASE_ADDR 0x1bde0000