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IB/mthca: Optimize large messages on Sinai HCAs
Sinai (one-port PCI Express) HCAs get improved throughput for messages bigger than 80 KB in DDR mode if memory keys are formatted in a specific way. The enhancement only works if the memory key table is smaller than 2^24 entries. For larger tables, the enhancement is off and a warning is printed (to avoid silent performance loss). Signed-off-by: Eli Cohen <eli@mellanox.co.il> Signed-off-by: Michael Tsirkin <mst@mellanox.co.il> Signed-off-by: Roland Dreier <rolandd@cisco.com>
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@ -1277,7 +1277,8 @@ int mthca_INIT_HCA(struct mthca_dev *dev,
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int err;
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#define INIT_HCA_IN_SIZE 0x200
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#define INIT_HCA_FLAGS_OFFSET 0x014
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#define INIT_HCA_FLAGS1_OFFSET 0x00c
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#define INIT_HCA_FLAGS2_OFFSET 0x014
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#define INIT_HCA_QPC_OFFSET 0x020
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#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
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#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
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@ -1320,15 +1321,18 @@ int mthca_INIT_HCA(struct mthca_dev *dev,
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memset(inbox, 0, INIT_HCA_IN_SIZE);
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if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
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MTHCA_PUT(inbox, 0x1, INIT_HCA_FLAGS1_OFFSET);
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#if defined(__LITTLE_ENDIAN)
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*(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
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*(inbox + INIT_HCA_FLAGS2_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
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#elif defined(__BIG_ENDIAN)
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*(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
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*(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1 << 1);
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#else
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#error Host endianness not defined
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#endif
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/* Check port for UD address vector: */
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*(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
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*(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1);
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/* We leave wqe_quota, responder_exu, etc as 0 (default) */
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@ -64,7 +64,8 @@ enum {
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MTHCA_FLAG_NO_LAM = 1 << 5,
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MTHCA_FLAG_FMR = 1 << 6,
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MTHCA_FLAG_MEMFREE = 1 << 7,
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MTHCA_FLAG_PCIE = 1 << 8
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MTHCA_FLAG_PCIE = 1 << 8,
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MTHCA_FLAG_SINAI_OPT = 1 << 9
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};
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enum {
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@ -935,13 +935,19 @@ enum {
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static struct {
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u64 latest_fw;
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int is_memfree;
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int is_pcie;
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u32 flags;
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} mthca_hca_table[] = {
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[TAVOR] = { .latest_fw = MTHCA_FW_VER(3, 3, 3), .is_memfree = 0, .is_pcie = 0 },
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[ARBEL_COMPAT] = { .latest_fw = MTHCA_FW_VER(4, 7, 0), .is_memfree = 0, .is_pcie = 1 },
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[ARBEL_NATIVE] = { .latest_fw = MTHCA_FW_VER(5, 1, 0), .is_memfree = 1, .is_pcie = 1 },
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[SINAI] = { .latest_fw = MTHCA_FW_VER(1, 0, 1), .is_memfree = 1, .is_pcie = 1 }
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[TAVOR] = { .latest_fw = MTHCA_FW_VER(3, 3, 3),
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.flags = 0 },
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[ARBEL_COMPAT] = { .latest_fw = MTHCA_FW_VER(4, 7, 0),
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.flags = MTHCA_FLAG_PCIE },
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[ARBEL_NATIVE] = { .latest_fw = MTHCA_FW_VER(5, 1, 0),
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.flags = MTHCA_FLAG_MEMFREE |
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MTHCA_FLAG_PCIE },
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[SINAI] = { .latest_fw = MTHCA_FW_VER(1, 0, 1),
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.flags = MTHCA_FLAG_MEMFREE |
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MTHCA_FLAG_PCIE |
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MTHCA_FLAG_SINAI_OPT }
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};
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static int __devinit mthca_init_one(struct pci_dev *pdev,
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@ -1031,12 +1037,9 @@ static int __devinit mthca_init_one(struct pci_dev *pdev,
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mdev->pdev = pdev;
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mdev->mthca_flags = mthca_hca_table[id->driver_data].flags;
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if (ddr_hidden)
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mdev->mthca_flags |= MTHCA_FLAG_DDR_HIDDEN;
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if (mthca_hca_table[id->driver_data].is_memfree)
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mdev->mthca_flags |= MTHCA_FLAG_MEMFREE;
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if (mthca_hca_table[id->driver_data].is_pcie)
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mdev->mthca_flags |= MTHCA_FLAG_PCIE;
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/*
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* Now reset the HCA before we touch the PCI capabilities or
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@ -76,6 +76,8 @@ struct mthca_mpt_entry {
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#define MTHCA_MPT_STATUS_SW 0xF0
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#define MTHCA_MPT_STATUS_HW 0x00
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#define SINAI_FMR_KEY_INC 0x1000000
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/*
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* Buddy allocator for MTT segments (currently not very efficient
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* since it doesn't keep a free list and just searches linearly
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@ -330,6 +332,14 @@ static inline u32 key_to_hw_index(struct mthca_dev *dev, u32 key)
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return tavor_key_to_hw_index(key);
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}
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static inline u32 adjust_key(struct mthca_dev *dev, u32 key)
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{
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if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
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return ((key << 20) & 0x800000) | (key & 0x7fffff);
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else
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return key;
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}
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int mthca_mr_alloc(struct mthca_dev *dev, u32 pd, int buffer_size_shift,
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u64 iova, u64 total_size, u32 access, struct mthca_mr *mr)
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{
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@ -345,6 +355,7 @@ int mthca_mr_alloc(struct mthca_dev *dev, u32 pd, int buffer_size_shift,
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key = mthca_alloc(&dev->mr_table.mpt_alloc);
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if (key == -1)
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return -ENOMEM;
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key = adjust_key(dev, key);
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mr->ibmr.rkey = mr->ibmr.lkey = hw_index_to_key(dev, key);
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if (mthca_is_memfree(dev)) {
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@ -504,6 +515,7 @@ int mthca_fmr_alloc(struct mthca_dev *dev, u32 pd,
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key = mthca_alloc(&dev->mr_table.mpt_alloc);
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if (key == -1)
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return -ENOMEM;
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key = adjust_key(dev, key);
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idx = key & (dev->limits.num_mpts - 1);
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mr->ibmr.rkey = mr->ibmr.lkey = hw_index_to_key(dev, key);
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@ -687,7 +699,10 @@ int mthca_arbel_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
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++fmr->maps;
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key = arbel_key_to_hw_index(fmr->ibmr.lkey);
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key += dev->limits.num_mpts;
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if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
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key += SINAI_FMR_KEY_INC;
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else
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key += dev->limits.num_mpts;
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fmr->ibmr.lkey = fmr->ibmr.rkey = arbel_hw_index_to_key(key);
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*(u8 *) fmr->mem.arbel.mpt = MTHCA_MPT_STATUS_SW;
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@ -760,6 +775,9 @@ int __devinit mthca_init_mr_table(struct mthca_dev *dev)
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else
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dev->mthca_flags |= MTHCA_FLAG_FMR;
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if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
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mthca_dbg(dev, "Memory key throughput optimization activated.\n");
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err = mthca_buddy_init(&dev->mr_table.mtt_buddy,
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fls(dev->limits.num_mtt_segs - 1));
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@ -152,7 +152,7 @@ u64 mthca_make_profile(struct mthca_dev *dev,
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}
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if (total_size > mem_avail) {
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mthca_err(dev, "Profile requires 0x%llx bytes; "
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"won't in 0x%llx bytes of context memory.\n",
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"won't fit in 0x%llx bytes of context memory.\n",
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(unsigned long long) total_size,
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(unsigned long long) mem_avail);
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kfree(profile);
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@ -262,6 +262,14 @@ u64 mthca_make_profile(struct mthca_dev *dev,
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*/
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dev->limits.num_pds = MTHCA_NUM_PDS;
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if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT &&
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init_hca->log_mpt_sz > 23) {
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mthca_warn(dev, "MPT table too large (requested size 2^%d >= 2^24)\n",
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init_hca->log_mpt_sz);
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mthca_warn(dev, "Disabling memory key throughput optimization.\n");
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dev->mthca_flags &= ~MTHCA_FLAG_SINAI_OPT;
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}
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/*
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* For Tavor, FMRs use ioremapped PCI memory. For 32 bit
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* systems it may use too much vmalloc space to map all MTT
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