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[ARM] 4194/1: S3C2443: include/asm-arm/arch-s3c2410/regs-gpio.h updates
Updates for regs-gpio.h for S3C2443 Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Ben Dooks
Russell King
parent
e9390ef845
commit
6619d58a65
@ -201,7 +201,7 @@
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#define S3C2400_GPBDAT S3C2410_GPIOREG(0x0C)
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#define S3C2400_GPBUP S3C2410_GPIOREG(0x10)
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/* no i/o pin in port b can have value 3! */
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/* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */
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#define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0)
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#define S3C2410_GPB0_INP (0x00 << 0)
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@ -242,6 +242,7 @@
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#define S3C2410_GPB5_INP (0x00 << 10)
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#define S3C2410_GPB5_OUTP (0x01 << 10)
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#define S3C2410_GPB5_nXBACK (0x02 << 10)
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#define S3C2443_GPB5_XBACK (0x03 << 10)
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#define S3C2400_GPB5_DATA21 (0x02 << 10)
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#define S3C2400_GPB5_nCTS1 (0x03 << 10)
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@ -249,6 +250,7 @@
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#define S3C2410_GPB6_INP (0x00 << 12)
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#define S3C2410_GPB6_OUTP (0x01 << 12)
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#define S3C2410_GPB6_nXBREQ (0x02 << 12)
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#define S3C2443_GPB6_XBREQ (0x03 << 12)
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#define S3C2400_GPB6_DATA22 (0x02 << 12)
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#define S3C2400_GPB6_nRTS1 (0x03 << 12)
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@ -256,6 +258,7 @@
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#define S3C2410_GPB7_INP (0x00 << 14)
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#define S3C2410_GPB7_OUTP (0x01 << 14)
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#define S3C2410_GPB7_nXDACK1 (0x02 << 14)
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#define S3C2443_GPB7_XDACK1 (0x03 << 14)
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#define S3C2400_GPB7_DATA23 (0x02 << 14)
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#define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8)
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@ -268,6 +271,7 @@
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#define S3C2410_GPB9_INP (0x00 << 18)
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#define S3C2410_GPB9_OUTP (0x01 << 18)
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#define S3C2410_GPB9_nXDACK0 (0x02 << 18)
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#define S3C2443_GPB9_XDACK0 (0x03 << 18)
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#define S3C2400_GPB9_DATA25 (0x02 << 18)
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#define S3C2400_GPB9_I2SSDI (0x03 << 18)
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@ -275,6 +279,7 @@
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#define S3C2410_GPB10_INP (0x00 << 20)
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#define S3C2410_GPB10_OUTP (0x01 << 20)
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#define S3C2410_GPB10_nXDRE0 (0x02 << 20)
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#define S3C2443_GPB10_XDREQ0 (0x03 << 20)
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#define S3C2400_GPB10_DATA26 (0x02 << 20)
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#define S3C2400_GPB10_nSS (0x03 << 20)
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@ -556,6 +561,7 @@
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#define S3C2410_GPE0_INP (0x00 << 0)
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#define S3C2410_GPE0_OUTP (0x01 << 0)
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#define S3C2410_GPE0_I2SLRCK (0x02 << 0)
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#define S3C2443_GPE0_AC_nRESET (0x03 << 0)
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#define S3C2400_GPE0_EINT0 (0x02 << 0)
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#define S3C2410_GPE0_MASK (0x03 << 0)
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@ -563,6 +569,7 @@
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#define S3C2410_GPE1_INP (0x00 << 2)
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#define S3C2410_GPE1_OUTP (0x01 << 2)
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#define S3C2410_GPE1_I2SSCLK (0x02 << 2)
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#define S3C2443_GPE1_AC_SYNC (0x03 << 2)
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#define S3C2400_GPE1_EINT1 (0x02 << 2)
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#define S3C2400_GPE1_nSS (0x03 << 2)
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#define S3C2410_GPE1_MASK (0x03 << 2)
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@ -571,6 +578,7 @@
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#define S3C2410_GPE2_INP (0x00 << 4)
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#define S3C2410_GPE2_OUTP (0x01 << 4)
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#define S3C2410_GPE2_CDCLK (0x02 << 4)
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#define S3C2443_GPE2_AC_BITCLK (0x03 << 4)
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#define S3C2400_GPE2_EINT2 (0x02 << 4)
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#define S3C2400_GPE2_I2SSDI (0x03 << 4)
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@ -578,6 +586,7 @@
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#define S3C2410_GPE3_INP (0x00 << 6)
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#define S3C2410_GPE3_OUTP (0x01 << 6)
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#define S3C2410_GPE3_I2SSDI (0x02 << 6)
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#define S3C2443_GPE3_AC_SDI (0x03 << 6)
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#define S3C2400_GPE3_EINT3 (0x02 << 6)
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#define S3C2400_GPE3_nCTS1 (0x03 << 6)
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#define S3C2410_GPE3_nSS0 (0x03 << 6)
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@ -587,6 +596,7 @@
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#define S3C2410_GPE4_INP (0x00 << 8)
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#define S3C2410_GPE4_OUTP (0x01 << 8)
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#define S3C2410_GPE4_I2SSDO (0x02 << 8)
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#define S3C2443_GPE4_AC_SDO (0x03 << 8)
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#define S3C2400_GPE4_EINT4 (0x02 << 8)
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#define S3C2400_GPE4_nRTS1 (0x03 << 8)
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#define S3C2410_GPE4_I2SSDI (0x03 << 8)
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@ -596,6 +606,7 @@
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#define S3C2410_GPE5_INP (0x00 << 10)
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#define S3C2410_GPE5_OUTP (0x01 << 10)
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#define S3C2410_GPE5_SDCLK (0x02 << 10)
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#define S3C2443_GPE5_SD1_CLK (0x02 << 10)
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#define S3C2400_GPE5_EINT5 (0x02 << 10)
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#define S3C2400_GPE5_TCLK1 (0x03 << 10)
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@ -603,24 +614,32 @@
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#define S3C2410_GPE6_INP (0x00 << 12)
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#define S3C2410_GPE6_OUTP (0x01 << 12)
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#define S3C2410_GPE6_SDCMD (0x02 << 12)
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#define S3C2443_GPE6_SD1_CMD (0x02 << 12)
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#define S3C2443_GPE6_AC_BITCLK (0x03 << 12)
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#define S3C2400_GPE6_EINT6 (0x02 << 12)
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#define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7)
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#define S3C2410_GPE7_INP (0x00 << 14)
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#define S3C2410_GPE7_OUTP (0x01 << 14)
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#define S3C2410_GPE7_SDDAT0 (0x02 << 14)
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#define S3C2443_GPE5_SD1_DAT0 (0x02 << 14)
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#define S3C2443_GPE7_AC_SDI (0x03 << 14)
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#define S3C2400_GPE7_EINT7 (0x02 << 14)
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#define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8)
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#define S3C2410_GPE8_INP (0x00 << 16)
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#define S3C2410_GPE8_OUTP (0x01 << 16)
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#define S3C2410_GPE8_SDDAT1 (0x02 << 16)
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#define S3C2443_GPE8_SD1_DAT1 (0x02 << 16)
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#define S3C2443_GPE8_AC_SDO (0x03 << 16)
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#define S3C2400_GPE8_nXDACK0 (0x02 << 16)
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#define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9)
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#define S3C2410_GPE9_INP (0x00 << 18)
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#define S3C2410_GPE9_OUTP (0x01 << 18)
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#define S3C2410_GPE9_SDDAT2 (0x02 << 18)
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#define S3C2443_GPE9_SD1_DAT2 (0x02 << 18)
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#define S3C2443_GPE9_AC_SYNC (0x03 << 18)
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#define S3C2400_GPE9_nXDACK1 (0x02 << 18)
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#define S3C2400_GPE9_nXBACK (0x03 << 18)
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@ -628,6 +647,8 @@
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#define S3C2410_GPE10_INP (0x00 << 20)
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#define S3C2410_GPE10_OUTP (0x01 << 20)
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#define S3C2410_GPE10_SDDAT3 (0x02 << 20)
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#define S3C2443_GPE10_SD1_DAT3 (0x02 << 20)
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#define S3C2443_GPE10_AC_nRESET (0x03 << 20)
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#define S3C2400_GPE10_nXDREQ0 (0x02 << 20)
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#define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11)
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@ -796,6 +817,7 @@
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#define S3C2400_GPG4_MMCCLK (0x02 << 8)
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#define S3C2400_GPG4_I2SSDI (0x03 << 8)
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#define S3C2410_GPG4_LCDPWREN (0x03 << 8)
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#define S3C2443_GPG4_LCDPWRDN (0x03 << 8)
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#define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5)
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#define S3C2410_GPG5_INP (0x00 << 10)
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@ -803,7 +825,7 @@
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#define S3C2410_GPG5_EINT13 (0x02 << 10)
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#define S3C2400_GPG5_MMCCMD (0x02 << 10)
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#define S3C2400_GPG5_IICSDA (0x03 << 10)
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#define S3C2410_GPG5_SPIMISO1 (0x03 << 10)
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#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */
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#define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6)
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#define S3C2410_GPG6_INP (0x00 << 12)
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@ -845,6 +867,7 @@
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#define S3C2410_GPG11_OUTP (0x01 << 22)
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#define S3C2410_GPG11_EINT19 (0x02 << 22)
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#define S3C2410_GPG11_TCLK1 (0x03 << 22)
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#define S3C2443_GPG11_CF_nIREQ (0x03 << 22)
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#define S3C2410_GPG12 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12)
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#define S3C2410_GPG12_INP (0x00 << 24)
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@ -852,25 +875,28 @@
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#define S3C2410_GPG12_EINT20 (0x02 << 24)
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#define S3C2410_GPG12_XMON (0x03 << 24)
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#define S3C2442_GPG12_nSPICS0 (0x03 << 24)
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#define S3C2443_GPG12_nINPACK (0x03 << 24)
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#define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13)
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#define S3C2410_GPG13_INP (0x00 << 26)
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#define S3C2410_GPG13_OUTP (0x01 << 26)
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#define S3C2410_GPG13_EINT21 (0x02 << 26)
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#define S3C2410_GPG13_nXPON (0x03 << 26)
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#define S3C2443_GPG13_CF_nREG (0x03 << 26)
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#define S3C2410_GPG14 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14)
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#define S3C2410_GPG14_INP (0x00 << 28)
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#define S3C2410_GPG14_OUTP (0x01 << 28)
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#define S3C2410_GPG14_EINT22 (0x02 << 28)
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#define S3C2410_GPG14_YMON (0x03 << 28)
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#define S3C2443_GPG14_CF_RESET (0x03 << 28)
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#define S3C2410_GPG15 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15)
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#define S3C2410_GPG15_INP (0x00 << 30)
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#define S3C2410_GPG15_OUTP (0x01 << 30)
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#define S3C2410_GPG15_EINT23 (0x02 << 30)
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#define S3C2410_GPG15_nYPON (0x03 << 30)
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#define S3C2443_GPG15_CF_PWR (0x03 << 30)
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#define S3C2410_GPG_PUPDIS(x) (1<<(x))
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