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https://github.com/FEX-Emu/linux.git
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Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 cpu updates from Ingo Molnar: "The main changes in this cycle were: - Improved CPU ID handling code and related enhancements (Borislav Petkov) - RDRAND fix (Len Brown)" * 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86: Replace RDRAND forced-reseed with simple sanity check x86/MSR: Chop off lower 32-bit value x86/cpu: Fix MSR value truncation issue x86/cpu/amd, kvm: Satisfy guest kernel reads of IC_CFG MSR kvm: Add accessors for guest CPU's family, model, stepping x86/cpu: Unify CPU family, model, stepping calculation
This commit is contained in:
commit
671d5532aa
@ -36,4 +36,7 @@ extern int _debug_hotplug_cpu(int cpu, int action);
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int mwait_usable(const struct cpuinfo_x86 *);
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unsigned int x86_family(unsigned int sig);
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unsigned int x86_model(unsigned int sig);
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unsigned int x86_stepping(unsigned int sig);
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#endif /* _ASM_X86_CPU_H */
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@ -1,6 +1,7 @@
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#ifndef _ASM_X86_MICROCODE_H
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#define _ASM_X86_MICROCODE_H
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#include <asm/cpu.h>
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#include <linux/earlycpio.h>
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#define native_rdmsr(msr, val1, val2) \
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@ -95,14 +96,14 @@ static inline void __exit exit_amd_microcode(void) {}
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/*
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* In early loading microcode phase on BSP, boot_cpu_data is not set up yet.
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* x86_vendor() gets vendor id for BSP.
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* x86_cpuid_vendor() gets vendor id for BSP.
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*
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* In 32 bit AP case, accessing boot_cpu_data needs linear address. To simplify
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* coding, we still use x86_vendor() to get vendor id for AP.
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* coding, we still use x86_cpuid_vendor() to get vendor id for AP.
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*
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* x86_vendor() gets vendor information directly from CPUID.
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* x86_cpuid_vendor() gets vendor information directly from CPUID.
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*/
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static inline int x86_vendor(void)
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static inline int x86_cpuid_vendor(void)
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{
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u32 eax = 0x00000000;
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u32 ebx, ecx = 0, edx;
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@ -118,40 +119,14 @@ static inline int x86_vendor(void)
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return X86_VENDOR_UNKNOWN;
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}
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static inline unsigned int __x86_family(unsigned int sig)
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{
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unsigned int x86;
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x86 = (sig >> 8) & 0xf;
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if (x86 == 0xf)
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x86 += (sig >> 20) & 0xff;
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return x86;
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}
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static inline unsigned int x86_family(void)
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static inline unsigned int x86_cpuid_family(void)
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{
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u32 eax = 0x00000001;
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u32 ebx, ecx = 0, edx;
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native_cpuid(&eax, &ebx, &ecx, &edx);
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return __x86_family(eax);
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}
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static inline unsigned int x86_model(unsigned int sig)
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{
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unsigned int x86, model;
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x86 = __x86_family(sig);
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model = (sig >> 4) & 0xf;
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if (x86 == 0x6 || x86 == 0xf)
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model += ((sig >> 16) & 0xf) << 4;
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return model;
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return x86_family(eax);
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}
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#ifdef CONFIG_MICROCODE
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@ -321,6 +321,7 @@
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#define MSR_F15H_PERF_CTR 0xc0010201
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#define MSR_F15H_NB_PERF_CTL 0xc0010240
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#define MSR_F15H_NB_PERF_CTR 0xc0010241
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#define MSR_F15H_IC_CFG 0xc0011021
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/* Fam 10h MSRs */
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#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
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@ -221,7 +221,7 @@ static inline void wrmsr(unsigned msr, unsigned low, unsigned high)
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static inline void wrmsrl(unsigned msr, u64 val)
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{
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native_write_msr(msr, (u32)val, (u32)(val >> 32));
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native_write_msr(msr, (u32)(val & 0xffffffffULL), (u32)(val >> 32));
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}
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/* wrmsr with exception handling */
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@ -678,9 +678,9 @@ static void init_amd_bd(struct cpuinfo_x86 *c)
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* Disable it on the affected CPUs.
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*/
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if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
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if (!rdmsrl_safe(0xc0011021, &value) && !(value & 0x1E)) {
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if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) {
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value |= 0x1E;
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wrmsrl_safe(0xc0011021, value);
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wrmsrl_safe(MSR_F15H_IC_CFG, value);
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}
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}
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}
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@ -581,14 +581,9 @@ void cpu_detect(struct cpuinfo_x86 *c)
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u32 junk, tfms, cap0, misc;
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cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
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c->x86 = (tfms >> 8) & 0xf;
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c->x86_model = (tfms >> 4) & 0xf;
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c->x86_mask = tfms & 0xf;
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if (c->x86 == 0xf)
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c->x86 += (tfms >> 20) & 0xff;
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if (c->x86 >= 0x6)
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c->x86_model += ((tfms >> 16) & 0xf) << 4;
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c->x86 = x86_family(tfms);
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c->x86_model = x86_model(tfms);
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c->x86_mask = x86_stepping(tfms);
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if (cap0 & (1<<19)) {
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c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
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@ -1187,7 +1182,7 @@ void syscall_init(void)
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* They both write to the same internal register. STAR allows to
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* set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
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*/
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wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
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wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
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wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
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#ifdef CONFIG_IA32_EMULATION
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@ -129,8 +129,8 @@ void __init load_ucode_bsp(void)
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if (!have_cpuid_p())
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return;
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vendor = x86_vendor();
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family = x86_family();
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vendor = x86_cpuid_vendor();
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family = x86_cpuid_family();
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switch (vendor) {
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case X86_VENDOR_INTEL:
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@ -165,8 +165,8 @@ void load_ucode_ap(void)
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if (!have_cpuid_p())
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return;
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vendor = x86_vendor();
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family = x86_family();
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vendor = x86_cpuid_vendor();
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family = x86_cpuid_family();
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switch (vendor) {
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case X86_VENDOR_INTEL:
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@ -206,8 +206,8 @@ void reload_early_microcode(void)
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{
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int vendor, family;
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vendor = x86_vendor();
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family = x86_family();
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vendor = x86_cpuid_vendor();
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family = x86_cpuid_family();
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switch (vendor) {
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case X86_VENDOR_INTEL:
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@ -145,10 +145,10 @@ matching_model_microcode(struct microcode_header_intel *mc_header,
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int ext_sigcount, i;
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struct extended_signature *ext_sig;
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fam = __x86_family(sig);
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fam = x86_family(sig);
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model = x86_model(sig);
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fam_ucode = __x86_family(mc_header->sig);
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fam_ucode = x86_family(mc_header->sig);
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model_ucode = x86_model(mc_header->sig);
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if (fam == fam_ucode && model == model_ucode)
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@ -163,7 +163,7 @@ matching_model_microcode(struct microcode_header_intel *mc_header,
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ext_sigcount = ext_header->count;
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for (i = 0; i < ext_sigcount; i++) {
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fam_ucode = __x86_family(ext_sig->sig);
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fam_ucode = x86_family(ext_sig->sig);
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model_ucode = x86_model(ext_sig->sig);
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if (fam == fam_ucode && model == model_ucode)
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@ -365,7 +365,7 @@ static int collect_cpu_info_early(struct ucode_cpu_info *uci)
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native_cpuid(&eax, &ebx, &ecx, &edx);
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csig.sig = eax;
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family = __x86_family(csig.sig);
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family = x86_family(csig.sig);
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model = x86_model(csig.sig);
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if ((model >= 5) || (family > 6)) {
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@ -521,16 +521,12 @@ static bool __init load_builtin_intel_microcode(struct cpio_data *cp)
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{
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#ifdef CONFIG_X86_64
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unsigned int eax = 0x00000001, ebx, ecx = 0, edx;
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unsigned int family, model, stepping;
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char name[30];
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native_cpuid(&eax, &ebx, &ecx, &edx);
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family = __x86_family(eax);
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model = x86_model(eax);
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stepping = eax & 0xf;
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sprintf(name, "intel-ucode/%02x-%02x-%02x", family, model, stepping);
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sprintf(name, "intel-ucode/%02x-%02x-%02x",
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x86_family(eax), x86_model(eax), x86_stepping(eax));
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return get_builtin_firmware(cp, name);
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#else
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@ -33,28 +33,27 @@ static int __init x86_rdrand_setup(char *s)
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__setup("nordrand", x86_rdrand_setup);
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/*
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* Force a reseed cycle; we are architecturally guaranteed a reseed
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* after no more than 512 128-bit chunks of random data. This also
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* acts as a test of the CPU capability.
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* RDRAND has Built-In-Self-Test (BIST) that runs on every invocation.
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* Run the instruction a few times as a sanity check.
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* If it fails, it is simple to disable RDRAND here.
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*/
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#define RESEED_LOOP ((512*128)/sizeof(unsigned long))
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#define SANITY_CHECK_LOOPS 8
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void x86_init_rdrand(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_ARCH_RANDOM
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unsigned long tmp;
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int i, count, ok;
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int i;
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if (!cpu_has(c, X86_FEATURE_RDRAND))
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return; /* Nothing to do */
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return;
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for (count = i = 0; i < RESEED_LOOP; i++) {
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ok = rdrand_long(&tmp);
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if (ok)
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count++;
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for (i = 0; i < SANITY_CHECK_LOOPS; i++) {
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if (!rdrand_long(&tmp)) {
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clear_cpu_cap(c, X86_FEATURE_RDRAND);
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printk_once(KERN_WARNING "rdrand: disabled\n");
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return;
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}
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}
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if (count != RESEED_LOOP)
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clear_cpu_cap(c, X86_FEATURE_RDRAND);
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#endif
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}
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@ -2,6 +2,7 @@
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#define ARCH_X86_KVM_CPUID_H
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#include "x86.h"
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#include <asm/cpu.h>
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int kvm_update_cpuid(struct kvm_vcpu *vcpu);
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struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
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@ -178,4 +179,37 @@ static inline bool guest_cpuid_has_nrips(struct kvm_vcpu *vcpu)
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}
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#undef BIT_NRIPS
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static inline int guest_cpuid_family(struct kvm_vcpu *vcpu)
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{
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struct kvm_cpuid_entry2 *best;
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best = kvm_find_cpuid_entry(vcpu, 0x1, 0);
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if (!best)
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return -1;
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return x86_family(best->eax);
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}
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static inline int guest_cpuid_model(struct kvm_vcpu *vcpu)
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{
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struct kvm_cpuid_entry2 *best;
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best = kvm_find_cpuid_entry(vcpu, 0x1, 0);
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if (!best)
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return -1;
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return x86_model(best->eax);
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}
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static inline int guest_cpuid_stepping(struct kvm_vcpu *vcpu)
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{
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struct kvm_cpuid_entry2 *best;
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best = kvm_find_cpuid_entry(vcpu, 0x1, 0);
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if (!best)
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return -1;
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return x86_stepping(best->eax);
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}
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#endif
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@ -3053,6 +3053,23 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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case MSR_IA32_UCODE_REV:
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msr_info->data = 0x01000065;
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break;
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case MSR_F15H_IC_CFG: {
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int family, model;
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family = guest_cpuid_family(vcpu);
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model = guest_cpuid_model(vcpu);
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if (family < 0 || model < 0)
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return kvm_get_msr_common(vcpu, msr_info);
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msr_info->data = 0;
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if (family == 0x15 &&
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(model >= 0x2 && model < 0x20))
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msr_info->data = 0x1E;
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}
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break;
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default:
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return kvm_get_msr_common(vcpu, msr_info);
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}
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@ -16,7 +16,7 @@ clean-files := inat-tables.c
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obj-$(CONFIG_SMP) += msr-smp.o cache-smp.o
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lib-y := delay.o misc.o cmdline.o
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lib-y := delay.o misc.o cmdline.o cpu.o
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lib-y += usercopy_$(BITS).o usercopy.o getuser.o putuser.o
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lib-y += memcpy_$(BITS).o
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lib-$(CONFIG_RWSEM_XCHGADD_ALGORITHM) += rwsem.o
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35
arch/x86/lib/cpu.c
Normal file
35
arch/x86/lib/cpu.c
Normal file
@ -0,0 +1,35 @@
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#include <linux/module.h>
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unsigned int x86_family(unsigned int sig)
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{
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unsigned int x86;
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x86 = (sig >> 8) & 0xf;
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if (x86 == 0xf)
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x86 += (sig >> 20) & 0xff;
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return x86;
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}
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EXPORT_SYMBOL_GPL(x86_family);
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unsigned int x86_model(unsigned int sig)
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{
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unsigned int fam, model;
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fam = x86_family(sig);
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model = (sig >> 4) & 0xf;
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if (fam >= 0x6)
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model += ((sig >> 16) & 0xf) << 4;
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return model;
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}
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EXPORT_SYMBOL_GPL(x86_model);
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unsigned int x86_stepping(unsigned int sig)
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{
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return sig & 0xf;
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}
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EXPORT_SYMBOL_GPL(x86_stepping);
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