FEX-Emu/linux
1
0
Fork 0
mirror of https://github.com/FEX-Emu/linux.git synced 2024-12-30 05:15:03 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Exporting clocks for MIPI DSI DPHY and the display PLL

Browse Source 
frequency list update for Exynos5433 SoC.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABCAAGBQJYiydyAAoJEE1bIKeAnHqLxkoP/2qfduAcS+pBwXjOFXgJgPnt
 l/2EHO6CAGsCDh2fW1CfpfB4DvHNoHLvtt5YrtIznzuYL3pIcZTGKoPICsVZnMG8
 7q+0/ijU98VRj0g5zXL1UglHvQRiiHVHNhzGNmPJPT6mqayaoxRVYyUkDKd04Kkk
 doUR08Zxk4vqU6dr1F699DR3LVNMmc2XDVyHIJX23l3rQF2vB5yLTbMgSmxhNc2O
 p7GWN3Vm307V+L6KYpSafNPGxdbzRAdqL6aHciOk9rPBRzE0pVU3rrQpSXfZnUVm
 9FkjoeI0VwQYaEgZmXn5QbarqBKlBHfFpKtgg4Yf9HcygecZFf1nhW0yIbEaev20
 TrmktOXNe5kchjTWJK0MlYc0Elj/r2/Kq0WHJhlukWWcZ+RAfGvrXz8C2jTjmAoB
 UzCY3PciXUmgrdEiBpIuu64lmQGW+zOHlaTb9WLW4xAU9wum5rN2P2G9PJytetYU
 ToZJXrYNKD36MzioiLPngUmqYJJj+208SjaIbCEHB38clP4TROp7iNzvBLKrS/2E
 kvlBzCjxLP799Tn0Rzbc4KY24+L+2sbCmpfJ0gcyzU0eqw8ib42Zwb6wAHnOb3hz
 ffT5q4wZEvVG/RydzYoqJYRvxabZN2PmYlGtvyRozTYAL5irhHYGx1ZK6m0SZJUM
 uB8i9oXIaJ8rDIKUO2RL
 =F8PS
 -----END PGP SIGNATURE-----

Merge tag 'clk-v4.11-samsung-dphy' of git://linuxtv.org/snawrocki/samsung into next/dt64

Exporting clocks for MIPI DSI DPHY and the display PLL
frequency list update for Exynos5433 SoC.
This commit is contained in:
Krzysztof Kozlowski 2017-01-31 21:36:52 +02:00
commit 67707c78f5
2 changed files with 10 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/clk/samsung/clk-exynos5433.c
View File

@ -739,7 +739,9 @@ static const struct samsung_pll_rate_table exynos5443_pll_rates[] __initconst =
PLL_35XX_RATE(350000000U, 350, 6, 2),
PLL_35XX_RATE(333000000U, 222, 4, 2),
PLL_35XX_RATE(300000000U, 500, 5, 3),
PLL_35XX_RATE(278000000U, 556, 6, 3),
PLL_35XX_RATE(266000000U, 532, 6, 3),
PLL_35XX_RATE(250000000U, 500, 6, 3),
PLL_35XX_RATE(200000000U, 400, 6, 3),
PLL_35XX_RATE(166000000U, 332, 6, 3),
PLL_35XX_RATE(160000000U, 320, 6, 3),
@ -2559,8 +2561,10 @@ static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = {
FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000),
FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000),
/* PHY clocks from MIPI_DPHY0 */
FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, 0, 188000000),
FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, 0, 100000000),
FRATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, "phyclk_mipidphy0_bitclkdiv8_phy",
NULL, 0, 188000000),
FRATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, "phyclk_mipidphy0_rxclkesc0_phy",
NULL, 0, 100000000),
/* PHY clocks from HDMI_PHY */
FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy",
NULL, 0, 300000000),

5
include/dt-bindings/clock/exynos5433.h
View File

@ -771,7 +771,10 @@
#define CLK_PCLK_DECON 113
#define DISP_NR_CLK 114
#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY 114
#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY 115
#define DISP_NR_CLK 116
/* CMU_AUD */
#define CLK_MOUT_AUD_PLL_USER 1