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[TG3]: Fix low power state
Fix the following bugs in tg3_set_power_state(): 1. Both WOL and ASF flags require switching to aux power. 2. Add a missing handshake with firmware to enable WOL. 3. Turn off the PHY if both WOL and ASF are disabled. 4. Add nvram arbitration before halting the firmware. 5. Fix tg3_setup_copper_phy() to switch to 100Mbps when changing to low power state. Update revision and date. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -68,8 +68,8 @@
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#define DRV_MODULE_NAME "tg3"
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#define PFX DRV_MODULE_NAME ": "
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#define DRV_MODULE_VERSION "3.44"
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#define DRV_MODULE_RELDATE "Dec 6, 2005"
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#define DRV_MODULE_VERSION "3.45"
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#define DRV_MODULE_RELDATE "Dec 13, 2005"
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#define TG3_DEF_MAC_MODE 0
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#define TG3_DEF_RX_MODE 0
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@ -1025,7 +1025,9 @@ static void tg3_frob_aux_power(struct tg3 *tp)
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if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
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(tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0) {
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(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
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(tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
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(tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
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tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
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@ -1105,6 +1107,8 @@ static int tg3_setup_phy(struct tg3 *, int);
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static void tg3_write_sig_post_reset(struct tg3 *, int);
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static int tg3_halt_cpu(struct tg3 *, u32);
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static int tg3_nvram_lock(struct tg3 *);
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static void tg3_nvram_unlock(struct tg3 *);
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static int tg3_set_power_state(struct tg3 *tp, int state)
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{
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@ -1179,6 +1183,21 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
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tg3_setup_phy(tp, 0);
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}
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if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
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int i;
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u32 val;
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for (i = 0; i < 200; i++) {
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tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
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if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
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break;
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msleep(1);
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}
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}
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tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
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WOL_DRV_STATE_SHUTDOWN |
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WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
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pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
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if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
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@ -1268,6 +1287,17 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
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}
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}
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if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
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!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
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/* Turn off the PHY */
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if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
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tg3_writephy(tp, MII_TG3_EXT_CTRL,
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MII_TG3_EXT_CTRL_FORCE_LED_OFF);
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
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tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
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}
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}
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tg3_frob_aux_power(tp);
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/* Workaround for unstable PLL clock */
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@ -1277,8 +1307,12 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
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val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
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tw32(0x7d00, val);
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if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
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if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
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tg3_nvram_lock(tp);
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tg3_halt_cpu(tp, RX_CPU_BASE);
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tw32_f(NVRAM_SWARB, SWARB_REQ_CLR0);
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tg3_nvram_unlock(tp);
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}
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}
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/* Finally, set the new power state. */
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@ -1812,7 +1846,7 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
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}
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}
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relink:
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if (current_link_up == 0) {
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if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
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u32 tmp;
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tg3_phy_copper_begin(tp);
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@ -1529,6 +1529,12 @@
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#define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14
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#define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18
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#define NIC_SRAM_WOL_MBOX 0x00000d30
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#define WOL_SIGNATURE 0x474c0000
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#define WOL_DRV_STATE_SHUTDOWN 0x00000001
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#define WOL_DRV_WOL 0x00000002
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#define WOL_SET_MAGIC_PKT 0x00000004
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#define NIC_SRAM_DATA_CFG_2 0x00000d38
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#define SHASTA_EXT_LED_MODE_MASK 0x00018000
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@ -1565,6 +1571,7 @@
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#define MII_TG3_EXT_CTRL 0x10 /* Extended control register */
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#define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001
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#define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
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#define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008
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#define MII_TG3_EXT_CTRL_TBI 0x8000
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#define MII_TG3_EXT_STAT 0x11 /* Extended status register */
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