mirror of
https://github.com/FEX-Emu/linux.git
synced 2024-12-14 04:41:26 +00:00
Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull perf fixes from Ingo Molnar: "Most of the kernel diffstat relates to a group of Intel P6 and KNC (Xeon-Phi Knights Corner) PMU driver fixes, neither of which is in heavy use, so we took the fixes. The rest is diverse smallish fixes to the tooling and kernel side." * 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: perf/x86: Remove unused variable in nhmex_rbox_alter_er() perf/x86: Enable overflow on Intel KNC with a custom knc_pmu_handle_irq() perf/x86: Remove cpuc->enable check on Intl KNC event enable/disable perf/x86: Make Intel KNC use full 40-bit width of counters perf/x86/uncore: Handle pci_read_config_dword() errors perf/x86: Remove P6 cpuc->enabled check perf/x86: Update/fix generic events on P6 PMU perf/x86: Fix P6 FP_ASSIST event constraint perf, cpu hotplug: Use cached value of smp_processor_id() perf, cpu hotplug: Run CPU_STARTING notifiers with irqs disabled x86/perf: Fix virtualization sanity check perf test: Fix exclude_guest parse events tests perf tools: do not flush maps on COMM for perf report perf help: Fix --help for builtins perf trace: Check if sample raw_data field is set perf trace: Validate syscall id before growing syscall table
This commit is contained in:
Linus Torvalds
commit
6a2e52f844
@ -208,12 +208,14 @@ static bool check_hw_exists(void)
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}
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/*
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* Now write a value and read it back to see if it matches,
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* this is needed to detect certain hardware emulators (qemu/kvm)
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* that don't trap on the MSR access and always return 0s.
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* Read the current value, change it and read it back to see if it
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* matches, this is needed to detect certain hardware emulators
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* (qemu/kvm) that don't trap on the MSR access and always return 0s.
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*/
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val = 0xabcdUL;
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reg = x86_pmu_event_addr(0);
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if (rdmsrl_safe(reg, &val))
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goto msr_fail;
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val ^= 0xffffUL;
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ret = wrmsrl_safe(reg, val);
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ret |= rdmsrl_safe(reg, &val_new);
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if (ret || val != val_new)
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@ -118,22 +118,24 @@ static void snbep_uncore_pci_disable_box(struct intel_uncore_box *box)
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{
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struct pci_dev *pdev = box->pci_dev;
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int box_ctl = uncore_pci_box_ctl(box);
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u32 config;
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u32 config = 0;
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pci_read_config_dword(pdev, box_ctl, &config);
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config |= SNBEP_PMON_BOX_CTL_FRZ;
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pci_write_config_dword(pdev, box_ctl, config);
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if (!pci_read_config_dword(pdev, box_ctl, &config)) {
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config |= SNBEP_PMON_BOX_CTL_FRZ;
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pci_write_config_dword(pdev, box_ctl, config);
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}
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}
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static void snbep_uncore_pci_enable_box(struct intel_uncore_box *box)
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{
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struct pci_dev *pdev = box->pci_dev;
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int box_ctl = uncore_pci_box_ctl(box);
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u32 config;
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u32 config = 0;
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pci_read_config_dword(pdev, box_ctl, &config);
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config &= ~SNBEP_PMON_BOX_CTL_FRZ;
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pci_write_config_dword(pdev, box_ctl, config);
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if (!pci_read_config_dword(pdev, box_ctl, &config)) {
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config &= ~SNBEP_PMON_BOX_CTL_FRZ;
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pci_write_config_dword(pdev, box_ctl, config);
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}
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}
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static void snbep_uncore_pci_enable_event(struct intel_uncore_box *box, struct perf_event *event)
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@ -156,7 +158,7 @@ static u64 snbep_uncore_pci_read_counter(struct intel_uncore_box *box, struct pe
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{
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struct pci_dev *pdev = box->pci_dev;
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struct hw_perf_event *hwc = &event->hw;
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u64 count;
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u64 count = 0;
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pci_read_config_dword(pdev, hwc->event_base, (u32 *)&count);
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pci_read_config_dword(pdev, hwc->event_base + 4, (u32 *)&count + 1);
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@ -603,11 +605,12 @@ static struct pci_driver snbep_uncore_pci_driver = {
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/*
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* build pci bus to socket mapping
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*/
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static void snbep_pci2phy_map_init(void)
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static int snbep_pci2phy_map_init(void)
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{
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struct pci_dev *ubox_dev = NULL;
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int i, bus, nodeid;
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u32 config;
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int err = 0;
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u32 config = 0;
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while (1) {
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/* find the UBOX device */
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@ -618,10 +621,14 @@ static void snbep_pci2phy_map_init(void)
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break;
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bus = ubox_dev->bus->number;
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/* get the Node ID of the local register */
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pci_read_config_dword(ubox_dev, 0x40, &config);
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err = pci_read_config_dword(ubox_dev, 0x40, &config);
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if (err)
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break;
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nodeid = config;
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/* get the Node ID mapping */
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pci_read_config_dword(ubox_dev, 0x54, &config);
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err = pci_read_config_dword(ubox_dev, 0x54, &config);
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if (err)
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break;
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/*
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* every three bits in the Node ID mapping register maps
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* to a particular node.
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@ -633,7 +640,11 @@ static void snbep_pci2phy_map_init(void)
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}
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}
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};
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return;
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if (ubox_dev)
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pci_dev_put(ubox_dev);
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return err ? pcibios_err_to_errno(err) : 0;
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}
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/* end of Sandy Bridge-EP uncore support */
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@ -1547,7 +1558,6 @@ void nhmex_rbox_alter_er(struct intel_uncore_box *box, struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
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int port;
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/* adjust the main event selector and extra register index */
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if (reg1->idx % 2) {
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@ -1559,7 +1569,6 @@ void nhmex_rbox_alter_er(struct intel_uncore_box *box, struct perf_event *event)
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}
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/* adjust extra register config */
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port = reg1->idx / 6 + box->pmu->pmu_idx * 4;
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switch (reg1->idx % 6) {
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case 2:
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/* shift the 8~15 bits to the 0~7 bits */
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@ -2578,9 +2587,11 @@ static int __init uncore_pci_init(void)
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switch (boot_cpu_data.x86_model) {
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case 45: /* Sandy Bridge-EP */
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ret = snbep_pci2phy_map_init();
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if (ret)
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return ret;
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pci_uncores = snbep_pci_uncores;
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uncore_pci_driver = &snbep_uncore_pci_driver;
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snbep_pci2phy_map_init();
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break;
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default:
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return 0;
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@ -3,6 +3,8 @@
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#include <linux/perf_event.h>
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#include <linux/types.h>
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#include <asm/hardirq.h>
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#include "perf_event.h"
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static const u64 knc_perfmon_event_map[] =
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@ -173,30 +175,100 @@ static void knc_pmu_enable_all(int added)
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static inline void
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knc_pmu_disable_event(struct perf_event *event)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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struct hw_perf_event *hwc = &event->hw;
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u64 val;
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val = hwc->config;
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if (cpuc->enabled)
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val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
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val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
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(void)wrmsrl_safe(hwc->config_base + hwc->idx, val);
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}
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static void knc_pmu_enable_event(struct perf_event *event)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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struct hw_perf_event *hwc = &event->hw;
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u64 val;
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val = hwc->config;
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if (cpuc->enabled)
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val |= ARCH_PERFMON_EVENTSEL_ENABLE;
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val |= ARCH_PERFMON_EVENTSEL_ENABLE;
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(void)wrmsrl_safe(hwc->config_base + hwc->idx, val);
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}
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static inline u64 knc_pmu_get_status(void)
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{
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u64 status;
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rdmsrl(MSR_KNC_IA32_PERF_GLOBAL_STATUS, status);
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return status;
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}
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static inline void knc_pmu_ack_status(u64 ack)
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{
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wrmsrl(MSR_KNC_IA32_PERF_GLOBAL_OVF_CONTROL, ack);
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}
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static int knc_pmu_handle_irq(struct pt_regs *regs)
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{
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struct perf_sample_data data;
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struct cpu_hw_events *cpuc;
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int handled = 0;
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int bit, loops;
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u64 status;
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cpuc = &__get_cpu_var(cpu_hw_events);
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knc_pmu_disable_all();
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status = knc_pmu_get_status();
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if (!status) {
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knc_pmu_enable_all(0);
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return handled;
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}
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loops = 0;
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again:
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knc_pmu_ack_status(status);
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if (++loops > 100) {
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WARN_ONCE(1, "perf: irq loop stuck!\n");
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perf_event_print_debug();
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goto done;
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}
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inc_irq_stat(apic_perf_irqs);
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for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
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struct perf_event *event = cpuc->events[bit];
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handled++;
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if (!test_bit(bit, cpuc->active_mask))
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continue;
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if (!intel_pmu_save_and_restart(event))
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continue;
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perf_sample_data_init(&data, 0, event->hw.last_period);
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if (perf_event_overflow(event, &data, regs))
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x86_pmu_stop(event, 0);
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}
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/*
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* Repeat if there is more work to be done:
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*/
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status = knc_pmu_get_status();
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if (status)
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goto again;
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done:
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knc_pmu_enable_all(0);
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return handled;
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}
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PMU_FORMAT_ATTR(event, "config:0-7" );
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PMU_FORMAT_ATTR(umask, "config:8-15" );
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PMU_FORMAT_ATTR(edge, "config:18" );
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@ -214,7 +286,7 @@ static struct attribute *intel_knc_formats_attr[] = {
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static __initconst struct x86_pmu knc_pmu = {
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.name = "knc",
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.handle_irq = x86_pmu_handle_irq,
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.handle_irq = knc_pmu_handle_irq,
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.disable_all = knc_pmu_disable_all,
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.enable_all = knc_pmu_enable_all,
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.enable = knc_pmu_enable_event,
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@ -226,12 +298,11 @@ static __initconst struct x86_pmu knc_pmu = {
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.event_map = knc_pmu_event_map,
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.max_events = ARRAY_SIZE(knc_perfmon_event_map),
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.apic = 1,
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.max_period = (1ULL << 31) - 1,
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.max_period = (1ULL << 39) - 1,
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.version = 0,
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.num_counters = 2,
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/* in theory 40 bits, early silicon is buggy though */
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.cntval_bits = 32,
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.cntval_mask = (1ULL << 32) - 1,
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.cntval_bits = 40,
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.cntval_mask = (1ULL << 40) - 1,
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.get_event_constraints = x86_get_event_constraints,
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.event_constraints = knc_event_constraints,
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.format_attrs = intel_knc_formats_attr,
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@ -8,13 +8,106 @@
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*/
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static const u64 p6_perfmon_event_map[] =
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{
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[PERF_COUNT_HW_CPU_CYCLES] = 0x0079,
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[PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
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[PERF_COUNT_HW_CACHE_REFERENCES] = 0x0f2e,
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[PERF_COUNT_HW_CACHE_MISSES] = 0x012e,
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
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[PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
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[PERF_COUNT_HW_BUS_CYCLES] = 0x0062,
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[PERF_COUNT_HW_CPU_CYCLES] = 0x0079, /* CPU_CLK_UNHALTED */
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[PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, /* INST_RETIRED */
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[PERF_COUNT_HW_CACHE_REFERENCES] = 0x0f2e, /* L2_RQSTS:M:E:S:I */
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[PERF_COUNT_HW_CACHE_MISSES] = 0x012e, /* L2_RQSTS:I */
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, /* BR_INST_RETIRED */
|
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[PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, /* BR_MISS_PRED_RETIRED */
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[PERF_COUNT_HW_BUS_CYCLES] = 0x0062, /* BUS_DRDY_CLOCKS */
|
||||
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a2, /* RESOURCE_STALLS */
|
||||
|
||||
};
|
||||
|
||||
static __initconst u64 p6_hw_cache_event_ids
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||||
[PERF_COUNT_HW_CACHE_MAX]
|
||||
[PERF_COUNT_HW_CACHE_OP_MAX]
|
||||
[PERF_COUNT_HW_CACHE_RESULT_MAX] =
|
||||
{
|
||||
[ C(L1D) ] = {
|
||||
[ C(OP_READ) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0x0043, /* DATA_MEM_REFS */
|
||||
[ C(RESULT_MISS) ] = 0x0045, /* DCU_LINES_IN */
|
||||
},
|
||||
[ C(OP_WRITE) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0,
|
||||
[ C(RESULT_MISS) ] = 0x0f29, /* L2_LD:M:E:S:I */
|
||||
},
|
||||
[ C(OP_PREFETCH) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0,
|
||||
[ C(RESULT_MISS) ] = 0,
|
||||
},
|
||||
},
|
||||
[ C(L1I ) ] = {
|
||||
[ C(OP_READ) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0x0080, /* IFU_IFETCH */
|
||||
[ C(RESULT_MISS) ] = 0x0f28, /* L2_IFETCH:M:E:S:I */
|
||||
},
|
||||
[ C(OP_WRITE) ] = {
|
||||
[ C(RESULT_ACCESS) ] = -1,
|
||||
[ C(RESULT_MISS) ] = -1,
|
||||
},
|
||||
[ C(OP_PREFETCH) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0,
|
||||
[ C(RESULT_MISS) ] = 0,
|
||||
},
|
||||
},
|
||||
[ C(LL ) ] = {
|
||||
[ C(OP_READ) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0,
|
||||
[ C(RESULT_MISS) ] = 0,
|
||||
},
|
||||
[ C(OP_WRITE) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0,
|
||||
[ C(RESULT_MISS) ] = 0x0025, /* L2_M_LINES_INM */
|
||||
},
|
||||
[ C(OP_PREFETCH) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0,
|
||||
[ C(RESULT_MISS) ] = 0,
|
||||
},
|
||||
},
|
||||
[ C(DTLB) ] = {
|
||||
[ C(OP_READ) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0x0043, /* DATA_MEM_REFS */
|
||||
[ C(RESULT_MISS) ] = 0,
|
||||
},
|
||||
[ C(OP_WRITE) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0,
|
||||
[ C(RESULT_MISS) ] = 0,
|
||||
},
|
||||
[ C(OP_PREFETCH) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0,
|
||||
[ C(RESULT_MISS) ] = 0,
|
||||
},
|
||||
},
|
||||
[ C(ITLB) ] = {
|
||||
[ C(OP_READ) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0x0080, /* IFU_IFETCH */
|
||||
[ C(RESULT_MISS) ] = 0x0085, /* ITLB_MISS */
|
||||
},
|
||||
[ C(OP_WRITE) ] = {
|
||||
[ C(RESULT_ACCESS) ] = -1,
|
||||
[ C(RESULT_MISS) ] = -1,
|
||||
},
|
||||
[ C(OP_PREFETCH) ] = {
|
||||
[ C(RESULT_ACCESS) ] = -1,
|
||||
[ C(RESULT_MISS) ] = -1,
|
||||
},
|
||||
},
|
||||
[ C(BPU ) ] = {
|
||||
[ C(OP_READ) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED */
|
||||
[ C(RESULT_MISS) ] = 0x00c5, /* BR_MISS_PRED_RETIRED */
|
||||
},
|
||||
[ C(OP_WRITE) ] = {
|
||||
[ C(RESULT_ACCESS) ] = -1,
|
||||
[ C(RESULT_MISS) ] = -1,
|
||||
},
|
||||
[ C(OP_PREFETCH) ] = {
|
||||
[ C(RESULT_ACCESS) ] = -1,
|
||||
[ C(RESULT_MISS) ] = -1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static u64 p6_pmu_event_map(int hw_event)
|
||||
@ -34,7 +127,7 @@ static struct event_constraint p6_event_constraints[] =
|
||||
{
|
||||
INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FLOPS */
|
||||
INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
|
||||
INTEL_EVENT_CONSTRAINT(0x11, 0x1), /* FP_ASSIST */
|
||||
INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
|
||||
INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
|
||||
INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
|
||||
INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
|
||||
@ -64,25 +157,25 @@ static void p6_pmu_enable_all(int added)
|
||||
static inline void
|
||||
p6_pmu_disable_event(struct perf_event *event)
|
||||
{
|
||||
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
u64 val = P6_NOP_EVENT;
|
||||
|
||||
if (cpuc->enabled)
|
||||
val |= ARCH_PERFMON_EVENTSEL_ENABLE;
|
||||
|
||||
(void)wrmsrl_safe(hwc->config_base, val);
|
||||
}
|
||||
|
||||
static void p6_pmu_enable_event(struct perf_event *event)
|
||||
{
|
||||
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
u64 val;
|
||||
|
||||
val = hwc->config;
|
||||
if (cpuc->enabled)
|
||||
val |= ARCH_PERFMON_EVENTSEL_ENABLE;
|
||||
|
||||
/*
|
||||
* p6 only has a global event enable, set on PerfEvtSel0
|
||||
* We "disable" events by programming P6_NOP_EVENT
|
||||
* and we rely on p6_pmu_enable_all() being called
|
||||
* to actually enable the events.
|
||||
*/
|
||||
|
||||
(void)wrmsrl_safe(hwc->config_base, val);
|
||||
}
|
||||
@ -158,5 +251,9 @@ __init int p6_pmu_init(void)
|
||||
|
||||
x86_pmu = p6_pmu;
|
||||
|
||||
memcpy(hw_cache_event_ids, p6_hw_cache_event_ids,
|
||||
sizeof(hw_cache_event_ids));
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -803,12 +803,16 @@ static inline void perf_event_task_tick(void) { }
|
||||
do { \
|
||||
static struct notifier_block fn##_nb __cpuinitdata = \
|
||||
{ .notifier_call = fn, .priority = CPU_PRI_PERF }; \
|
||||
unsigned long cpu = smp_processor_id(); \
|
||||
unsigned long flags; \
|
||||
fn(&fn##_nb, (unsigned long)CPU_UP_PREPARE, \
|
||||
(void *)(unsigned long)smp_processor_id()); \
|
||||
(void *)(unsigned long)cpu); \
|
||||
local_irq_save(flags); \
|
||||
fn(&fn##_nb, (unsigned long)CPU_STARTING, \
|
||||
(void *)(unsigned long)smp_processor_id()); \
|
||||
(void *)(unsigned long)cpu); \
|
||||
local_irq_restore(flags); \
|
||||
fn(&fn##_nb, (unsigned long)CPU_ONLINE, \
|
||||
(void *)(unsigned long)smp_processor_id()); \
|
||||
(void *)(unsigned long)cpu); \
|
||||
register_cpu_notifier(&fn##_nb); \
|
||||
} while (0)
|
||||
|
||||
|
||||
@ -414,7 +414,7 @@ static int show_html_page(const char *perf_cmd)
|
||||
int cmd_help(int argc, const char **argv, const char *prefix __maybe_unused)
|
||||
{
|
||||
bool show_all = false;
|
||||
enum help_format help_format = HELP_FORMAT_NONE;
|
||||
enum help_format help_format = HELP_FORMAT_MAN;
|
||||
struct option builtin_help_options[] = {
|
||||
OPT_BOOLEAN('a', "all", &show_all, "print all available commands"),
|
||||
OPT_SET_UINT('m', "man", &help_format, "show man page", HELP_FORMAT_MAN),
|
||||
|
||||
@ -56,6 +56,10 @@ static int trace__read_syscall_info(struct trace *trace, int id)
|
||||
{
|
||||
char tp_name[128];
|
||||
struct syscall *sc;
|
||||
const char *name = audit_syscall_to_name(id, trace->audit_machine);
|
||||
|
||||
if (name == NULL)
|
||||
return -1;
|
||||
|
||||
if (id > trace->syscalls.max) {
|
||||
struct syscall *nsyscalls = realloc(trace->syscalls.table, (id + 1) * sizeof(*sc));
|
||||
@ -75,11 +79,8 @@ static int trace__read_syscall_info(struct trace *trace, int id)
|
||||
}
|
||||
|
||||
sc = trace->syscalls.table + id;
|
||||
sc->name = audit_syscall_to_name(id, trace->audit_machine);
|
||||
if (sc->name == NULL)
|
||||
return -1;
|
||||
|
||||
sc->fmt = syscall_fmt__find(sc->name);
|
||||
sc->name = name;
|
||||
sc->fmt = syscall_fmt__find(sc->name);
|
||||
|
||||
snprintf(tp_name, sizeof(tp_name), "sys_enter_%s", sc->name);
|
||||
sc->tp_format = event_format__new("syscalls", tp_name);
|
||||
@ -267,6 +268,13 @@ again:
|
||||
if (evlist->threads->map[0] == -1 || evlist->threads->nr > 1)
|
||||
printf("%d ", sample.tid);
|
||||
|
||||
if (sample.raw_data == NULL) {
|
||||
printf("%s sample with no payload for tid: %d, cpu %d, raw_size=%d, skipping...\n",
|
||||
perf_evsel__name(evsel), sample.tid,
|
||||
sample.cpu, sample.raw_size);
|
||||
continue;
|
||||
}
|
||||
|
||||
handler = evsel->handler.func;
|
||||
handler(trace, evsel, &sample);
|
||||
}
|
||||
|
||||
@ -513,7 +513,8 @@ static int test__group1(struct perf_evlist *evlist)
|
||||
TEST_ASSERT_VAL("wrong exclude_user", !evsel->attr.exclude_user);
|
||||
TEST_ASSERT_VAL("wrong exclude_kernel", evsel->attr.exclude_kernel);
|
||||
TEST_ASSERT_VAL("wrong exclude_hv", evsel->attr.exclude_hv);
|
||||
TEST_ASSERT_VAL("wrong exclude guest", !evsel->attr.exclude_guest);
|
||||
/* use of precise requires exclude_guest */
|
||||
TEST_ASSERT_VAL("wrong exclude guest", evsel->attr.exclude_guest);
|
||||
TEST_ASSERT_VAL("wrong exclude host", !evsel->attr.exclude_host);
|
||||
TEST_ASSERT_VAL("wrong precise_ip", evsel->attr.precise_ip == 2);
|
||||
TEST_ASSERT_VAL("wrong leader", evsel->leader == leader);
|
||||
@ -599,7 +600,8 @@ static int test__group3(struct perf_evlist *evlist __maybe_unused)
|
||||
TEST_ASSERT_VAL("wrong exclude_user", evsel->attr.exclude_user);
|
||||
TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->attr.exclude_kernel);
|
||||
TEST_ASSERT_VAL("wrong exclude_hv", evsel->attr.exclude_hv);
|
||||
TEST_ASSERT_VAL("wrong exclude guest", !evsel->attr.exclude_guest);
|
||||
/* use of precise requires exclude_guest */
|
||||
TEST_ASSERT_VAL("wrong exclude guest", evsel->attr.exclude_guest);
|
||||
TEST_ASSERT_VAL("wrong exclude host", !evsel->attr.exclude_host);
|
||||
TEST_ASSERT_VAL("wrong precise_ip", evsel->attr.precise_ip == 3);
|
||||
TEST_ASSERT_VAL("wrong leader", evsel->leader == leader);
|
||||
@ -662,7 +664,8 @@ static int test__group4(struct perf_evlist *evlist __maybe_unused)
|
||||
TEST_ASSERT_VAL("wrong exclude_user", !evsel->attr.exclude_user);
|
||||
TEST_ASSERT_VAL("wrong exclude_kernel", evsel->attr.exclude_kernel);
|
||||
TEST_ASSERT_VAL("wrong exclude_hv", evsel->attr.exclude_hv);
|
||||
TEST_ASSERT_VAL("wrong exclude guest", !evsel->attr.exclude_guest);
|
||||
/* use of precise requires exclude_guest */
|
||||
TEST_ASSERT_VAL("wrong exclude guest", evsel->attr.exclude_guest);
|
||||
TEST_ASSERT_VAL("wrong exclude host", !evsel->attr.exclude_host);
|
||||
TEST_ASSERT_VAL("wrong precise_ip", evsel->attr.precise_ip == 1);
|
||||
TEST_ASSERT_VAL("wrong group name", !evsel->group_name);
|
||||
@ -676,7 +679,8 @@ static int test__group4(struct perf_evlist *evlist __maybe_unused)
|
||||
TEST_ASSERT_VAL("wrong exclude_user", evsel->attr.exclude_user);
|
||||
TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->attr.exclude_kernel);
|
||||
TEST_ASSERT_VAL("wrong exclude_hv", evsel->attr.exclude_hv);
|
||||
TEST_ASSERT_VAL("wrong exclude guest", !evsel->attr.exclude_guest);
|
||||
/* use of precise requires exclude_guest */
|
||||
TEST_ASSERT_VAL("wrong exclude guest", evsel->attr.exclude_guest);
|
||||
TEST_ASSERT_VAL("wrong exclude host", !evsel->attr.exclude_host);
|
||||
TEST_ASSERT_VAL("wrong precise_ip", evsel->attr.precise_ip == 2);
|
||||
TEST_ASSERT_VAL("wrong leader", evsel->leader == leader);
|
||||
|
||||
@ -39,7 +39,6 @@ int thread__set_comm(struct thread *self, const char *comm)
|
||||
err = self->comm == NULL ? -ENOMEM : 0;
|
||||
if (!err) {
|
||||
self->comm_set = true;
|
||||
map_groups__flush(&self->mg);
|
||||
}
|
||||
return err;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user