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[media] davinci: vpfe: dm365: add ISIF driver based on media framework
add support for ISIF as a subdevice for dm365 vpfe capture driver. ISIF is responsible for capturing video data both in raw bayer format on sync seperate signals and YUV through BT656/1120 interfaces. ISIF is exposed as a subdev for the vpfe driver and allows users to use the driver through standard media controller interface. Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com> Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Sakari Ailus <sakari.ailus@iki.fi> Acked-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Manjunath Hadli
Mauro Carvalho Chehab
parent
f7fa454dc1
commit
6a630533c4
2104
drivers/staging/media/davinci_vpfe/dm365_isif.c
Normal file
2104
drivers/staging/media/davinci_vpfe/dm365_isif.c
Normal file
File diff suppressed because it is too large
Load Diff
203
drivers/staging/media/davinci_vpfe/dm365_isif.h
Normal file
203
drivers/staging/media/davinci_vpfe/dm365_isif.h
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@ -0,0 +1,203 @@
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/*
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* Copyright (C) 2012 Texas Instruments Inc
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* Contributors:
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* Manjunath Hadli <manjunath.hadli@ti.com>
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* Prabhakar Lad <prabhakar.lad@ti.com>
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*/
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#ifndef _DAVINCI_VPFE_DM365_ISIF_H
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#define _DAVINCI_VPFE_DM365_ISIF_H
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#include <linux/platform_device.h>
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#include <mach/mux.h>
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#include <media/davinci/vpfe_types.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-device.h>
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#include "davinci_vpfe_user.h"
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#include "dm365_isif_regs.h"
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#include "vpfe_video.h"
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#define ISIF_CULLING_HCAPT_ODD 0xff
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#define ISIF_CULLING_HCAPT_EVEN 0xff
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#define ISIF_CULLING_VCAPT 0xff
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#define ISIF_CADU_BITS 0x07ff
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#define ISIF_CADL_BITS 0x0ffff
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enum isif_pixfmt {
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ISIF_PIXFMT_RAW = 0,
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ISIF_PIXFMT_YCBCR_16BIT = 1,
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ISIF_PIXFMT_YCBCR_8BIT = 2,
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};
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enum isif_frmfmt {
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ISIF_FRMFMT_PROGRESSIVE = 0,
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ISIF_FRMFMT_INTERLACED = 1,
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};
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/* PIXEL ORDER IN MEMORY from LSB to MSB */
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/* only applicable for 8-bit input mode */
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enum isif_pixorder {
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ISIF_PIXORDER_YCBYCR = 0,
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ISIF_PIXORDER_CBYCRY = 1,
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};
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enum isif_buftype {
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ISIF_BUFTYPE_FLD_INTERLEAVED = 0,
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ISIF_BUFTYPE_FLD_SEPARATED = 1,
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};
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struct isif_ycbcr_config {
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/* v4l2 pixel format */
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unsigned long v4l2_pix_fmt;
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/* isif pixel format */
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enum isif_pixfmt pix_fmt;
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/* isif frame format */
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enum isif_frmfmt frm_fmt;
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/* isif crop window */
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struct v4l2_rect win;
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/* field polarity */
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enum vpfe_pin_pol fid_pol;
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/* interface VD polarity */
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enum vpfe_pin_pol vd_pol;
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/* interface HD polarity */
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enum vpfe_pin_pol hd_pol;
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/* isif pix order. Only used for ycbcr capture */
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enum isif_pixorder pix_order;
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/* isif buffer type. Only used for ycbcr capture */
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enum isif_buftype buf_type;
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};
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enum isif_cfa_pattern {
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ISIF_CFA_PAT_MOSAIC = 0,
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ISIF_CFA_PAT_STRIPE = 1,
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};
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enum isif_data_msb {
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/* MSB b15 */
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ISIF_BIT_MSB_15 = 0,
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/* MSB b14 */
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ISIF_BIT_MSB_14 = 1,
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/* MSB b13 */
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ISIF_BIT_MSB_13 = 2,
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/* MSB b12 */
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ISIF_BIT_MSB_12 = 3,
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/* MSB b11 */
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ISIF_BIT_MSB_11 = 4,
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/* MSB b10 */
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ISIF_BIT_MSB_10 = 5,
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/* MSB b9 */
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ISIF_BIT_MSB_9 = 6,
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/* MSB b8 */
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ISIF_BIT_MSB_8 = 7,
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/* MSB b7 */
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ISIF_BIT_MSB_7 = 8,
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};
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struct isif_params_raw {
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/* v4l2 pixel format */
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unsigned long v4l2_pix_fmt;
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/* isif pixel format */
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enum isif_pixfmt pix_fmt;
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/* isif frame format */
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enum isif_frmfmt frm_fmt;
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/* video window */
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struct v4l2_rect win;
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/* field polarity */
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enum vpfe_pin_pol fid_pol;
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/* interface VD polarity */
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enum vpfe_pin_pol vd_pol;
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/* interface HD polarity */
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enum vpfe_pin_pol hd_pol;
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/* buffer type. Applicable for interlaced mode */
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enum isif_buftype buf_type;
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/* cfa pattern */
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enum isif_cfa_pattern cfa_pat;
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/* Data MSB position */
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enum isif_data_msb data_msb;
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/* Enable horizontal flip */
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unsigned char horz_flip_en;
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/* Enable image invert vertically */
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unsigned char image_invert_en;
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unsigned char dpcm_predictor;
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struct vpfe_isif_raw_config config_params;
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};
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enum isif_data_pack {
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ISIF_PACK_16BIT = 0,
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ISIF_PACK_12BIT = 1,
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ISIF_PACK_8BIT = 2,
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};
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struct isif_gain_values {
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unsigned int cr_gain;
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unsigned int cgr_gain;
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unsigned int cgb_gain;
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unsigned int cb_gain;
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unsigned int offset;
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};
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struct isif_oper_config {
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struct isif_ycbcr_config ycbcr;
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struct isif_params_raw bayer;
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enum isif_data_pack data_pack;
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struct isif_gain_values isif_gain_params;
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void *__iomem base_addr;
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void *__iomem linear_tbl0_addr;
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void *__iomem linear_tbl1_addr;
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};
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#define ISIF_PAD_SINK 0
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#define ISIF_PAD_SOURCE 1
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#define ISIF_PADS_NUM 2
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enum isif_input_entity {
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ISIF_INPUT_NONE = 0,
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ISIF_INPUT_PARALLEL = 1,
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};
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#define ISIF_OUTPUT_NONE (0)
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#define ISIF_OUTPUT_MEMORY (1 << 0)
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#define ISIF_OUTPUT_IPIPEIF (1 << 1)
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struct vpfe_isif_device {
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struct v4l2_subdev subdev;
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struct media_pad pads[ISIF_PADS_NUM];
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struct v4l2_mbus_framefmt formats[ISIF_PADS_NUM];
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enum isif_input_entity input;
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unsigned int output;
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struct v4l2_ctrl_handler ctrls;
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struct v4l2_rect crop;
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struct isif_oper_config isif_cfg;
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struct vpfe_video_device video_out;
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};
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enum v4l2_field vpfe_isif_get_fid(struct vpfe_device *vpfe_dev);
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void vpfe_isif_unregister_entities(struct vpfe_isif_device *isif);
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int vpfe_isif_register_entities(struct vpfe_isif_device *isif,
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struct v4l2_device *dev);
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int vpfe_isif_init(struct vpfe_isif_device *isif, struct platform_device *pdev);
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void vpfe_isif_cleanup(struct vpfe_isif_device *vpfe_isif,
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struct platform_device *pdev);
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void vpfe_isif_vidint1_isr(struct vpfe_isif_device *isif);
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void vpfe_isif_buffer_isr(struct vpfe_isif_device *isif);
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#endif /* _DAVINCI_VPFE_DM365_ISIF_H */
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294
drivers/staging/media/davinci_vpfe/dm365_isif_regs.h
Normal file
294
drivers/staging/media/davinci_vpfe/dm365_isif_regs.h
Normal file
@ -0,0 +1,294 @@
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/*
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* Copyright (C) 2012 Texas Instruments Inc
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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||||
* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* Contributors:
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* Manjunath Hadli <manjunath.hadli@ti.com>
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* Prabhakar Lad <prabhakar.lad@ti.com>
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*/
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#ifndef _DAVINCI_VPFE_DM365_ISIF_REGS_H
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#define _DAVINCI_VPFE_DM365_ISIF_REGS_H
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/* ISIF registers relative offsets */
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#define SYNCEN 0x00
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#define MODESET 0x04
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#define HDW 0x08
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#define VDW 0x0c
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#define PPLN 0x10
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#define LPFR 0x14
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#define SPH 0x18
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#define LNH 0x1c
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#define SLV0 0x20
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#define SLV1 0x24
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#define LNV 0x28
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#define CULH 0x2c
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#define CULV 0x30
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#define HSIZE 0x34
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#define SDOFST 0x38
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#define CADU 0x3c
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#define CADL 0x40
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#define LINCFG0 0x44
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#define LINCFG1 0x48
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#define CCOLP 0x4c
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#define CRGAIN 0x50
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#define CGRGAIN 0x54
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#define CGBGAIN 0x58
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#define CBGAIN 0x5c
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#define COFSTA 0x60
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#define FLSHCFG0 0x64
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#define FLSHCFG1 0x68
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#define FLSHCFG2 0x6c
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#define VDINT0 0x70
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#define VDINT1 0x74
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#define VDINT2 0x78
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#define MISC 0x7c
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#define CGAMMAWD 0x80
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#define REC656IF 0x84
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#define CCDCFG 0x88
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/*****************************************************
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* Defect Correction registers
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*****************************************************/
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#define DFCCTL 0x8c
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#define VDFSATLV 0x90
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#define DFCMEMCTL 0x94
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#define DFCMEM0 0x98
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#define DFCMEM1 0x9c
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#define DFCMEM2 0xa0
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#define DFCMEM3 0xa4
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#define DFCMEM4 0xa8
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/****************************************************
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* Black Clamp registers
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****************************************************/
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#define CLAMPCFG 0xac
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#define CLDCOFST 0xb0
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#define CLSV 0xb4
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#define CLHWIN0 0xb8
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#define CLHWIN1 0xbc
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#define CLHWIN2 0xc0
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#define CLVRV 0xc4
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#define CLVWIN0 0xc8
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#define CLVWIN1 0xcc
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#define CLVWIN2 0xd0
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#define CLVWIN3 0xd4
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/****************************************************
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* Lense Shading Correction
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****************************************************/
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#define DATAHOFST 0xd8
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#define DATAVOFST 0xdc
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#define LSCHVAL 0xe0
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#define LSCVVAL 0xe4
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#define TWODLSCCFG 0xe8
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#define TWODLSCOFST 0xec
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#define TWODLSCINI 0xf0
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#define TWODLSCGRBU 0xf4
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#define TWODLSCGRBL 0xf8
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#define TWODLSCGROF 0xfc
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#define TWODLSCORBU 0x100
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#define TWODLSCORBL 0x104
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#define TWODLSCOROF 0x108
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#define TWODLSCIRQEN 0x10c
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#define TWODLSCIRQST 0x110
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/****************************************************
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* Data formatter
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****************************************************/
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#define FMTCFG 0x114
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#define FMTPLEN 0x118
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#define FMTSPH 0x11c
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#define FMTLNH 0x120
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#define FMTSLV 0x124
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#define FMTLNV 0x128
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#define FMTRLEN 0x12c
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#define FMTHCNT 0x130
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#define FMTAPTR_BASE 0x134
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/* Below macro for addresses FMTAPTR0 - FMTAPTR15 */
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#define FMTAPTR(i) (FMTAPTR_BASE + (i * 4))
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#define FMTPGMVF0 0x174
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#define FMTPGMVF1 0x178
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#define FMTPGMAPU0 0x17c
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#define FMTPGMAPU1 0x180
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#define FMTPGMAPS0 0x184
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#define FMTPGMAPS1 0x188
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#define FMTPGMAPS2 0x18c
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#define FMTPGMAPS3 0x190
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#define FMTPGMAPS4 0x194
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#define FMTPGMAPS5 0x198
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#define FMTPGMAPS6 0x19c
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#define FMTPGMAPS7 0x1a0
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/************************************************
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* Color Space Converter
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************************************************/
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#define CSCCTL 0x1a4
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#define CSCM0 0x1a8
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#define CSCM1 0x1ac
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#define CSCM2 0x1b0
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#define CSCM3 0x1b4
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#define CSCM4 0x1b8
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#define CSCM5 0x1bc
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#define CSCM6 0x1c0
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#define CSCM7 0x1c4
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#define OBWIN0 0x1c8
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#define OBWIN1 0x1cc
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#define OBWIN2 0x1d0
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#define OBWIN3 0x1d4
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#define OBVAL0 0x1d8
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#define OBVAL1 0x1dc
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#define OBVAL2 0x1e0
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#define OBVAL3 0x1e4
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#define OBVAL4 0x1e8
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#define OBVAL5 0x1ec
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#define OBVAL6 0x1f0
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#define OBVAL7 0x1f4
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#define CLKCTL 0x1f8
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/* Masks & Shifts below */
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#define START_PX_HOR_MASK 0x7fff
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#define NUM_PX_HOR_MASK 0x7fff
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#define START_VER_ONE_MASK 0x7fff
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#define START_VER_TWO_MASK 0x7fff
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#define NUM_LINES_VER 0x7fff
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/* gain - offset masks */
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#define OFFSET_MASK 0xfff
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#define GAIN_SDRAM_EN_SHIFT 12
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#define GAIN_IPIPE_EN_SHIFT 13
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#define GAIN_H3A_EN_SHIFT 14
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#define OFST_SDRAM_EN_SHIFT 8
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#define OFST_IPIPE_EN_SHIFT 9
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#define OFST_H3A_EN_SHIFT 10
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#define GAIN_OFFSET_EN_MASK 0x7700
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/* Culling */
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#define CULL_PAT_EVEN_LINE_SHIFT 8
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/* CCDCFG register */
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#define ISIF_YCINSWP_RAW (0x00 << 4)
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#define ISIF_YCINSWP_YCBCR (0x01 << 4)
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#define ISIF_CCDCFG_FIDMD_LATCH_VSYNC (0x00 << 6)
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#define ISIF_CCDCFG_WENLOG_AND (0x00 << 8)
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#define ISIF_CCDCFG_TRGSEL_WEN (0x00 << 9)
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#define ISIF_CCDCFG_EXTRG_DISABLE (0x00 << 10)
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#define ISIF_LATCH_ON_VSYNC_DISABLE (0x01 << 15)
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#define ISIF_LATCH_ON_VSYNC_ENABLE (0x00 << 15)
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#define ISIF_DATA_PACK_MASK 0x03
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#define ISIF_PIX_ORDER_SHIFT 11
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#define ISIF_PIX_ORDER_MASK 0x01
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#define ISIF_BW656_ENABLE (0x01 << 5)
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/* MODESET registers */
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#define ISIF_VDHDOUT_INPUT (0x00 << 0)
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#define ISIF_INPUT_MASK 0x03
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#define ISIF_INPUT_SHIFT 12
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#define ISIF_FID_POL_MASK 0x01
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#define ISIF_FID_POL_SHIFT 4
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#define ISIF_HD_POL_MASK 0x01
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#define ISIF_HD_POL_SHIFT 3
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#define ISIF_VD_POL_MASK 0x01
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#define ISIF_VD_POL_SHIFT 2
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#define ISIF_DATAPOL_NORMAL 0x00
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#define ISIF_DATAPOL_MASK 0x01
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#define ISIF_DATAPOL_SHIFT 6
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#define ISIF_EXWEN_DISABLE 0x00
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#define ISIF_EXWEN_MASK 0x01
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#define ISIF_EXWEN_SHIFT 5
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#define ISIF_FRM_FMT_MASK 0x01
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#define ISIF_FRM_FMT_SHIFT 7
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#define ISIF_DATASFT_MASK 0x07
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#define ISIF_DATASFT_SHIFT 8
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#define ISIF_LPF_SHIFT 14
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#define ISIF_LPF_MASK 0x1
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/* GAMMAWD registers */
|
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#define ISIF_ALAW_GAMA_WD_MASK 0xf
|
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#define ISIF_ALAW_GAMA_WD_SHIFT 1
|
||||
#define ISIF_ALAW_ENABLE 0x01
|
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#define ISIF_GAMMAWD_CFA_MASK 0x01
|
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#define ISIF_GAMMAWD_CFA_SHIFT 5
|
||||
|
||||
/* HSIZE registers */
|
||||
#define ISIF_HSIZE_FLIP_MASK 0x01
|
||||
#define ISIF_HSIZE_FLIP_SHIFT 12
|
||||
#define ISIF_LINEOFST_MASK 0xfff
|
||||
|
||||
/* MISC registers */
|
||||
#define ISIF_DPCM_EN_SHIFT 12
|
||||
#define ISIF_DPCM_PREDICTOR_SHIFT 13
|
||||
#define ISIF_DPCM_PREDICTOR_MASK 1
|
||||
|
||||
/* Black clamp related */
|
||||
#define ISIF_BC_DCOFFSET_MASK 0x1fff
|
||||
#define ISIF_BC_MODE_COLOR_MASK 1
|
||||
#define ISIF_BC_MODE_COLOR_SHIFT 4
|
||||
#define ISIF_HORZ_BC_MODE_MASK 3
|
||||
#define ISIF_HORZ_BC_MODE_SHIFT 1
|
||||
#define ISIF_HORZ_BC_WIN_COUNT_MASK 0x1f
|
||||
#define ISIF_HORZ_BC_WIN_SEL_SHIFT 5
|
||||
#define ISIF_HORZ_BC_PIX_LIMIT_SHIFT 6
|
||||
#define ISIF_HORZ_BC_WIN_H_SIZE_MASK 3
|
||||
#define ISIF_HORZ_BC_WIN_H_SIZE_SHIFT 8
|
||||
#define ISIF_HORZ_BC_WIN_V_SIZE_MASK 3
|
||||
#define ISIF_HORZ_BC_WIN_V_SIZE_SHIFT 12
|
||||
#define ISIF_HORZ_BC_WIN_START_H_MASK 0x1fff
|
||||
#define ISIF_HORZ_BC_WIN_START_V_MASK 0x1fff
|
||||
#define ISIF_VERT_BC_OB_H_SZ_MASK 7
|
||||
#define ISIF_VERT_BC_RST_VAL_SEL_MASK 3
|
||||
#define ISIF_VERT_BC_RST_VAL_SEL_SHIFT 4
|
||||
#define ISIF_VERT_BC_LINE_AVE_COEF_SHIFT 8
|
||||
#define ISIF_VERT_BC_OB_START_HORZ_MASK 0x1fff
|
||||
#define ISIF_VERT_BC_OB_START_VERT_MASK 0x1fff
|
||||
#define ISIF_VERT_BC_OB_VERT_SZ_MASK 0x1fff
|
||||
#define ISIF_VERT_BC_RST_VAL_MASK 0xfff
|
||||
#define ISIF_BC_VERT_START_SUB_V_MASK 0x1fff
|
||||
|
||||
/* VDFC registers */
|
||||
#define ISIF_VDFC_EN_SHIFT 4
|
||||
#define ISIF_VDFC_CORR_MOD_MASK 3
|
||||
#define ISIF_VDFC_CORR_MOD_SHIFT 5
|
||||
#define ISIF_VDFC_CORR_WHOLE_LN_SHIFT 7
|
||||
#define ISIF_VDFC_LEVEL_SHFT_MASK 7
|
||||
#define ISIF_VDFC_LEVEL_SHFT_SHIFT 8
|
||||
#define ISIF_VDFC_SAT_LEVEL_MASK 0xfff
|
||||
#define ISIF_VDFC_POS_MASK 0x1fff
|
||||
#define ISIF_DFCMEMCTL_DFCMARST_SHIFT 2
|
||||
|
||||
/* CSC registers */
|
||||
#define ISIF_CSC_COEF_INTEG_MASK 7
|
||||
#define ISIF_CSC_COEF_DECIMAL_MASK 0x1f
|
||||
#define ISIF_CSC_COEF_INTEG_SHIFT 5
|
||||
#define ISIF_CSCM_MSB_SHIFT 8
|
||||
#define ISIF_DF_CSC_SPH_MASK 0x1fff
|
||||
#define ISIF_DF_CSC_LNH_MASK 0x1fff
|
||||
#define ISIF_DF_CSC_SLV_MASK 0x1fff
|
||||
#define ISIF_DF_CSC_LNV_MASK 0x1fff
|
||||
#define ISIF_DF_NUMLINES 0x7fff
|
||||
#define ISIF_DF_NUMPIX 0x1fff
|
||||
|
||||
/* Offsets for LSC/DFC/Gain */
|
||||
#define ISIF_DATA_H_OFFSET_MASK 0x1fff
|
||||
#define ISIF_DATA_V_OFFSET_MASK 0x1fff
|
||||
|
||||
/* Linearization */
|
||||
#define ISIF_LIN_CORRSFT_MASK 7
|
||||
#define ISIF_LIN_CORRSFT_SHIFT 4
|
||||
#define ISIF_LIN_SCALE_FACT_INTEG_SHIFT 10
|
||||
#define ISIF_LIN_SCALE_FACT_DECIMAL_MASK 0x3ff
|
||||
#define ISIF_LIN_ENTRY_MASK 0x3ff
|
||||
|
||||
/* masks and shifts*/
|
||||
#define ISIF_SYNCEN_VDHDEN_MASK (1 << 0)
|
||||
#define ISIF_SYNCEN_WEN_MASK (1 << 1)
|
||||
#define ISIF_SYNCEN_WEN_SHIFT 1
|
||||
|
||||
#endif /* _DAVINCI_VPFE_DM365_ISIF_REGS_H */
|
||||
Loading…
Reference in New Issue
Block a user