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ASoC: Intel: Add PM support to the HSW/BDW DSP core.
Add support for PM wake, sleep and stall calls to the core HSW/BDW driver. This includes reworking the reset and boot code and adding new calls for setting D3/D0 state. Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Liam Girdwood
Mark Brown
parent
d96c53a193
commit
6b7b4b8941
@ -247,8 +247,67 @@ static irqreturn_t hsw_irq(int irq, void *context)
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return ret;
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}
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static void hsw_boot(struct sst_dsp *sst)
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static void hsw_set_dsp_D3(struct sst_dsp *sst)
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{
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u32 val;
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/* switch off audio PLL, DRAM & IRAM blocks */
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val = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
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val |= SST_VDRTCL0_APLLSE_MASK | SST_VDRTCL0_DSRAMPGE_MASK |
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SST_VDRTCL0_ISRAMPGE_MASK;
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writel(val, sst->addr.pci_cfg + SST_VDRTCTL0);
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/* Set D3 state */
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val = readl(sst->addr.pci_cfg + SST_PMCS);
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val |= SST_PMCS_PS_MASK;
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writel(val, sst->addr.pci_cfg + SST_PMCS);
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}
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static void hsw_reset(struct sst_dsp *sst)
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{
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/* put DSP into reset and stall */
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sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
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SST_CSR_RST | SST_CSR_STALL,
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SST_CSR_RST | SST_CSR_STALL);
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/* keep in reset for 10ms */
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mdelay(10);
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/* take DSP out of reset and keep stalled for FW loading */
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sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
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SST_CSR_RST | SST_CSR_STALL, SST_CSR_STALL);
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}
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static int hsw_set_dsp_D0(struct sst_dsp *sst)
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{
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int tries = 10;
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u32 reg;
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/* Set D0 state */
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reg = readl(sst->addr.pci_cfg + SST_PMCS);
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reg &= ~SST_PMCS_PS_MASK;
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writel(reg, sst->addr.pci_cfg + SST_PMCS);
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/* check that ADSP shim is enabled */
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while (tries--) {
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reg = readl(sst->addr.pci_cfg + SST_PMCS) & SST_PMCS_PS_MASK;
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if (reg == 0)
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goto finish;
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msleep(1);
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}
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return -ENODEV;
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finish:
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hsw_reset(sst);
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/* switch on audio PLL, DRAM & IRAM blocks */
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reg = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
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reg &= ~(SST_VDRTCL0_APLLSE_MASK | SST_VDRTCL0_DSRAMPGE_MASK |
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SST_VDRTCL0_ISRAMPGE_MASK);
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writel(reg, sst->addr.pci_cfg + SST_VDRTCTL0);
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/* select SSP1 19.2MHz base clock, SSP clock 0, turn off Low Power Clock */
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sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
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SST_CSR_S1IOCS | SST_CSR_SBCS1 | SST_CSR_LPCS, 0x0);
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@ -267,30 +326,73 @@ static void hsw_boot(struct sst_dsp *sst)
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sst_dsp_shim_update_bits_unlocked(sst, SST_CSR2, SST_CSR2_SDFD_SSP1,
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SST_CSR2_SDFD_SSP1);
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/* enable DMA engine 0,1 all channels to access host memory */
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sst_dsp_shim_update_bits_unlocked(sst, SST_HMDC,
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SST_HMDC_HDDA1(0xff) | SST_HMDC_HDDA0(0xff),
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SST_HMDC_HDDA1(0xff) | SST_HMDC_HDDA0(0xff));
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/* set on-demond mode on engine 0,1 for all channels */
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sst_dsp_shim_update_bits(sst, SST_HMDC,
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SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH,
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SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH);
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/* Enable Interrupt from both sides */
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sst_dsp_shim_update_bits(sst, SST_IMRX, (SST_IMRX_BUSY | SST_IMRX_DONE),
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0x0);
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sst_dsp_shim_update_bits(sst, SST_IMRD, (SST_IMRD_DONE | SST_IMRD_BUSY |
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SST_IMRD_SSP0 | SST_IMRD_DMAC), 0x0);
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/* clear IPC registers */
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sst_dsp_shim_write(sst, SST_IPCX, 0x0);
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sst_dsp_shim_write(sst, SST_IPCD, 0x0);
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sst_dsp_shim_write(sst, 0x80, 0x6);
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sst_dsp_shim_write(sst, 0xe0, 0x300a);
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/* disable all clock gating */
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writel(0x0, sst->addr.pci_cfg + SST_VDRTCTL2);
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return 0;
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}
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static void hsw_boot(struct sst_dsp *sst)
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{
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/* set oportunistic mode on engine 0,1 for all channels */
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sst_dsp_shim_update_bits(sst, SST_HMDC,
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SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH, 0);
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/* set DSP to RUN */
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sst_dsp_shim_update_bits_unlocked(sst, SST_CSR, SST_CSR_STALL, 0x0);
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}
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static void hsw_reset(struct sst_dsp *sst)
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static void hsw_stall(struct sst_dsp *sst)
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{
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/* stall DSP */
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sst_dsp_shim_update_bits(sst, SST_CSR,
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SST_CSR_24MHZ_LPCS | SST_CSR_STALL,
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SST_CSR_STALL | SST_CSR_24MHZ_LPCS);
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}
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static void hsw_sleep(struct sst_dsp *sst)
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{
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dev_dbg(sst->dev, "HSW_PM dsp runtime suspend\n");
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/* put DSP into reset and stall */
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sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
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SST_CSR_RST | SST_CSR_STALL, SST_CSR_RST | SST_CSR_STALL);
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sst_dsp_shim_update_bits(sst, SST_CSR,
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SST_CSR_24MHZ_LPCS | SST_CSR_RST | SST_CSR_STALL,
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SST_CSR_RST | SST_CSR_STALL | SST_CSR_24MHZ_LPCS);
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/* keep in reset for 10ms */
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mdelay(10);
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hsw_set_dsp_D3(sst);
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dev_dbg(sst->dev, "HSW_PM dsp runtime suspend exit\n");
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}
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/* take DSP out of reset and keep stalled for FW loading */
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sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
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SST_CSR_RST | SST_CSR_STALL, SST_CSR_STALL);
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static int hsw_wake(struct sst_dsp *sst)
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{
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int ret;
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dev_dbg(sst->dev, "HSW_PM dsp runtime resume\n");
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ret = hsw_set_dsp_D0(sst);
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if (ret < 0)
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return ret;
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dev_dbg(sst->dev, "HSW_PM dsp runtime resume exit\n");
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return 0;
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}
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struct sst_adsp_memregion {
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@ -431,27 +533,6 @@ static struct sst_block_ops sst_hsw_ops = {
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.disable = hsw_block_disable,
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};
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static int hsw_enable_shim(struct sst_dsp *sst)
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{
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int tries = 10;
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u32 reg;
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/* enable shim */
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reg = readl(sst->addr.pci_cfg + SST_SHIM_PM_REG);
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writel(reg & ~0x3, sst->addr.pci_cfg + SST_SHIM_PM_REG);
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/* check that ADSP shim is enabled */
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while (tries--) {
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reg = sst_dsp_shim_read_unlocked(sst, SST_CSR);
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if (reg != 0xffffffff)
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return 0;
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msleep(1);
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}
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return -ENODEV;
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}
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static int hsw_init(struct sst_dsp *sst, struct sst_pdata *pdata)
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{
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const struct sst_adsp_memregion *region;
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@ -490,7 +571,7 @@ static int hsw_init(struct sst_dsp *sst, struct sst_pdata *pdata)
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}
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/* enable the DSP SHIM */
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ret = hsw_enable_shim(sst);
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ret = hsw_set_dsp_D0(sst);
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if (ret < 0) {
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dev_err(dev, "error: failed to set DSP D0 and reset SHIM\n");
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return ret;
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@ -500,10 +581,6 @@ static int hsw_init(struct sst_dsp *sst, struct sst_pdata *pdata)
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if (ret)
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return ret;
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/* Enable Interrupt from both sides */
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sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX, 0x3, 0x0);
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sst_dsp_shim_update_bits_unlocked(sst, SST_IMRD,
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(0x3 | 0x1 << 16 | 0x3 << 21), 0x0);
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/* register DSP memory blocks - ideally we should get this from ACPI */
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for (i = 0; i < region_count; i++) {
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@ -535,6 +612,9 @@ static void hsw_free(struct sst_dsp *sst)
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struct sst_ops haswell_ops = {
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.reset = hsw_reset,
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.boot = hsw_boot,
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.stall = hsw_stall,
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.wake = hsw_wake,
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.sleep = hsw_sleep,
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.write = sst_shim32_write,
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.read = sst_shim32_read,
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.write64 = sst_shim32_write64,
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