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x86, 64bit: #PF handler set page to cover only 2M per #PF

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We only map a single 2 MiB page per #PF, even though we should be able
to do this a full gigabyte at a time with no additional memory cost.
This is a workaround for a broken AMD reference BIOS (and its
derivatives in shipping system) which maps a large chunk of memory as
WB in the MTRR system but will #MC if the processor wanders off and
tries to prefetch that memory, which can happen any time the memory is
mapped in the TLB.

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Link: http://lkml.kernel.org/r/1359058816-7615-13-git-send-email-yinghai@kernel.org
Cc: Alexander Duyck <alexander.h.duyck@intel.com>
[ hpa: rewrote the patch description ]
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
This commit is contained in:
Yinghai Lu 2013-01-24 12:19:53 -08:00 committed by H. Peter Anvin
parent 8170e6bed4
commit 6b9c75aca6
1 changed files with 24 additions and 16 deletions
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40
arch/x86/kernel/head64.c
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@ -53,15 +53,15 @@ int __init early_make_pgtable(unsigned long address)
unsigned long physaddr = address - __PAGE_OFFSET; unsigned long physaddr = address - __PAGE_OFFSET;
unsigned long i; unsigned long i;
pgdval_t pgd, *pgd_p; pgdval_t pgd, *pgd_p;
pudval_t *pud_p; pudval_t pud, *pud_p;
pmdval_t pmd, *pmd_p; pmdval_t pmd, *pmd_p;
/* Invalid address or early pgt is done ? */ /* Invalid address or early pgt is done ? */
if (physaddr >= MAXMEM || read_cr3() != __pa(early_level4_pgt)) if (physaddr >= MAXMEM || read_cr3() != __pa(early_level4_pgt))
return -1; return -1;
i = (address >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1); again:
pgd_p = &early_level4_pgt[i].pgd; pgd_p = &early_level4_pgt[pgd_index(address)].pgd;
pgd = *pgd_p; pgd = *pgd_p;
/* /*
@ -69,29 +69,37 @@ int __init early_make_pgtable(unsigned long address)
* critical -- __PAGE_OFFSET would point us back into the dynamic * critical -- __PAGE_OFFSET would point us back into the dynamic
* range and we might end up looping forever... * range and we might end up looping forever...
*/ */
if (pgd && next_early_pgt < EARLY_DYNAMIC_PAGE_TABLES) { if (pgd)
pud_p = (pudval_t *)((pgd & PTE_PFN_MASK) + __START_KERNEL_map - phys_base); pud_p = (pudval_t *)((pgd & PTE_PFN_MASK) + __START_KERNEL_map - phys_base);
} else { else {
if (next_early_pgt >= EARLY_DYNAMIC_PAGE_TABLES-1) if (next_early_pgt >= EARLY_DYNAMIC_PAGE_TABLES) {
reset_early_page_tables(); reset_early_page_tables();
goto again;
}
pud_p = (pudval_t *)early_dynamic_pgts[next_early_pgt++]; pud_p = (pudval_t *)early_dynamic_pgts[next_early_pgt++];
for (i = 0; i < PTRS_PER_PUD; i++) for (i = 0; i < PTRS_PER_PUD; i++)
pud_p[i] = 0; pud_p[i] = 0;
*pgd_p = (pgdval_t)pud_p - __START_KERNEL_map + phys_base + _KERNPG_TABLE; *pgd_p = (pgdval_t)pud_p - __START_KERNEL_map + phys_base + _KERNPG_TABLE;
} }
i = (address >> PUD_SHIFT) & (PTRS_PER_PUD - 1); pud_p += pud_index(address);
pud_p += i; pud = *pud_p;
pmd_p = (pmdval_t *)early_dynamic_pgts[next_early_pgt++]; if (pud)
pmd = (physaddr & PUD_MASK) + (__PAGE_KERNEL_LARGE & ~_PAGE_GLOBAL); pmd_p = (pmdval_t *)((pud & PTE_PFN_MASK) + __START_KERNEL_map - phys_base);
for (i = 0; i < PTRS_PER_PMD; i++) { else {
pmd_p[i] = pmd; if (next_early_pgt >= EARLY_DYNAMIC_PAGE_TABLES) {
pmd += PMD_SIZE; reset_early_page_tables();
goto again;
}
pmd_p = (pmdval_t *)early_dynamic_pgts[next_early_pgt++];
for (i = 0; i < PTRS_PER_PMD; i++)
pmd_p[i] = 0;
*pud_p = (pudval_t)pmd_p - __START_KERNEL_map + phys_base + _KERNPG_TABLE;
} }
pmd = (physaddr & PMD_MASK) + (__PAGE_KERNEL_LARGE & ~_PAGE_GLOBAL);
*pud_p = (pudval_t)pmd_p - __START_KERNEL_map + phys_base + _KERNPG_TABLE; pmd_p[pmd_index(address)] = pmd;
return 0; return 0;
} }