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clk: sunxi: Add DRAM gates support for sun4i-a10

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The A10/A20 share the same set of DRAM clock gates, which controls
direct memory access for some peripherals.

On the A10, bit 15 controls the system's DRAM clock output (possibly
to the DRAM chips), which we need to keep on.

On the A20 this has been moved to the DRAM controller, becoming a no-op.
However it is still listed in the user manual, so add it anyway.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Chen-Yu Tsai 2015-12-05 21:16:42 +08:00 committed by Maxime Ripard
parent 77d16e2c66
commit 6d3a47c291
2 changed files with 13 additions and 0 deletions
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1
Documentation/devicetree/bindings/clock/sunxi.txt
View File

@ -57,6 +57,7 @@ Required properties:
"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
"allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
"allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10
"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80

12
drivers/clk/sunxi/clk-simple-gates.c
View File

@ -160,3 +160,15 @@ CLK_OF_DECLARE(sun5i_a13_ahb, "allwinner,sun5i-a13-ahb-gates-clk",
sun4i_a10_ahb_init);
CLK_OF_DECLARE(sun7i_a20_ahb, "allwinner,sun7i-a20-ahb-gates-clk",
sun4i_a10_ahb_init);
static const int sun4i_a10_dram_critical_clocks[] __initconst = {
15, /* dram_output */
};
static void __init sun4i_a10_dram_init(struct device_node *node)
{
sunxi_simple_gates_setup(node, sun4i_a10_dram_critical_clocks,
ARRAY_SIZE(sun4i_a10_dram_critical_clocks));
}
CLK_OF_DECLARE(sun4i_a10_dram, "allwinner,sun4i-a10-dram-gates-clk",
sun4i_a10_dram_init);