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ARM: nomadik: convert all clocks except timer to dt
This moves all Nomadik clocks except the one used for the timer/clocksource over to the device tree. Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
parent
c7785ea0d2
commit
6e2b07a172
@ -3,6 +3,11 @@ ST-Ericsson Nomadik Device Tree Bindings
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For various board the "board" node may contain specific properties
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that pertain to this particular board, such as board-specific GPIOs.
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Required root node property: src
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- Nomadik System and reset controller used for basic chip control, clock
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and reset line control.
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- compatible: must be "stericsson,nomadik,src"
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Boards with the Nomadik SoC include:
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S8815 "MiniKit" manufactured by Calao Systems:
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@ -45,6 +45,7 @@
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gpio-controller;
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#gpio-cells = <2>;
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gpio-bank = <0>;
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clocks = <&pclk>;
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};
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gpio1: gpio@101e5000 {
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@ -57,6 +58,7 @@
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gpio-controller;
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#gpio-cells = <2>;
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gpio-bank = <1>;
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clocks = <&pclk>;
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};
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gpio2: gpio@101e6000 {
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@ -69,6 +71,7 @@
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gpio-controller;
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#gpio-cells = <2>;
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gpio-bank = <2>;
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clocks = <&pclk>;
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};
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gpio3: gpio@101e7000 {
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@ -81,12 +84,50 @@
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gpio-controller;
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#gpio-cells = <2>;
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gpio-bank = <3>;
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clocks = <&pclk>;
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};
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pinctrl {
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compatible = "stericsson,nmk-pinctrl-stn8815";
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};
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src: src@101e0000 {
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compatible = "stericsson,nomadik-src";
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reg = <0x101e0000 0x1000>;
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clocks {
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/*
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* Dummy clock for primecells
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*/
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pclk: pclk@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <2400000>;
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};
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/*
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* The 2.4 MHz TIMCLK reference clock is active at
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* boot time, this is actually the MXTALCLK @19.2 MHz
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* divided by 8. This clock is used by the timers and
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* watchdog. See page 105 ff.
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*/
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timclk: timclk@2.4M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <2400000>;
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};
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/*
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* At boot time, PLL2 is set to generate a set of
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* fixed clocks, one of them is CLK48, the 48 MHz
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* clock, routed to the UART, MMC/SD, I2C, IrDA,
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* USB and SSP blocks.
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*/
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clk48: clk48@48M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <48000000>;
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};
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};
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};
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/* A NAND flash of 128 MiB */
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fsmc: flash@40000000 {
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compatible = "stericsson,fsmc-nand";
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@ -97,6 +138,7 @@
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<0x41000000 0x2000>, /* NAND Base ADDR */
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<0x40800000 0x2000>; /* NAND Base CMD */
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reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
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clocks = <&pclk>;
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status = "okay";
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partition@0 {
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@ -211,6 +253,8 @@
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reg = <0x101fd000 0x1000>;
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interrupt-parent = <&vica>;
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interrupts = <12>;
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clocks = <&clk48>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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uart1: uart@101fb000 {
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@ -218,6 +262,8 @@
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reg = <0x101fb000 0x1000>;
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interrupt-parent = <&vica>;
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interrupts = <17>;
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clocks = <&clk48>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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uart2: uart@101f2000 {
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@ -225,17 +271,23 @@
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reg = <0x101f2000 0x1000>;
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interrupt-parent = <&vica>;
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interrupts = <28>;
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clocks = <&clk48>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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rng: rng@101b0000 {
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compatible = "arm,primecell";
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reg = <0x101b0000 0x1000>;
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clocks = <&clk48>, <&pclk>;
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clock-names = "rng", "apb_pclk";
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};
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rtc: rtc@101e8000 {
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compatible = "arm,pl031", "arm,primecell";
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reg = <0x101e8000 0x1000>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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interrupt-parent = <&vica>;
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interrupts = <10>;
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};
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@ -243,6 +295,8 @@
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mmcsd: sdi@101f6000 {
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compatible = "arm,pl18x", "arm,primecell";
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reg = <0x101f6000 0x1000>;
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clocks = <&clk48>, <&pclk>;
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clock-names = "mclk", "apb_pclk";
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interrupt-parent = <&vica>;
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interrupts = <22>;
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max-frequency = <48000000>;
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@ -280,28 +280,12 @@ device_initcall(cpu8815_mmcsd_init);
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/* These are mostly to get the right device names for the clock lookups */
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static struct of_dev_auxdata cpu8815_auxdata_lookup[] __initdata = {
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OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO0_BASE,
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"gpio.0", NULL),
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OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO1_BASE,
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"gpio.1", NULL),
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OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO2_BASE,
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"gpio.2", NULL),
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OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO3_BASE,
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"gpio.3", NULL),
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OF_DEV_AUXDATA("stericsson,nmk-pinctrl-stn8815", 0,
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"pinctrl-stn8815", NULL),
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OF_DEV_AUXDATA("arm,primecell", NOMADIK_UART0_BASE,
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"uart0", NULL),
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OF_DEV_AUXDATA("arm,primecell", NOMADIK_UART1_BASE,
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"uart1", NULL),
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OF_DEV_AUXDATA("arm,primecell", NOMADIK_RNG_BASE,
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"rng", NULL),
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OF_DEV_AUXDATA("arm,primecell", NOMADIK_RTC_BASE,
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"rtc-pl031", NULL),
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OF_DEV_AUXDATA("stericsson,fsmc-nand", NOMADIK_FSMC_BASE,
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"fsmc-nand", &cpu8815_nand_data),
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NULL, &cpu8815_nand_data),
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OF_DEV_AUXDATA("arm,primecell", NOMADIK_SDI_BASE,
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"mmci", &mmcsd_plat_data),
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NULL, &mmcsd_plat_data),
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{ /* sentinel */ },
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};
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@ -3,24 +3,24 @@
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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/*
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* The Nomadik clock tree is described in the STN8815A12 DB V4.2
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* reference manual for the chip, page 94 ff.
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*/
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static const __initconst struct of_device_id cpu8815_clk_match[] = {
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{ .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
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{ /* sentinel */ }
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};
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void __init nomadik_clk_init(void)
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{
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struct clk *clk;
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clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
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clk_register_clkdev(clk, "apb_pclk", NULL);
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clk_register_clkdev(clk, NULL, "gpio.0");
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clk_register_clkdev(clk, NULL, "gpio.1");
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clk_register_clkdev(clk, NULL, "gpio.2");
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clk_register_clkdev(clk, NULL, "gpio.3");
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clk_register_clkdev(clk, NULL, "rng");
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clk_register_clkdev(clk, NULL, "fsmc-nand");
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/*
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* The 2.4 MHz TIMCLK reference clock is active at boot time, this is
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@ -32,17 +32,5 @@ void __init nomadik_clk_init(void)
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clk_register_clkdev(clk, NULL, "mtu0");
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clk_register_clkdev(clk, NULL, "mtu1");
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/*
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* At boot time, PLL2 is set to generate a set of fixed clocks,
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* one of them is CLK48, the 48 MHz clock, routed to the UART, MMC/SD
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* I2C, IrDA, USB and SSP blocks.
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*/
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clk = clk_register_fixed_rate(NULL, "CLK48", NULL, CLK_IS_ROOT,
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48000000);
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clk_register_clkdev(clk, NULL, "uart0");
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clk_register_clkdev(clk, NULL, "uart1");
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clk_register_clkdev(clk, NULL, "mmci");
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clk_register_clkdev(clk, NULL, "ssp");
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clk_register_clkdev(clk, NULL, "nmk-i2c.0");
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clk_register_clkdev(clk, NULL, "nmk-i2c.1");
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of_clk_init(cpu8815_clk_match);
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}
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