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ARM: cns3xxx: Use IO memory accessors everywhere
Before it isn't too late let's switch to IO memory accessors. This patch converts all current _REG users and _REG definitions. There should be no functional changes. Suggested-by: Ben Dooks <ben-linux@fluff.org> Suggested-by: Sergei Shtylyov <sshtylyov@mvista.com> Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
This commit is contained in:
Anton Vorontsov
parent
9dda696f0d
commit
6eb5d146d4
@ -247,37 +247,36 @@
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* Misc block
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*/
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#define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs))
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#define MISC_MEM_MAP_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_MISC_BASE_VIRT + (offset))))
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#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP_VALUE(0x00)
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#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP_VALUE(0x04)
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#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP_VALUE(0x08)
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#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP_VALUE(0x0C)
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#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP_VALUE(0x10)
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#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x14)
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#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x18)
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#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP_VALUE(0x1C)
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#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP_VALUE(0x20)
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#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x24)
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#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x28)
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#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x2C)
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#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x30)
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#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x34)
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#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP_VALUE(0x40)
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#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP_VALUE(0x44)
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#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP_VALUE(0x48)
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#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP_VALUE(0x4C)
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#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP_VALUE(0x50)
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#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP_VALUE(0x54)
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#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP(0x00)
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#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP(0x04)
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#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP(0x08)
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#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP(0x0C)
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#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP(0x10)
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#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP(0x14)
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#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP(0x18)
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#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP(0x1C)
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#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP(0x20)
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#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x24)
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#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x28)
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#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x2C)
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#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x30)
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#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP(0x34)
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#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP(0x40)
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#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP(0x44)
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#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP(0x48)
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#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP(0x4C)
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#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP(0x50)
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#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP(0x54)
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#define MISC_SATA_POWER_MODE MISC_MEM_MAP_VALUE(0x310)
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#define MISC_SATA_POWER_MODE MISC_MEM_MAP(0x310)
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#define MISC_USB_CFG_REG MISC_MEM_MAP_VALUE(0x800)
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#define MISC_USB_STS_REG MISC_MEM_MAP_VALUE(0x804)
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#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP_VALUE(0x808)
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#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP_VALUE(0x80c)
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#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP_VALUE(0x810)
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#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP_VALUE(0x814)
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#define MISC_USB_CFG_REG MISC_MEM_MAP(0x800)
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#define MISC_USB_STS_REG MISC_MEM_MAP(0x804)
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#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP(0x808)
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#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP(0x80c)
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#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP(0x810)
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#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP(0x814)
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#define MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004)
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#define MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100)
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@ -300,21 +299,21 @@
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/*
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* Power management and clock control
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*/
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#define PMU_REG_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_PM_BASE_VIRT + (offset))))
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#define PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs))
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#define PM_CLK_GATE_REG PMU_REG_VALUE(0x000)
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#define PM_SOFT_RST_REG PMU_REG_VALUE(0x004)
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#define PM_HS_CFG_REG PMU_REG_VALUE(0x008)
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#define PM_CACTIVE_STA_REG PMU_REG_VALUE(0x00C)
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#define PM_PWR_STA_REG PMU_REG_VALUE(0x010)
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#define PM_CLK_CTRL_REG PMU_REG_VALUE(0x014)
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#define PM_PLL_LCD_I2S_CTRL_REG PMU_REG_VALUE(0x018)
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#define PM_PLL_HM_PD_CTRL_REG PMU_REG_VALUE(0x01C)
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#define PM_REGULAT_CTRL_REG PMU_REG_VALUE(0x020)
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#define PM_WDT_CTRL_REG PMU_REG_VALUE(0x024)
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#define PM_WU_CTRL0_REG PMU_REG_VALUE(0x028)
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#define PM_WU_CTRL1_REG PMU_REG_VALUE(0x02C)
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#define PM_CSR_REG PMU_REG_VALUE(0x030)
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#define PM_CLK_GATE_REG PMU_MEM_MAP(0x000)
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#define PM_SOFT_RST_REG PMU_MEM_MAP(0x004)
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#define PM_HS_CFG_REG PMU_MEM_MAP(0x008)
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#define PM_CACTIVE_STA_REG PMU_MEM_MAP(0x00C)
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#define PM_PWR_STA_REG PMU_MEM_MAP(0x010)
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#define PM_CLK_CTRL_REG PMU_MEM_MAP(0x014)
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#define PM_PLL_LCD_I2S_CTRL_REG PMU_MEM_MAP(0x018)
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#define PM_PLL_HM_PD_CTRL_REG PMU_MEM_MAP(0x01C)
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#define PM_REGULAT_CTRL_REG PMU_MEM_MAP(0x020)
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#define PM_WDT_CTRL_REG PMU_MEM_MAP(0x024)
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#define PM_WU_CTRL0_REG PMU_MEM_MAP(0x028)
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#define PM_WU_CTRL1_REG PMU_MEM_MAP(0x02C)
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#define PM_CSR_REG PMU_MEM_MAP(0x030)
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/* PM_CLK_GATE_REG */
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#define PM_CLK_GATE_REG_OFFSET_SDIO (25)
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@ -6,18 +6,25 @@
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* published by the Free Software Foundation.
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*/
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <mach/system.h>
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#include <mach/cns3xxx.h>
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void cns3xxx_pwr_clk_en(unsigned int block)
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{
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PM_CLK_GATE_REG |= (block & PM_CLK_GATE_REG_MASK);
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u32 reg = __raw_readl(PM_CLK_GATE_REG);
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reg |= (block & PM_CLK_GATE_REG_MASK);
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__raw_writel(reg, PM_CLK_GATE_REG);
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}
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void cns3xxx_pwr_power_up(unsigned int block)
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{
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PM_PLL_HM_PD_CTRL_REG &= ~(block & CNS3XXX_PWR_PLL_ALL);
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u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
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reg &= ~(block & CNS3XXX_PWR_PLL_ALL);
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__raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
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/* Wait for 300us for the PLL output clock locked. */
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udelay(300);
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@ -25,22 +32,29 @@ void cns3xxx_pwr_power_up(unsigned int block)
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void cns3xxx_pwr_power_down(unsigned int block)
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{
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u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
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/* write '1' to power down */
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PM_PLL_HM_PD_CTRL_REG |= (block & CNS3XXX_PWR_PLL_ALL);
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reg |= (block & CNS3XXX_PWR_PLL_ALL);
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__raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
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};
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static void cns3xxx_pwr_soft_rst_force(unsigned int block)
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{
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u32 reg = __raw_readl(PM_SOFT_RST_REG);
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/*
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* bit 0, 28, 29 => program low to reset,
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* the other else program low and then high
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*/
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if (block & 0x30000001) {
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PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
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reg &= ~(block & PM_SOFT_RST_REG_MASK);
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} else {
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PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
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PM_SOFT_RST_REG |= (block & PM_SOFT_RST_REG_MASK);
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reg &= ~(block & PM_SOFT_RST_REG_MASK);
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reg |= (block & PM_SOFT_RST_REG_MASK);
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}
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__raw_writel(reg, PM_SOFT_RST_REG);
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}
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void cns3xxx_pwr_soft_rst(unsigned int block)
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@ -73,12 +87,13 @@ void arch_reset(char mode, const char *cmd)
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*/
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int cns3xxx_cpu_clock(void)
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{
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u32 reg = __raw_readl(PM_CLK_CTRL_REG);
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int cpu;
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int cpu_sel;
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int div_sel;
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cpu_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
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div_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
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cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
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div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
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cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;
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