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Merge branch 'clk-fixes' into clk-next
* clk-fixes: clk: samsung: fix cpu clock's flags checking
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commit
6f83d30a37
@ -164,7 +164,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
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* the values for DIV_COPY and DIV_HPM dividers need not be set.
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*/
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div0 = cfg_data->div0;
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if (test_bit(CLK_CPU_HAS_DIV1, &cpuclk->flags)) {
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if (cpuclk->flags & CLK_CPU_HAS_DIV1) {
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div1 = cfg_data->div1;
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if (readl(base + E4210_SRC_CPU) & E4210_MUX_HPM_MASK)
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div1 = readl(base + E4210_DIV_CPU1) &
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@ -185,7 +185,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
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alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;
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WARN_ON(alt_div >= MAX_DIV);
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if (test_bit(CLK_CPU_NEEDS_DEBUG_ALT_DIV, &cpuclk->flags)) {
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if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
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/*
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* In Exynos4210, ATB clock parent is also mout_core. So
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* ATB clock also needs to be mantained at safe speed.
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@ -206,7 +206,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
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writel(div0, base + E4210_DIV_CPU0);
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wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, DIV_MASK_ALL);
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if (test_bit(CLK_CPU_HAS_DIV1, &cpuclk->flags)) {
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if (cpuclk->flags & CLK_CPU_HAS_DIV1) {
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writel(div1, base + E4210_DIV_CPU1);
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wait_until_divider_stable(base + E4210_DIV_STAT_CPU1,
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DIV_MASK_ALL);
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@ -225,7 +225,7 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
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unsigned long mux_reg;
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/* find out the divider values to use for clock data */
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if (test_bit(CLK_CPU_NEEDS_DEBUG_ALT_DIV, &cpuclk->flags)) {
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if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
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while ((cfg_data->prate * 1000) != ndata->new_rate) {
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if (cfg_data->prate == 0)
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return -EINVAL;
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@ -240,7 +240,7 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
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writel(mux_reg & ~(1 << 16), base + E4210_SRC_CPU);
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wait_until_mux_stable(base + E4210_STAT_CPU, 16, 1);
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if (test_bit(CLK_CPU_NEEDS_DEBUG_ALT_DIV, &cpuclk->flags)) {
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if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
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div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK);
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div_mask |= E4210_DIV0_ATB_MASK;
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}
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