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drm/i915: Set SSC frequency for 8xx chips correctly

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All 8xx class chips have the 66/48 split, not just 855.

Signed-off-by: Ma Ling <ling.ma@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
ling.ma@intel.com 2009-06-25 10:59:22 +08:00 committed by Eric Anholt
parent 7662c8bd65
commit 6ff4fd0567
1 changed files with 6 additions and 4 deletions
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10
drivers/gpu/drm/i915/intel_bios.c
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@ -195,10 +195,12 @@ parse_general_features(struct drm_i915_private *dev_priv,
dev_priv->lvds_use_ssc = general->enable_ssc;
if (dev_priv->lvds_use_ssc) {
if (IS_I855(dev_priv->dev))
dev_priv->lvds_ssc_freq = general->ssc_freq ? 66 : 48;
else
dev_priv->lvds_ssc_freq = general->ssc_freq ? 100 : 96;
if (IS_I85X(dev_priv->dev))
dev_priv->lvds_ssc_freq =
general->ssc_freq ? 66 : 48;
else
dev_priv->lvds_ssc_freq =
general->ssc_freq ? 100 : 96;
}
}
}