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bpf, arm64: use separate register for state in stxr
Will reported that in BPF_XADD we must use a different register in stxr
instruction for the status flag due to otherwise CONSTRAINED UNPREDICTABLE
behavior per architecture. Reference manual says [1]:
If s == t, then one of the following behaviors must occur:
* The instruction is UNDEFINED.
* The instruction executes as a NOP.
* The instruction performs the store to the specified address, but
the value stored is UNKNOWN.
Thus, use a different temporary register for the status flag to fix it.
Disassembly extract from test 226/STX_XADD_DW from test_bpf.ko:
[...]
0000003c: c85f7d4b ldxr x11, [x10]
00000040: 8b07016b add x11, x11, x7
00000044: c80c7d4b stxr w12, x11, [x10]
00000048: 35ffffac cbnz w12, 0x0000003c
[...]
[1] https://static.docs.arm.com/ddi0487/b/DDI0487B_a_armv8_arm.pdf, p.6132
Fixes: 85f68fe898
("bpf, arm64: implement jiting of BPF_XADD")
Reported-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
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@ -36,6 +36,7 @@ int bpf_jit_enable __read_mostly;
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#define TMP_REG_1 (MAX_BPF_JIT_REG + 0)
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#define TMP_REG_2 (MAX_BPF_JIT_REG + 1)
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#define TCALL_CNT (MAX_BPF_JIT_REG + 2)
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#define TMP_REG_3 (MAX_BPF_JIT_REG + 3)
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/* Map BPF registers to A64 registers */
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static const int bpf2a64[] = {
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@ -57,6 +58,7 @@ static const int bpf2a64[] = {
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/* temporary registers for internal BPF JIT */
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[TMP_REG_1] = A64_R(10),
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[TMP_REG_2] = A64_R(11),
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[TMP_REG_3] = A64_R(12),
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/* tail_call_cnt */
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[TCALL_CNT] = A64_R(26),
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/* temporary register for blinding constants */
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@ -319,6 +321,7 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx)
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const u8 src = bpf2a64[insn->src_reg];
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const u8 tmp = bpf2a64[TMP_REG_1];
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const u8 tmp2 = bpf2a64[TMP_REG_2];
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const u8 tmp3 = bpf2a64[TMP_REG_3];
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const s16 off = insn->off;
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const s32 imm = insn->imm;
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const int i = insn - ctx->prog->insnsi;
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@ -689,10 +692,10 @@ emit_cond_jmp:
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emit(A64_PRFM(tmp, PST, L1, STRM), ctx);
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emit(A64_LDXR(isdw, tmp2, tmp), ctx);
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emit(A64_ADD(isdw, tmp2, tmp2, src), ctx);
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emit(A64_STXR(isdw, tmp2, tmp, tmp2), ctx);
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emit(A64_STXR(isdw, tmp2, tmp, tmp3), ctx);
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jmp_offset = -3;
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check_imm19(jmp_offset);
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emit(A64_CBNZ(0, tmp2, jmp_offset), ctx);
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emit(A64_CBNZ(0, tmp3, jmp_offset), ctx);
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break;
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/* R0 = ntohx(*(size *)(((struct sk_buff *)R6)->data + imm)) */
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