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ARM: common: edma: Internal API to use pointer to 'struct edma'
Merge the iomem into the 'struct edma' and change the internal (static) functions to use pointer to the edma_cc instead of the ctlr number. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Peter Ujfalusi
Vinod Koul
parent
dc9b60552f
commit
700c371913
@ -114,127 +114,10 @@
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#define EDMA_MAX_PARAMENTRY 512
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/*****************************************************************************/
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static void __iomem *edmacc_regs_base[EDMA_MAX_CC];
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static inline unsigned int edma_read(unsigned ctlr, int offset)
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{
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return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset);
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}
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static inline void edma_write(unsigned ctlr, int offset, int val)
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{
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__raw_writel(val, edmacc_regs_base[ctlr] + offset);
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}
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static inline void edma_modify(unsigned ctlr, int offset, unsigned and,
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unsigned or)
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{
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unsigned val = edma_read(ctlr, offset);
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val &= and;
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val |= or;
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edma_write(ctlr, offset, val);
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}
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static inline void edma_and(unsigned ctlr, int offset, unsigned and)
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{
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unsigned val = edma_read(ctlr, offset);
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val &= and;
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edma_write(ctlr, offset, val);
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}
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static inline void edma_or(unsigned ctlr, int offset, unsigned or)
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{
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unsigned val = edma_read(ctlr, offset);
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val |= or;
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edma_write(ctlr, offset, val);
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}
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static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i)
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{
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return edma_read(ctlr, offset + (i << 2));
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}
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static inline void edma_write_array(unsigned ctlr, int offset, int i,
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unsigned val)
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{
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edma_write(ctlr, offset + (i << 2), val);
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}
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static inline void edma_modify_array(unsigned ctlr, int offset, int i,
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unsigned and, unsigned or)
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{
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edma_modify(ctlr, offset + (i << 2), and, or);
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}
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static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or)
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{
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edma_or(ctlr, offset + (i << 2), or);
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}
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static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j,
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unsigned or)
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{
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edma_or(ctlr, offset + ((i*2 + j) << 2), or);
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}
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static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j,
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unsigned val)
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{
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edma_write(ctlr, offset + ((i*2 + j) << 2), val);
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}
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static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset)
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{
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return edma_read(ctlr, EDMA_SHADOW0 + offset);
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}
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static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset,
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int i)
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{
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return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2));
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}
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static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val)
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{
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edma_write(ctlr, EDMA_SHADOW0 + offset, val);
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}
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static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i,
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unsigned val)
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{
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edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val);
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}
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static inline unsigned int edma_parm_read(unsigned ctlr, int offset,
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int param_no)
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{
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return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5));
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}
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static inline void edma_parm_write(unsigned ctlr, int offset, int param_no,
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unsigned val)
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{
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edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val);
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}
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static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no,
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unsigned and, unsigned or)
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{
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edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or);
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}
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static inline void edma_parm_and(unsigned ctlr, int offset, int param_no,
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unsigned and)
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{
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edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and);
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}
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static inline void edma_parm_or(unsigned ctlr, int offset, int param_no,
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unsigned or)
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{
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edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or);
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}
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static inline void set_bits(int offset, int len, unsigned long *p)
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{
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for (; len > 0; len--)
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set_bit(offset + (len - 1), p);
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}
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static inline void clear_bits(int offset, int len, unsigned long *p)
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{
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for (; len > 0; len--)
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clear_bit(offset + (len - 1), p);
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}
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/*****************************************************************************/
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/* actual number of DMA channels and slots on this silicon */
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struct edma {
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struct device *dev;
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void __iomem *base;
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/* how many dma resources of each type */
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unsigned num_channels;
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unsigned num_region;
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@ -265,7 +148,122 @@ struct edma {
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void *data;
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} intr_data[EDMA_MAX_DMACH];
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};
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/*****************************************************************************/
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static inline unsigned int edma_read(struct edma *cc, int offset)
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{
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return (unsigned int)__raw_readl(cc->base + offset);
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}
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static inline void edma_write(struct edma *cc, int offset, int val)
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{
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__raw_writel(val, cc->base + offset);
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}
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static inline void edma_modify(struct edma *cc, int offset, unsigned and,
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unsigned or)
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{
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unsigned val = edma_read(cc, offset);
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val &= and;
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val |= or;
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edma_write(cc, offset, val);
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}
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static inline void edma_and(struct edma *cc, int offset, unsigned and)
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{
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unsigned val = edma_read(cc, offset);
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val &= and;
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edma_write(cc, offset, val);
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}
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static inline void edma_or(struct edma *cc, int offset, unsigned or)
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{
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unsigned val = edma_read(cc, offset);
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val |= or;
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edma_write(cc, offset, val);
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}
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static inline unsigned int edma_read_array(struct edma *cc, int offset, int i)
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{
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return edma_read(cc, offset + (i << 2));
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}
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static inline void edma_write_array(struct edma *cc, int offset, int i,
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unsigned val)
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{
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edma_write(cc, offset + (i << 2), val);
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}
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static inline void edma_modify_array(struct edma *cc, int offset, int i,
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unsigned and, unsigned or)
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{
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edma_modify(cc, offset + (i << 2), and, or);
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}
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static inline void edma_or_array(struct edma *cc, int offset, int i, unsigned or)
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{
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edma_or(cc, offset + (i << 2), or);
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}
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static inline void edma_or_array2(struct edma *cc, int offset, int i, int j,
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unsigned or)
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{
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edma_or(cc, offset + ((i*2 + j) << 2), or);
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}
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static inline void edma_write_array2(struct edma *cc, int offset, int i, int j,
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unsigned val)
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{
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edma_write(cc, offset + ((i*2 + j) << 2), val);
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}
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static inline unsigned int edma_shadow0_read(struct edma *cc, int offset)
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{
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return edma_read(cc, EDMA_SHADOW0 + offset);
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}
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static inline unsigned int edma_shadow0_read_array(struct edma *cc, int offset,
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int i)
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{
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return edma_read(cc, EDMA_SHADOW0 + offset + (i << 2));
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}
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static inline void edma_shadow0_write(struct edma *cc, int offset, unsigned val)
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{
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edma_write(cc, EDMA_SHADOW0 + offset, val);
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}
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static inline void edma_shadow0_write_array(struct edma *cc, int offset, int i,
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unsigned val)
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{
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edma_write(cc, EDMA_SHADOW0 + offset + (i << 2), val);
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}
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static inline unsigned int edma_parm_read(struct edma *cc, int offset,
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int param_no)
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{
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return edma_read(cc, EDMA_PARM + offset + (param_no << 5));
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}
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static inline void edma_parm_write(struct edma *cc, int offset, int param_no,
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unsigned val)
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{
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edma_write(cc, EDMA_PARM + offset + (param_no << 5), val);
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}
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static inline void edma_parm_modify(struct edma *cc, int offset, int param_no,
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unsigned and, unsigned or)
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{
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edma_modify(cc, EDMA_PARM + offset + (param_no << 5), and, or);
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}
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static inline void edma_parm_and(struct edma *cc, int offset, int param_no,
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unsigned and)
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{
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edma_and(cc, EDMA_PARM + offset + (param_no << 5), and);
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}
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static inline void edma_parm_or(struct edma *cc, int offset, int param_no,
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unsigned or)
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{
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edma_or(cc, EDMA_PARM + offset + (param_no << 5), or);
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}
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static inline void set_bits(int offset, int len, unsigned long *p)
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{
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for (; len > 0; len--)
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set_bit(offset + (len - 1), p);
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}
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static inline void clear_bits(int offset, int len, unsigned long *p)
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{
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for (; len > 0; len--)
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clear_bit(offset + (len - 1), p);
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}
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/*****************************************************************************/
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static struct edma *edma_cc[EDMA_MAX_CC];
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static int arch_num_cc;
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@ -282,26 +280,25 @@ static const struct of_device_id edma_of_ids[] = {
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/*****************************************************************************/
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static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
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enum dma_event_q queue_no)
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static void map_dmach_queue(struct edma *cc, unsigned ch_no,
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enum dma_event_q queue_no)
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{
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int bit = (ch_no & 0x7) * 4;
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/* default to low priority queue */
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if (queue_no == EVENTQ_DEFAULT)
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queue_no = edma_cc[ctlr]->default_queue;
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queue_no = cc->default_queue;
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queue_no &= 7;
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edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
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~(0x7 << bit), queue_no << bit);
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edma_modify_array(cc, EDMA_DMAQNUM, (ch_no >> 3),
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~(0x7 << bit), queue_no << bit);
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}
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static void assign_priority_to_queue(unsigned ctlr, int queue_no,
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int priority)
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static void assign_priority_to_queue(struct edma *cc, int queue_no,
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int priority)
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{
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int bit = queue_no * 4;
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edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit),
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((priority & 0x7) << bit));
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edma_modify(cc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit));
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}
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/**
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@ -315,35 +312,30 @@ static void assign_priority_to_queue(unsigned ctlr, int queue_no,
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* included in that particular EDMA variant (Eg : dm646x)
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*
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*/
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static void map_dmach_param(unsigned ctlr)
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static void map_dmach_param(struct edma *cc)
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{
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int i;
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for (i = 0; i < EDMA_MAX_DMACH; i++)
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edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5));
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edma_write_array(cc, EDMA_DCHMAP , i , (i << 5));
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}
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static inline void
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setup_dma_interrupt(unsigned lch,
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static inline void setup_dma_interrupt(struct edma *cc, unsigned lch,
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void (*callback)(unsigned channel, u16 ch_status, void *data),
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void *data)
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{
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unsigned ctlr;
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ctlr = EDMA_CTLR(lch);
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lch = EDMA_CHAN_SLOT(lch);
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if (!callback)
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edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
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BIT(lch & 0x1f));
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edma_shadow0_write_array(cc, SH_IECR, lch >> 5,
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BIT(lch & 0x1f));
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edma_cc[ctlr]->intr_data[lch].callback = callback;
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edma_cc[ctlr]->intr_data[lch].data = data;
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cc->intr_data[lch].callback = callback;
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cc->intr_data[lch].data = data;
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if (callback) {
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edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
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BIT(lch & 0x1f));
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edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
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BIT(lch & 0x1f));
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edma_shadow0_write_array(cc, SH_ICR, lch >> 5, BIT(lch & 0x1f));
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edma_shadow0_write_array(cc, SH_IESR, lch >> 5,
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BIT(lch & 0x1f));
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}
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}
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@ -366,15 +358,15 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
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dev_dbg(cc->dev, "dma_irq_handler\n");
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sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 0);
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sh_ipr = edma_shadow0_read_array(cc, SH_IPR, 0);
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if (!sh_ipr) {
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sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 1);
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sh_ipr = edma_shadow0_read_array(cc, SH_IPR, 1);
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if (!sh_ipr)
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return IRQ_NONE;
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sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 1);
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sh_ier = edma_shadow0_read_array(cc, SH_IER, 1);
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bank = 1;
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} else {
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sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 0);
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sh_ier = edma_shadow0_read_array(cc, SH_IER, 0);
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bank = 0;
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}
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@ -390,8 +382,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
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if (sh_ier & BIT(slot)) {
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channel = (bank << 5) | slot;
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/* Clear the corresponding IPR bits */
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edma_shadow0_write_array(ctlr, SH_ICR, bank,
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BIT(slot));
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edma_shadow0_write_array(cc, SH_ICR, bank, BIT(slot));
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if (cc->intr_data[channel].callback)
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cc->intr_data[channel].callback(
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EDMA_CTLR_CHAN(ctlr, channel),
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@ -400,7 +391,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
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}
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} while (sh_ipr);
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edma_shadow0_write(ctlr, SH_IEVAL, 1);
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edma_shadow0_write(cc, SH_IEVAL, 1);
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return IRQ_HANDLED;
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}
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@ -422,30 +413,30 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
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dev_dbg(cc->dev, "dma_ccerr_handler\n");
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if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
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(edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
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(edma_read(ctlr, EDMA_QEMR) == 0) &&
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(edma_read(ctlr, EDMA_CCERR) == 0))
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if ((edma_read_array(cc, EDMA_EMR, 0) == 0) &&
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(edma_read_array(cc, EDMA_EMR, 1) == 0) &&
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(edma_read(cc, EDMA_QEMR) == 0) &&
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(edma_read(cc, EDMA_CCERR) == 0))
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return IRQ_NONE;
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while (1) {
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int j = -1;
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if (edma_read_array(ctlr, EDMA_EMR, 0))
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if (edma_read_array(cc, EDMA_EMR, 0))
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j = 0;
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else if (edma_read_array(ctlr, EDMA_EMR, 1))
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else if (edma_read_array(cc, EDMA_EMR, 1))
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j = 1;
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if (j >= 0) {
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dev_dbg(cc->dev, "EMR%d %08x\n", j,
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edma_read_array(ctlr, EDMA_EMR, j));
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edma_read_array(cc, EDMA_EMR, j));
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for (i = 0; i < 32; i++) {
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int k = (j << 5) + i;
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if (edma_read_array(ctlr, EDMA_EMR, j) &
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if (edma_read_array(cc, EDMA_EMR, j) &
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BIT(i)) {
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/* Clear the corresponding EMR bits */
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edma_write_array(ctlr, EDMA_EMCR, j,
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BIT(i));
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edma_write_array(cc, EDMA_EMCR, j,
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BIT(i));
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/* Clear any SER */
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edma_shadow0_write_array(ctlr, SH_SECR,
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edma_shadow0_write_array(cc, SH_SECR,
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j, BIT(i));
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if (cc->intr_data[k].callback) {
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cc->intr_data[k].callback(
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@ -455,44 +446,44 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
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}
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}
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}
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} else if (edma_read(ctlr, EDMA_QEMR)) {
|
||||
} else if (edma_read(cc, EDMA_QEMR)) {
|
||||
dev_dbg(cc->dev, "QEMR %02x\n",
|
||||
edma_read(ctlr, EDMA_QEMR));
|
||||
edma_read(cc, EDMA_QEMR));
|
||||
for (i = 0; i < 8; i++) {
|
||||
if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) {
|
||||
if (edma_read(cc, EDMA_QEMR) & BIT(i)) {
|
||||
/* Clear the corresponding IPR bits */
|
||||
edma_write(ctlr, EDMA_QEMCR, BIT(i));
|
||||
edma_shadow0_write(ctlr, SH_QSECR,
|
||||
BIT(i));
|
||||
edma_write(cc, EDMA_QEMCR, BIT(i));
|
||||
edma_shadow0_write(cc, SH_QSECR,
|
||||
BIT(i));
|
||||
|
||||
/* NOTE: not reported!! */
|
||||
}
|
||||
}
|
||||
} else if (edma_read(ctlr, EDMA_CCERR)) {
|
||||
} else if (edma_read(cc, EDMA_CCERR)) {
|
||||
dev_dbg(cc->dev, "CCERR %08x\n",
|
||||
edma_read(ctlr, EDMA_CCERR));
|
||||
edma_read(cc, EDMA_CCERR));
|
||||
/* FIXME: CCERR.BIT(16) ignored! much better
|
||||
* to just write CCERRCLR with CCERR value...
|
||||
*/
|
||||
for (i = 0; i < 8; i++) {
|
||||
if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) {
|
||||
if (edma_read(cc, EDMA_CCERR) & BIT(i)) {
|
||||
/* Clear the corresponding IPR bits */
|
||||
edma_write(ctlr, EDMA_CCERRCLR, BIT(i));
|
||||
edma_write(cc, EDMA_CCERRCLR, BIT(i));
|
||||
|
||||
/* NOTE: not reported!! */
|
||||
}
|
||||
}
|
||||
}
|
||||
if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
|
||||
(edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
|
||||
(edma_read(ctlr, EDMA_QEMR) == 0) &&
|
||||
(edma_read(ctlr, EDMA_CCERR) == 0))
|
||||
if ((edma_read_array(cc, EDMA_EMR, 0) == 0) &&
|
||||
(edma_read_array(cc, EDMA_EMR, 1) == 0) &&
|
||||
(edma_read(cc, EDMA_QEMR) == 0) &&
|
||||
(edma_read(cc, EDMA_CCERR) == 0))
|
||||
break;
|
||||
cnt++;
|
||||
if (cnt > 10)
|
||||
break;
|
||||
}
|
||||
edma_write(ctlr, EDMA_EEVAL, 1);
|
||||
edma_write(cc, EDMA_EEVAL, 1);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
@ -629,18 +620,19 @@ int edma_alloc_channel(int channel,
|
||||
}
|
||||
|
||||
/* ensure access through shadow region 0 */
|
||||
edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
|
||||
edma_or_array2(edma_cc[ctlr], EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
|
||||
|
||||
/* ensure no events are pending */
|
||||
edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
|
||||
memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
|
||||
&dummy_paramset, PARM_SIZE);
|
||||
memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(channel), &dummy_paramset,
|
||||
PARM_SIZE);
|
||||
|
||||
if (callback)
|
||||
setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel),
|
||||
callback, data);
|
||||
setup_dma_interrupt(edma_cc[ctlr],
|
||||
EDMA_CTLR_CHAN(ctlr, channel), callback,
|
||||
data);
|
||||
|
||||
map_dmach_queue(ctlr, channel, eventq_no);
|
||||
map_dmach_queue(edma_cc[ctlr], channel, eventq_no);
|
||||
|
||||
return EDMA_CTLR_CHAN(ctlr, channel);
|
||||
}
|
||||
@ -668,11 +660,11 @@ void edma_free_channel(unsigned channel)
|
||||
if (channel >= edma_cc[ctlr]->num_channels)
|
||||
return;
|
||||
|
||||
setup_dma_interrupt(channel, NULL, NULL);
|
||||
setup_dma_interrupt(edma_cc[ctlr], channel, NULL, NULL);
|
||||
/* REVISIT should probably take out of shadow region 0 */
|
||||
|
||||
memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
|
||||
&dummy_paramset, PARM_SIZE);
|
||||
memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(channel), &dummy_paramset,
|
||||
PARM_SIZE);
|
||||
clear_bit(channel, edma_cc[ctlr]->edma_inuse);
|
||||
}
|
||||
EXPORT_SYMBOL(edma_free_channel);
|
||||
@ -716,8 +708,8 @@ int edma_alloc_slot(unsigned ctlr, int slot)
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
|
||||
&dummy_paramset, PARM_SIZE);
|
||||
memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(slot), &dummy_paramset,
|
||||
PARM_SIZE);
|
||||
|
||||
return EDMA_CTLR_CHAN(ctlr, slot);
|
||||
}
|
||||
@ -742,8 +734,8 @@ void edma_free_slot(unsigned slot)
|
||||
slot >= edma_cc[ctlr]->num_slots)
|
||||
return;
|
||||
|
||||
memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
|
||||
&dummy_paramset, PARM_SIZE);
|
||||
memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(slot), &dummy_paramset,
|
||||
PARM_SIZE);
|
||||
clear_bit(slot, edma_cc[ctlr]->edma_inuse);
|
||||
}
|
||||
EXPORT_SYMBOL(edma_free_slot);
|
||||
@ -768,7 +760,7 @@ dma_addr_t edma_get_position(unsigned slot, bool dst)
|
||||
offs = PARM_OFFSET(slot);
|
||||
offs += dst ? PARM_DST : PARM_SRC;
|
||||
|
||||
return edma_read(ctlr, offs);
|
||||
return edma_read(edma_cc[ctlr], offs);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -791,7 +783,7 @@ void edma_link(unsigned from, unsigned to)
|
||||
return;
|
||||
if (to >= edma_cc[ctlr_to]->num_slots)
|
||||
return;
|
||||
edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
|
||||
edma_parm_modify(edma_cc[ctlr_from], PARM_LINK_BCNTRLD, from, 0xffff0000,
|
||||
PARM_OFFSET(to));
|
||||
}
|
||||
EXPORT_SYMBOL(edma_link);
|
||||
@ -819,8 +811,7 @@ void edma_write_slot(unsigned slot, const struct edmacc_param *param)
|
||||
|
||||
if (slot >= edma_cc[ctlr]->num_slots)
|
||||
return;
|
||||
memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
|
||||
PARM_SIZE);
|
||||
memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(slot), param, PARM_SIZE);
|
||||
}
|
||||
EXPORT_SYMBOL(edma_write_slot);
|
||||
|
||||
@ -841,8 +832,8 @@ void edma_read_slot(unsigned slot, struct edmacc_param *param)
|
||||
|
||||
if (slot >= edma_cc[ctlr]->num_slots)
|
||||
return;
|
||||
memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
|
||||
PARM_SIZE);
|
||||
memcpy_fromio(param, edma_cc[ctlr]->base + PARM_OFFSET(slot),
|
||||
PARM_SIZE);
|
||||
}
|
||||
EXPORT_SYMBOL(edma_read_slot);
|
||||
|
||||
@ -867,7 +858,8 @@ void edma_pause(unsigned channel)
|
||||
if (channel < edma_cc[ctlr]->num_channels) {
|
||||
unsigned int mask = BIT(channel & 0x1f);
|
||||
|
||||
edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
|
||||
edma_shadow0_write_array(edma_cc[ctlr], SH_EECR, channel >> 5,
|
||||
mask);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(edma_pause);
|
||||
@ -888,7 +880,8 @@ void edma_resume(unsigned channel)
|
||||
if (channel < edma_cc[ctlr]->num_channels) {
|
||||
unsigned int mask = BIT(channel & 0x1f);
|
||||
|
||||
edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
|
||||
edma_shadow0_write_array(edma_cc[ctlr], SH_EESR, channel >> 5,
|
||||
mask);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(edma_resume);
|
||||
@ -902,10 +895,11 @@ int edma_trigger_channel(unsigned channel)
|
||||
channel = EDMA_CHAN_SLOT(channel);
|
||||
mask = BIT(channel & 0x1f);
|
||||
|
||||
edma_shadow0_write_array(ctlr, SH_ESR, (channel >> 5), mask);
|
||||
edma_shadow0_write_array(edma_cc[ctlr], SH_ESR, (channel >> 5), mask);
|
||||
|
||||
pr_debug("EDMA: ESR%d %08x\n", (channel >> 5),
|
||||
edma_shadow0_read_array(ctlr, SH_ESR, (channel >> 5)));
|
||||
edma_shadow0_read_array(edma_cc[ctlr], SH_ESR,
|
||||
(channel >> 5)));
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(edma_trigger_channel);
|
||||
@ -929,28 +923,29 @@ int edma_start(unsigned channel)
|
||||
channel = EDMA_CHAN_SLOT(channel);
|
||||
|
||||
if (channel < edma_cc[ctlr]->num_channels) {
|
||||
struct edma *cc = edma_cc[ctlr];
|
||||
int j = channel >> 5;
|
||||
unsigned int mask = BIT(channel & 0x1f);
|
||||
|
||||
/* EDMA channels without event association */
|
||||
if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
|
||||
if (test_bit(channel, cc->edma_unused)) {
|
||||
pr_debug("EDMA: ESR%d %08x\n", j,
|
||||
edma_shadow0_read_array(ctlr, SH_ESR, j));
|
||||
edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
|
||||
edma_shadow0_read_array(cc, SH_ESR, j));
|
||||
edma_shadow0_write_array(cc, SH_ESR, j, mask);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* EDMA channel with event association */
|
||||
pr_debug("EDMA: ER%d %08x\n", j,
|
||||
edma_shadow0_read_array(ctlr, SH_ER, j));
|
||||
edma_shadow0_read_array(cc, SH_ER, j));
|
||||
/* Clear any pending event or error */
|
||||
edma_write_array(ctlr, EDMA_ECR, j, mask);
|
||||
edma_write_array(ctlr, EDMA_EMCR, j, mask);
|
||||
edma_write_array(cc, EDMA_ECR, j, mask);
|
||||
edma_write_array(cc, EDMA_EMCR, j, mask);
|
||||
/* Clear any SER */
|
||||
edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
|
||||
edma_shadow0_write_array(ctlr, SH_EESR, j, mask);
|
||||
edma_shadow0_write_array(cc, SH_SECR, j, mask);
|
||||
edma_shadow0_write_array(cc, SH_EESR, j, mask);
|
||||
pr_debug("EDMA: EER%d %08x\n", j,
|
||||
edma_shadow0_read_array(ctlr, SH_EER, j));
|
||||
edma_shadow0_read_array(cc, SH_EER, j));
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -975,19 +970,20 @@ void edma_stop(unsigned channel)
|
||||
channel = EDMA_CHAN_SLOT(channel);
|
||||
|
||||
if (channel < edma_cc[ctlr]->num_channels) {
|
||||
struct edma *cc = edma_cc[ctlr];
|
||||
int j = channel >> 5;
|
||||
unsigned int mask = BIT(channel & 0x1f);
|
||||
|
||||
edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
|
||||
edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
|
||||
edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
|
||||
edma_write_array(ctlr, EDMA_EMCR, j, mask);
|
||||
edma_shadow0_write_array(cc, SH_EECR, j, mask);
|
||||
edma_shadow0_write_array(cc, SH_ECR, j, mask);
|
||||
edma_shadow0_write_array(cc, SH_SECR, j, mask);
|
||||
edma_write_array(cc, EDMA_EMCR, j, mask);
|
||||
|
||||
/* clear possibly pending completion interrupt */
|
||||
edma_shadow0_write_array(ctlr, SH_ICR, j, mask);
|
||||
edma_shadow0_write_array(cc, SH_ICR, j, mask);
|
||||
|
||||
pr_debug("EDMA: EER%d %08x\n", j,
|
||||
edma_shadow0_read_array(ctlr, SH_EER, j));
|
||||
edma_shadow0_read_array(cc, SH_EER, j));
|
||||
|
||||
/* REVISIT: consider guarding against inappropriate event
|
||||
* chaining by overwriting with dummy_paramset.
|
||||
@ -1017,17 +1013,18 @@ void edma_clean_channel(unsigned channel)
|
||||
channel = EDMA_CHAN_SLOT(channel);
|
||||
|
||||
if (channel < edma_cc[ctlr]->num_channels) {
|
||||
struct edma *cc = edma_cc[ctlr];
|
||||
int j = (channel >> 5);
|
||||
unsigned int mask = BIT(channel & 0x1f);
|
||||
|
||||
pr_debug("EDMA: EMR%d %08x\n", j,
|
||||
edma_read_array(ctlr, EDMA_EMR, j));
|
||||
edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
|
||||
edma_read_array(cc, EDMA_EMR, j));
|
||||
edma_shadow0_write_array(cc, SH_ECR, j, mask);
|
||||
/* Clear the corresponding EMR bits */
|
||||
edma_write_array(ctlr, EDMA_EMCR, j, mask);
|
||||
edma_write_array(cc, EDMA_EMCR, j, mask);
|
||||
/* Clear any SER */
|
||||
edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
|
||||
edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
|
||||
edma_shadow0_write_array(cc, SH_SECR, j, mask);
|
||||
edma_write(cc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(edma_clean_channel);
|
||||
@ -1056,7 +1053,7 @@ void edma_assign_channel_eventq(unsigned channel, enum dma_event_q eventq_no)
|
||||
if (eventq_no >= edma_cc[ctlr]->num_tc)
|
||||
return;
|
||||
|
||||
map_dmach_queue(ctlr, channel, eventq_no);
|
||||
map_dmach_queue(edma_cc[ctlr], channel, eventq_no);
|
||||
}
|
||||
EXPORT_SYMBOL(edma_assign_channel_eventq);
|
||||
|
||||
@ -1068,7 +1065,7 @@ static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
|
||||
s8 (*queue_priority_map)[2];
|
||||
|
||||
/* Decode the eDMA3 configuration from CCCFG register */
|
||||
cccfg = edma_read(cc_id, EDMA_CCCFG);
|
||||
cccfg = edma_read(edma_cc, EDMA_CCCFG);
|
||||
|
||||
value = GET_NUM_REGN(cccfg);
|
||||
edma_cc->num_region = BIT(value);
|
||||
@ -1281,10 +1278,6 @@ static int edma_probe(struct platform_device *pdev)
|
||||
}
|
||||
}
|
||||
|
||||
edmacc_regs_base[dev_id] = devm_ioremap_resource(dev, mem);
|
||||
if (IS_ERR(edmacc_regs_base[dev_id]))
|
||||
return PTR_ERR(edmacc_regs_base[dev_id]);
|
||||
|
||||
edma_cc[dev_id] = devm_kzalloc(dev, sizeof(struct edma), GFP_KERNEL);
|
||||
if (!edma_cc[dev_id])
|
||||
return -ENOMEM;
|
||||
@ -1294,6 +1287,10 @@ static int edma_probe(struct platform_device *pdev)
|
||||
cc->id = dev_id;
|
||||
dev_set_drvdata(dev, cc);
|
||||
|
||||
cc->base = devm_ioremap_resource(dev, mem);
|
||||
if (IS_ERR(cc->base))
|
||||
return PTR_ERR(cc->base);
|
||||
|
||||
/* Get eDMA3 configuration from IP */
|
||||
ret = edma_setup_from_hw(dev, info, cc, dev_id);
|
||||
if (ret)
|
||||
@ -1301,11 +1298,9 @@ static int edma_probe(struct platform_device *pdev)
|
||||
|
||||
cc->default_queue = info->default_queue;
|
||||
|
||||
dev_dbg(dev, "DMA REG BASE ADDR=%p\n", edmacc_regs_base[dev_id]);
|
||||
|
||||
for (i = 0; i < cc->num_slots; i++)
|
||||
memcpy_toio(edmacc_regs_base[dev_id] + PARM_OFFSET(i),
|
||||
&dummy_paramset, PARM_SIZE);
|
||||
memcpy_toio(cc->base + PARM_OFFSET(i), &dummy_paramset,
|
||||
PARM_SIZE);
|
||||
|
||||
/* Mark all channels as unused */
|
||||
memset(cc->edma_unused, 0xff, sizeof(cc->edma_unused));
|
||||
@ -1373,23 +1368,23 @@ static int edma_probe(struct platform_device *pdev)
|
||||
}
|
||||
|
||||
for (i = 0; i < cc->num_channels; i++)
|
||||
map_dmach_queue(dev_id, i, info->default_queue);
|
||||
map_dmach_queue(cc, i, info->default_queue);
|
||||
|
||||
queue_priority_mapping = info->queue_priority_mapping;
|
||||
|
||||
/* Event queue priority mapping */
|
||||
for (i = 0; queue_priority_mapping[i][0] != -1; i++)
|
||||
assign_priority_to_queue(dev_id, queue_priority_mapping[i][0],
|
||||
assign_priority_to_queue(cc, queue_priority_mapping[i][0],
|
||||
queue_priority_mapping[i][1]);
|
||||
|
||||
/* Map the channel to param entry if channel mapping logic exist */
|
||||
if (edma_read(dev_id, EDMA_CCCFG) & CHMAP_EXIST)
|
||||
map_dmach_param(dev_id);
|
||||
if (edma_read(cc, EDMA_CCCFG) & CHMAP_EXIST)
|
||||
map_dmach_param(cc);
|
||||
|
||||
for (i = 0; i < cc->num_region; i++) {
|
||||
edma_write_array2(dev_id, EDMA_DRAE, i, 0, 0x0);
|
||||
edma_write_array2(dev_id, EDMA_DRAE, i, 1, 0x0);
|
||||
edma_write_array(dev_id, EDMA_QRAE, i, 0x0);
|
||||
edma_write_array2(cc, EDMA_DRAE, i, 0, 0x0);
|
||||
edma_write_array2(cc, EDMA_DRAE, i, 1, 0x0);
|
||||
edma_write_array(cc, EDMA_QRAE, i, 0x0);
|
||||
}
|
||||
cc->info = info;
|
||||
arch_num_cc++;
|
||||
@ -1412,20 +1407,19 @@ static int edma_pm_resume(struct device *dev)
|
||||
|
||||
/* Event queue priority mapping */
|
||||
for (i = 0; queue_priority_mapping[i][0] != -1; i++)
|
||||
assign_priority_to_queue(cc->id, queue_priority_mapping[i][0],
|
||||
assign_priority_to_queue(cc, queue_priority_mapping[i][0],
|
||||
queue_priority_mapping[i][1]);
|
||||
|
||||
/* Map the channel to param entry if channel mapping logic */
|
||||
if (edma_read(cc->id, EDMA_CCCFG) & CHMAP_EXIST)
|
||||
map_dmach_param(cc->id);
|
||||
if (edma_read(cc, EDMA_CCCFG) & CHMAP_EXIST)
|
||||
map_dmach_param(cc);
|
||||
|
||||
for (i = 0; i < cc->num_channels; i++) {
|
||||
if (test_bit(i, cc->edma_inuse)) {
|
||||
/* ensure access through shadow region 0 */
|
||||
edma_or_array2(cc->id, EDMA_DRAE, 0, i >> 5,
|
||||
BIT(i & 0x1f));
|
||||
edma_or_array2(cc, EDMA_DRAE, 0, i >> 5, BIT(i & 0x1f));
|
||||
|
||||
setup_dma_interrupt(EDMA_CTLR_CHAN(cc->id, i),
|
||||
setup_dma_interrupt(cc, EDMA_CTLR_CHAN(cc->id, i),
|
||||
cc->intr_data[i].callback,
|
||||
cc->intr_data[i].data);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user