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[PATCH] mv643xx_eth: Move #defines of constants to mv643xx_eth.h
Signed-off-by: Dale Farnsworth <dale@farnsworth.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Dale Farnsworth
Jeff Garzik
parent
ff561eef9f
commit
7303fde88a
@ -50,37 +50,6 @@
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#include <asm/delay.h>
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#include "mv643xx_eth.h"
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/*
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* The first part is the high level driver of the gigE ethernet ports.
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*/
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/* Constants */
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#define VLAN_HLEN 4
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#define FCS_LEN 4
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#define DMA_ALIGN 8 /* hw requires 8-byte alignment */
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#define HW_IP_ALIGN 2 /* hw aligns IP header */
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#define WRAP HW_IP_ALIGN + ETH_HLEN + VLAN_HLEN + FCS_LEN
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#define RX_SKB_SIZE ((dev->mtu + WRAP + 7) & ~0x7)
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#define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */
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#define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */
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#define INT_UNMASK_ALL 0x0007ffff
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#define INT_UNMASK_ALL_EXT 0x0011ffff
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#define INT_MASK_ALL 0x00000000
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#define INT_MASK_ALL_EXT 0x00000000
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#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
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#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
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#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
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#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
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#else
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#define MAX_DESCS_PER_SKB 1
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#endif
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#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
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#define PHY_WAIT_MICRO_SECONDS 10
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/* Static function declarations */
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static void eth_port_uc_addr_get(struct net_device *dev,
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unsigned char *MacAddr);
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@ -182,24 +151,24 @@ static void mv643xx_eth_rx_task(void *data)
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panic("%s: Error in test_set_bit / clear_bit", dev->name);
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while (mp->rx_desc_count < (mp->rx_ring_size - 5)) {
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skb = dev_alloc_skb(RX_SKB_SIZE + DMA_ALIGN);
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skb = dev_alloc_skb(ETH_RX_SKB_SIZE + ETH_DMA_ALIGN);
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if (!skb)
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break;
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mp->rx_desc_count++;
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unaligned = (u32)skb->data & (DMA_ALIGN - 1);
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unaligned = (u32)skb->data & (ETH_DMA_ALIGN - 1);
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if (unaligned)
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skb_reserve(skb, DMA_ALIGN - unaligned);
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skb_reserve(skb, ETH_DMA_ALIGN - unaligned);
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pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
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pkt_info.byte_cnt = RX_SKB_SIZE;
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pkt_info.buf_ptr = dma_map_single(NULL, skb->data, RX_SKB_SIZE,
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DMA_FROM_DEVICE);
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pkt_info.byte_cnt = ETH_RX_SKB_SIZE;
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pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
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ETH_RX_SKB_SIZE, DMA_FROM_DEVICE);
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pkt_info.return_info = skb;
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if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
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printk(KERN_ERR
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"%s: Error allocating RX Ring\n", dev->name);
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break;
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}
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skb_reserve(skb, HW_IP_ALIGN);
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skb_reserve(skb, ETH_HW_IP_ALIGN);
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}
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clear_bit(0, &mp->rx_task_busy);
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/*
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@ -375,7 +344,7 @@ int mv643xx_eth_free_tx_descs(struct net_device *dev, int force)
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spin_unlock_irqrestore(&mp->lock, flags);
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if (cmd_sts & BIT0) {
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if (cmd_sts & ETH_ERROR_SUMMARY) {
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printk("%s: Error in TX\n", dev->name);
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mp->stats.tx_errors++;
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}
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@ -562,12 +531,12 @@ static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id,
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/* Read interrupt cause registers */
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eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) &
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INT_UNMASK_ALL;
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ETH_INT_UNMASK_ALL;
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if (eth_int_cause & BIT1)
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eth_int_cause_ext = mv_read(
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MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
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INT_UNMASK_ALL_EXT;
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ETH_INT_UNMASK_ALL_EXT;
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#ifdef MV643XX_NAPI
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if (!(eth_int_cause & 0x0007fffd)) {
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@ -591,7 +560,7 @@ static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id,
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if (netif_rx_schedule_prep(dev)) {
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/* Mask all the interrupts */
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mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
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INT_MASK_ALL);
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ETH_INT_MASK_ALL);
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/* wait for previous write to complete */
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mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
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__netif_rx_schedule(dev);
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@ -619,6 +588,7 @@ static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id,
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#endif
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#endif
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}
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/* PHY status changed */
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if (eth_int_cause_ext & (BIT16 | BIT20)) {
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struct ethtool_cmd cmd;
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@ -966,10 +936,10 @@ static int mv643xx_eth_open(struct net_device *dev)
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/* Unmask phy and link status changes interrupts */
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mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
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INT_UNMASK_ALL_EXT);
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ETH_INT_UNMASK_ALL_EXT);
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/* Unmask RX buffer and TX end interrupt */
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mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_UNMASK_ALL);
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mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
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return 0;
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@ -1049,7 +1019,7 @@ static int mv643xx_eth_stop(struct net_device *dev)
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unsigned int port_num = mp->port_num;
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/* Mask all interrupts on ethernet port */
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mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_MASK_ALL);
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mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
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/* wait for previous write to complete */
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mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
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@ -1110,7 +1080,7 @@ static int mv643xx_poll(struct net_device *dev, int *budget)
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mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
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mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
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mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
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INT_UNMASK_ALL);
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ETH_INT_UNMASK_ALL);
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}
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return done ? 0 : 1;
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@ -1325,13 +1295,13 @@ static void mv643xx_netpoll(struct net_device *netdev)
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struct mv643xx_private *mp = netdev_priv(netdev);
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int port_num = mp->port_num;
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mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_MASK_ALL);
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mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
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/* wait for previous write to complete */
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mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
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mv643xx_eth_int_handler(netdev->irq, netdev, NULL);
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mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_UNMASK_ALL);
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mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
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}
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#endif
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@ -74,21 +74,40 @@
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#define MV643XX_RX_COAL 100
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#endif
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/*
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* The second part is the low level driver of the gigE ethernet ports.
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*/
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#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
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#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
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#else
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#define MAX_DESCS_PER_SKB 1
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#endif
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/*
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* Header File for : MV-643xx network interface header
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*
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* DESCRIPTION:
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* This header file contains macros typedefs and function declaration for
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* the Marvell Gig Bit Ethernet Controller.
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*
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* DEPENDENCIES:
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* None.
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*
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*/
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#define ETH_VLAN_HLEN 4
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#define ETH_FCS_LEN 4
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#define ETH_DMA_ALIGN 8 /* hw requires 8-byte alignment */
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#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
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#define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \
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ETH_VLAN_HLEN + ETH_FCS_LEN)
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#define ETH_RX_SKB_SIZE ((dev->mtu + ETH_WRAPPER_LEN + 7) & ~0x7)
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#define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */
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#define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */
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#define ETH_INT_CAUSE_RX_DONE (ETH_RX_QUEUES_ENABLED << 2)
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#define ETH_INT_CAUSE_RX_ERROR (ETH_RX_QUEUES_ENABLED << 9)
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#define ETH_INT_CAUSE_RX (ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR)
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#define ETH_INT_CAUSE_EXT 0x00000002
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#define ETH_INT_UNMASK_ALL (ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT)
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#define ETH_INT_CAUSE_TX_DONE (ETH_TX_QUEUES_ENABLED << 0)
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#define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8)
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#define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR)
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#define ETH_INT_CAUSE_PHY 0x00010000
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#define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY)
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#define ETH_INT_MASK_ALL 0x00000000
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#define ETH_INT_MASK_ALL_EXT 0x00000000
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#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
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#define PHY_WAIT_MICRO_SECONDS 10
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/* Buffer offset from buffer pointer */
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#define RX_BUF_OFFSET 0x2
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