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i2c: i2c-ocores: support for 16bit and 32bit IO
Some architectures supports only 16-bit or 32-bit read/write access to their IO space. Add a 'reg-io-width' platform and OF parameter which specifies the IO width to support these platforms. reg-io-width can be specified as 1, 2 or 4, and has a default value of 1 if it is unspecified. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
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@ -10,6 +10,7 @@ Required properties:
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Optional properties:
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Optional properties:
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- reg-shift : device register offsets are shifted by this value
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- reg-shift : device register offsets are shifted by this value
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- reg-io-width : io register width in bytes (1, 2 or 4)
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- regstep : deprecated, use reg-shift above
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- regstep : deprecated, use reg-shift above
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Example:
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Example:
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@ -23,6 +24,7 @@ Example:
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clock-frequency = <20000000>;
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clock-frequency = <20000000>;
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reg-shift = <0>; /* 8 bit registers */
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reg-shift = <0>; /* 8 bit registers */
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reg-io-width = <1>; /* 8 bit read/write */
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dummy@60 {
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dummy@60 {
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compatible = "dummy";
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compatible = "dummy";
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@ -30,6 +30,7 @@
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struct ocores_i2c {
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struct ocores_i2c {
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void __iomem *base;
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void __iomem *base;
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u32 reg_shift;
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u32 reg_shift;
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u32 reg_io_width;
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wait_queue_head_t wait;
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wait_queue_head_t wait;
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struct i2c_adapter adap;
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struct i2c_adapter adap;
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struct i2c_msg *msg;
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struct i2c_msg *msg;
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@ -72,12 +73,22 @@ struct ocores_i2c {
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static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
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static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
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{
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{
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iowrite8(value, i2c->base + (reg << i2c->reg_shift));
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if (i2c->reg_io_width == 4)
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iowrite32(value, i2c->base + (reg << i2c->reg_shift));
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else if (i2c->reg_io_width == 2)
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iowrite16(value, i2c->base + (reg << i2c->reg_shift));
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else
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iowrite8(value, i2c->base + (reg << i2c->reg_shift));
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}
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}
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static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
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static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
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{
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{
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return ioread8(i2c->base + (reg << i2c->reg_shift));
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if (i2c->reg_io_width == 4)
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return ioread32(i2c->base + (reg << i2c->reg_shift));
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else if (i2c->reg_io_width == 2)
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return ioread16(i2c->base + (reg << i2c->reg_shift));
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else
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return ioread8(i2c->base + (reg << i2c->reg_shift));
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}
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}
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static void ocores_process(struct ocores_i2c *i2c)
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static void ocores_process(struct ocores_i2c *i2c)
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@ -244,6 +255,8 @@ static int ocores_i2c_of_probe(struct platform_device *pdev,
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}
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}
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i2c->clock_khz = val / 1000;
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i2c->clock_khz = val / 1000;
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of_property_read_u32(pdev->dev.of_node, "reg-io-width",
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&i2c->reg_io_width);
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return 0;
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return 0;
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}
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}
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#else
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#else
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@ -286,6 +299,7 @@ static int __devinit ocores_i2c_probe(struct platform_device *pdev)
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pdata = pdev->dev.platform_data;
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pdata = pdev->dev.platform_data;
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if (pdata) {
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if (pdata) {
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i2c->reg_shift = pdata->reg_shift;
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i2c->reg_shift = pdata->reg_shift;
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i2c->reg_io_width = pdata->reg_io_width;
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i2c->clock_khz = pdata->clock_khz;
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i2c->clock_khz = pdata->clock_khz;
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} else {
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} else {
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ret = ocores_i2c_of_probe(pdev, i2c);
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ret = ocores_i2c_of_probe(pdev, i2c);
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@ -293,6 +307,9 @@ static int __devinit ocores_i2c_probe(struct platform_device *pdev)
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return ret;
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return ret;
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}
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}
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if (i2c->reg_io_width == 0)
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i2c->reg_io_width = 1; /* Set to default value */
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ocores_init(i2c);
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ocores_init(i2c);
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init_waitqueue_head(&i2c->wait);
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init_waitqueue_head(&i2c->wait);
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@ -13,6 +13,7 @@
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struct ocores_i2c_platform_data {
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struct ocores_i2c_platform_data {
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u32 reg_shift; /* register offset shift value */
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u32 reg_shift; /* register offset shift value */
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u32 reg_io_width; /* register io read/write width */
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u32 clock_khz; /* input clock in kHz */
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u32 clock_khz; /* input clock in kHz */
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u8 num_devices; /* number of devices in the devices list */
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u8 num_devices; /* number of devices in the devices list */
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struct i2c_board_info const *devices; /* devices connected to the bus */
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struct i2c_board_info const *devices; /* devices connected to the bus */
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