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ARM: dts: Add basic clocks for dm816x
The clocks on dm816x are a bit different from the other omap variants. The clocks are sourced from a FAPLL (Flying Adder PLL) unlike on other omaps. Other than that, it's a similar setup to am33xx with extra muxes and dividers that can be defined as existing component clocks. Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Tony Lindgren
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7800064ba5
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7383ca9255
250
arch/arm/boot/dts/dm816x-clocks.dtsi
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arch/arm/boot/dts/dm816x-clocks.dtsi
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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&scrm {
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main_fapll: main_fapll {
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#clock-cells = <1>;
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compatible = "ti,dm816-fapll-clock";
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reg = <0x400 0x40>;
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clocks = <&sys_clkin_ck &sys_clkin_ck>;
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clock-indices = <1>, <2>, <3>, <4>, <5>,
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<6>, <7>;
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clock-output-names = "main_pll_clk1",
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"main_pll_clk2",
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"main_pll_clk3",
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"main_pll_clk4",
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"main_pll_clk5",
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"main_pll_clk6",
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"main_pll_clk7";
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};
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ddr_fapll: ddr_fapll {
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#clock-cells = <1>;
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compatible = "ti,dm816-fapll-clock";
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reg = <0x440 0x30>;
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clocks = <&sys_clkin_ck &sys_clkin_ck>;
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clock-indices = <1>, <2>, <3>, <4>;
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clock-output-names = "ddr_pll_clk1",
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"ddr_pll_clk2",
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"ddr_pll_clk3",
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"ddr_pll_clk4";
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};
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video_fapll: video_fapll {
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#clock-cells = <1>;
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compatible = "ti,dm816-fapll-clock";
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reg = <0x470 0x30>;
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clocks = <&sys_clkin_ck &sys_clkin_ck>;
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clock-indices = <1>, <2>, <3>;
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clock-output-names = "video_pll_clk1",
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"video_pll_clk2",
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"video_pll_clk3";
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};
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audio_fapll: audio_fapll {
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#clock-cells = <1>;
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compatible = "ti,dm816-fapll-clock";
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reg = <0x4a0 0x30>;
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clocks = <&main_fapll 7>, < &sys_clkin_ck>;
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clock-indices = <1>, <2>, <3>, <4>, <5>;
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clock-output-names = "audio_pll_clk1",
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"audio_pll_clk2",
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"audio_pll_clk3",
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"audio_pll_clk4",
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"audio_pll_clk5";
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};
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};
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&scrm_clocks {
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secure_32k_ck: secure_32k_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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sys_32k_ck: sys_32k_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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tclkin_ck: tclkin_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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sys_clkin_ck: sys_clkin_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <27000000>;
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};
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};
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/* 0x48180000 */
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&prcm_clocks {
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clkout_pre_ck: clkout_pre_ck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1
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&audio_fapll 1>;
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reg = <0x100>;
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};
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clkout_div_ck: clkout_div_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&clkout_pre_ck>;
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ti,bit-shift = <3>;
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ti,max-div = <8>;
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reg = <0x100>;
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};
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clkout_ck: clkout_ck {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&clkout_div_ck>;
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ti,bit-shift = <7>;
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reg = <0x100>;
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};
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/* CM_DPLL clocks p1795 */
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sysclk1_ck: sysclk1_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&main_fapll 1>;
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ti,max-div = <7>;
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reg = <0x0300>;
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};
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sysclk2_ck: sysclk2_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&main_fapll 2>;
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ti,max-div = <7>;
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reg = <0x0304>;
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};
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sysclk3_ck: sysclk3_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&main_fapll 3>;
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ti,max-div = <7>;
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reg = <0x0308>;
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};
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sysclk4_ck: sysclk4_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&main_fapll 4>;
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ti,max-div = <1>;
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reg = <0x030c>;
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};
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sysclk5_ck: sysclk5_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&sysclk4_ck>;
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ti,max-div = <1>;
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reg = <0x0310>;
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};
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sysclk6_ck: sysclk6_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&main_fapll 4>;
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ti,dividers = <2>, <4>;
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reg = <0x0314>;
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};
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sysclk10_ck: sysclk10_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&ddr_fapll 2>;
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ti,max-div = <7>;
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reg = <0x0324>;
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};
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sysclk24_ck: sysclk24_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&main_fapll 5>;
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ti,max-div = <7>;
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reg = <0x03b4>;
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};
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mpu_ck: mpu_ck {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&sysclk2_ck>;
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ti,bit-shift = <1>;
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reg = <0x15dc>;
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};
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audio_pll_a_ck: audio_pll_a_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&audio_fapll 1>;
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ti,max-div = <7>;
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reg = <0x035c>;
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};
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sysclk18_ck: sysclk18_ck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&sys_32k_ck>, <&audio_pll_a_ck>;
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reg = <0x0378>;
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};
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timer1_fck: timer1_fck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
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reg = <0x0390>;
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};
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timer2_fck: timer2_fck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
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reg = <0x0394>;
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};
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timer3_fck: timer3_fck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
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reg = <0x0398>;
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};
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timer4_fck: timer4_fck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
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reg = <0x039c>;
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};
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timer5_fck: timer5_fck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
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reg = <0x03a0>;
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};
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timer6_fck: timer6_fck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
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reg = <0x03a4>;
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};
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timer7_fck: timer7_fck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
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reg = <0x03a8>;
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};
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};
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@ -384,3 +384,4 @@
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};
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};
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#include "dm816x-clocks.dtsi"
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