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[ARM] 3240/2: AT91RM9200 support for 2.6 (Core)

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Patch from SAN People

Following changes were made to clock.c:

1) Replaced <asm/hardware/clock.h> with <linux/clk.h>
2) Removed old unused clk_enable & clk_disable.
3) Replaced clk_use/clk_unuse with clk_enable/clk_disable.

Otherwise it's the same as the previous patch.

Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
SAN People 2006-01-09 17:05:41 +00:00 committed by Russell King
parent 50365c5786
commit 73a59c1c4a
32 changed files with 3280 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
arch/arm/Kconfig
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@ -210,6 +210,12 @@ config ARCH_AAEC2000
help
This enables support for systems based on the Agilent AAEC-2000
config ARCH_AT91RM9200
bool "AT91RM9200"
help
Say Y here if you intend to run this kernel on an AT91RM9200-based
board.
endchoice
source "arch/arm/mach-clps711x/Kconfig"
@ -248,6 +254,8 @@ source "arch/arm/mach-aaec2000/Kconfig"
source "arch/arm/mach-realview/Kconfig"
source "arch/arm/mach-at91rm9200/Kconfig"
# Definitions to make life easier
config ARCH_ACORN
bool
@ -413,7 +421,8 @@ config LEDS
ARCH_EBSA285 || ARCH_IMX || ARCH_INTEGRATOR || \
ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE
ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
ARCH_AT91RM9200
help
If you say Y here, the LEDs on your machine will be used
to provide useful information about your current system status.

1
arch/arm/Makefile
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@ -99,6 +99,7 @@ endif
machine-$(CONFIG_ARCH_H720X) := h720x
machine-$(CONFIG_ARCH_AAEC2000) := aaec2000
machine-$(CONFIG_ARCH_REALVIEW) := realview
machine-$(CONFIG_ARCH_AT91RM9200) := at91rm9200
ifeq ($(CONFIG_ARCH_EBSA110),y)
# This is what happens if you forget the IOCS16 line.

4
arch/arm/boot/compressed/Makefile
View File

@ -46,6 +46,10 @@ ifeq ($(CONFIG_PXA_SHARPSL),y)
OBJS += head-sharpsl.o
endif
ifeq ($(CONFIG_ARCH_AT91RM9200),y)
OBJS += head-at91rm9200.o
endif
ifeq ($(CONFIG_DEBUG_ICEDCC),y)
OBJS += ice-dcc.o
endif

57
arch/arm/boot/compressed/head-at91rm9200.S Normal file
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@ -0,0 +1,57 @@
/*
* linux/arch/arm/boot/compressed/head-at91rm9200.S
*
* Copyright (C) 2003 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#include <asm/mach-types.h>
.section ".start", "ax"
@ Atmel AT91RM9200-DK : 262
mov r3, #(MACH_TYPE_AT91RM9200DK & 0xff)
orr r3, r3, #(MACH_TYPE_AT91RM9200DK & 0xff00)
cmp r7, r3
beq 99f
@ Cogent CSB337 : 399
mov r3, #(MACH_TYPE_CSB337 & 0xff)
orr r3, r3, #(MACH_TYPE_CSB337 & 0xff00)
cmp r7, r3
beq 99f
@ Cogent CSB637 : 648
mov r3, #(MACH_TYPE_CSB637 & 0xff)
orr r3, r3, #(MACH_TYPE_CSB637 & 0xff00)
cmp r7, r3
beq 99f
@ Atmel AT91RM9200-EK : 705
mov r3, #(MACH_TYPE_AT91RM9200EK & 0xff)
orr r3, r3, #(MACH_TYPE_AT91RM9200EK & 0xff00)
cmp r7, r3
beq 99f
@ Conitec Carmeva : 769
mov r3, #(MACH_TYPE_CARMEVA & 0xff)
orr r3, r3, #(MACH_TYPE_CARMEVA & 0xff00)
cmp r7, r3
beq 99f
@ KwikByte KB920x : 612
mov r3, #(MACH_TYPE_KB9200 & 0xff)
orr r3, r3, #(MACH_TYPE_KB9200 & 0xff00)
cmp r7, r3
beq 99f
@ Unknown board, use the AT91RM9200DK board
@ mov r7, #MACH_TYPE_AT91RM9200
mov r7, #(MACH_TYPE_AT91RM9200DK & 0xff)
orr r7, r7, #(MACH_TYPE_AT91RM9200DK & 0xff00)
99:

54
arch/arm/mach-at91rm9200/Kconfig Normal file
View File

@ -0,0 +1,54 @@
if ARCH_AT91RM9200
menu "AT91RM9200 Implementations"
comment "AT91RM9200 Board Type"
config ARCH_AT91RM9200DK
bool "Atmel AT91RM9200-DK Development board"
depends on ARCH_AT91RM9200
help
Select this if you are using Atmel's AT91RM9200-DK Development board
config MACH_AT91RM9200EK
bool "Atmel AT91RM9200-EK Evaluation Kit"
depends on ARCH_AT91RM9200
help
Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit
config MACH_CSB337
bool "Cogent CSB337 board"
depends on ARCH_AT91RM9200
help
Select this if you are using Cogent's CSB337 board
config MACH_CSB637
bool "Cogent CSB637 board"
depends on ARCH_AT91RM9200
help
Select this if you are using Cogent's CSB637 board
config MACH_CARMEVA
bool "Conitec's ARM&EVA"
depends on ARCH_AT91RM9200
help
Select this if you are using Conitec's AT91RM9200-MCU-Module
config MACH_KB9200
bool "KwikByte's KB920x"
depends on ARCH_AT91RM9200
help
Select this if you are using KwikByte's KB920x board
comment "AT91RM9200 Feature Selections"
config AT91_PROGRAMMABLE_CLOCKS
bool "Programmable Clocks"
help
Select this if you need to program one or more of the PCK0..PCK3
programmable clock outputs.
endmenu
endif

27
arch/arm/mach-at91rm9200/Makefile Normal file
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@ -0,0 +1,27 @@
#
# Makefile for the linux kernel.
#
obj-y := clock.o irq.o time.o gpio.o common.o devices.o
obj-m :=
obj-n :=
obj- :=
# Board-specific support
#obj-$(CONFIG_ARCH_AT91RM9200DK) += board-dk.o
#obj-$(CONFIG_MACH_AT91RM9200EK) += board-ek.o
#obj-$(CONFIG_MACH_CSB337) += board-csb337.o
#obj-$(CONFIG_MACH_CSB637) += board-csb637.o
#obj-$(CONFIG_MACH_CARMEVA) += board-carmeva.o
#obj-$(CONFIG_MACH_KB9200) += board-kb9202.o
# LEDs support
#led-$(CONFIG_ARCH_AT91RM9200DK) += leds.o
#led-$(CONFIG_MACH_AT91RM9200EK) += leds.o
#led-$(CONFIG_MACH_CSB337) += leds.o
#led-$(CONFIG_MACH_CSB637) += leds.o
#led-$(CONFIG_MACH_KB9200) += leds.o
obj-$(CONFIG_LEDS) += $(led-y)
# VGA support
#obj-$(CONFIG_FB_S1D13XXX) += ics1523.o

9
arch/arm/mach-at91rm9200/Makefile.boot Normal file
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@ -0,0 +1,9 @@
# Note: the following conditions must always be true:
# ZRELADDR == virt_to_phys(TEXTADDR)
# PARAMS_PHYS must be within 4MB of ZRELADDR
# INITRD_PHYS must be in RAM
zreladdr-y := 0x20008000
params_phys-y := 0x20000100
initrd_phys-y := 0x20410000

620
arch/arm/mach-at91rm9200/clock.c Normal file
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@ -0,0 +1,620 @@
/*
* linux/arch/arm/mach-at91rm9200/clock.c
*
* Copyright (C) 2005 David Brownell
* Copyright (C) 2005 Ivan Kokshaysky
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/fs.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/spinlock.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <asm/semaphore.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/arch/hardware.h>
#include <asm/arch/board.h> /* for master clock global */
#include "generic.h"
#undef DEBUG
/*
* There's a lot more which can be done with clocks, including cpufreq
* integration, slow clock mode support (for system suspend), letting
* PLLB be used at other rates (on boards that don't need USB), etc.
*/
struct clk {
const char *name;
unsigned long rate_hz;
struct clk *parent;
u32 pmc_mask;
void (*mode)(struct clk *, int);
unsigned id:2; /* PCK0..3, or 32k/main/a/b */
unsigned primary:1;
unsigned pll:1;
unsigned programmable:1;
u16 users;
};
static spinlock_t clk_lock;
static u32 at91_pllb_usb_init;
/*
* Four primary clock sources: two crystal oscillators (32K, main), and
* two PLLs. PLLA usually runs the master clock; and PLLB must run at
* 48 MHz (unless no USB function clocks are needed). The main clock and
* both PLLs are turned off to run in "slow clock mode" (system suspend).
*/
static struct clk clk32k = {
.name = "clk32k",
.rate_hz = AT91_SLOW_CLOCK,
.users = 1, /* always on */
.id = 0,
.primary = 1,
};
static struct clk main_clk = {
.name = "main",
.pmc_mask = 1 << 0, /* in PMC_SR */
.users = 1,
.id = 1,
.primary = 1,
};
static struct clk plla = {
.name = "plla",
.parent = &main_clk,
.pmc_mask = 1 << 1, /* in PMC_SR */
.id = 2,
.primary = 1,
.pll = 1,
};
static void pllb_mode(struct clk *clk, int is_on)
{
u32 value;
if (is_on) {
is_on = AT91_PMC_LOCKB;
value = at91_pllb_usb_init;
} else
value = 0;
at91_sys_write(AT91_CKGR_PLLBR, value);
do {
cpu_relax();
} while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
}
static struct clk pllb = {
.name = "pllb",
.parent = &main_clk,
.pmc_mask = 1 << 2, /* in PMC_SR */
.mode = pllb_mode,
.id = 3,
.primary = 1,
.pll = 1,
};
static void pmc_sys_mode(struct clk *clk, int is_on)
{
if (is_on)
at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
else
at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
}
/* USB function clocks (PLLB must be 48 MHz) */
static struct clk udpck = {
.name = "udpck",
.parent = &pllb,
.pmc_mask = AT91_PMC_UDP,
.mode = pmc_sys_mode,
};
static struct clk uhpck = {
.name = "uhpck",
.parent = &pllb,
.pmc_mask = AT91_PMC_UHP,
.mode = pmc_sys_mode,
};
#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
/*
* The four programmable clocks can be parented by any primary clock.
* You must configure pin multiplexing to bring these signals out.
*/
static struct clk pck0 = {
.name = "pck0",
.pmc_mask = AT91_PMC_PCK0,
.mode = pmc_sys_mode,
.programmable = 1,
.id = 0,
};
static struct clk pck1 = {
.name = "pck1",
.pmc_mask = AT91_PMC_PCK1,
.mode = pmc_sys_mode,
.programmable = 1,
.id = 1,
};
static struct clk pck2 = {
.name = "pck2",
.pmc_mask = AT91_PMC_PCK2,
.mode = pmc_sys_mode,
.programmable = 1,
.id = 2,
};
static struct clk pck3 = {
.name = "pck3",
.pmc_mask = AT91_PMC_PCK3,
.mode = pmc_sys_mode,
.programmable = 1,
.id = 3,
};
#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
/*
* The master clock is divided from the CPU clock (by 1-4). It's used for
* memory, interfaces to on-chip peripherals, the AIC, and sometimes more
* (e.g baud rate generation). It's sourced from one of the primary clocks.
*/
static struct clk mck = {
.name = "mck",
.pmc_mask = 1 << 3, /* in PMC_SR */
.users = 1, /* (must be) always on */
};
static void pmc_periph_mode(struct clk *clk, int is_on)
{
if (is_on)
at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
else
at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
}
static struct clk udc_clk = {
.name = "udc_clk",
.parent = &mck,
.pmc_mask = 1 << AT91_ID_UDP,
.mode = pmc_periph_mode,
};
static struct clk ohci_clk = {
.name = "ohci_clk",
.parent = &mck,
.pmc_mask = 1 << AT91_ID_UHP,
.mode = pmc_periph_mode,
};
static struct clk *const clock_list[] = {
/* four primary clocks -- MUST BE FIRST! */
&clk32k,
&main_clk,
&plla,
&pllb,
/* PLLB children (USB) */
&udpck,
&uhpck,
#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
/* programmable clocks */
&pck0,
&pck1,
&pck2,
&pck3,
#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
/* MCK and peripherals */
&mck,
// usart0..usart3
// mmc
&udc_clk,
// i2c
// spi
// ssc0..ssc2
// tc0..tc5
&ohci_clk,
// ether
};
/* clocks are all static for now; no refcounting necessary */
struct clk *clk_get(struct device *dev, const char *id)
{
int i;
for (i = 0; i < ARRAY_SIZE(clock_list); i++) {
if (strcmp(id, clock_list[i]->name) == 0)
return clock_list[i];
}
return ERR_PTR(-ENOENT);
}
EXPORT_SYMBOL(clk_get);
void clk_put(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_put);
static void __clk_enable(struct clk *clk)
{
if (clk->parent)
__clk_enable(clk->parent);
if (clk->users++ == 0 && clk->mode)
clk->mode(clk, 1);
}
int clk_enable(struct clk *clk)
{
unsigned long flags;
spin_lock_irqsave(&clk_lock, flags);
__clk_enable(clk);
spin_unlock_irqrestore(&clk_lock, flags);
return 0;
}
EXPORT_SYMBOL(clk_enable);
static void __clk_disable(struct clk *clk)
{
BUG_ON(clk->users == 0);
if (--clk->users == 0 && clk->mode)
clk->mode(clk, 0);
if (clk->parent)
__clk_disable(clk->parent);
}
void clk_disable(struct clk *clk)
{
unsigned long flags;
spin_lock_irqsave(&clk_lock, flags);
__clk_disable(clk);
spin_unlock_irqrestore(&clk_lock, flags);
}
EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
unsigned long flags;
unsigned long rate;
spin_lock_irqsave(&clk_lock, flags);
for (;;) {
rate = clk->rate_hz;
if (rate || !clk->parent)
break;
clk = clk->parent;
}
spin_unlock_irqrestore(&clk_lock, flags);
return rate;
}
EXPORT_SYMBOL(clk_get_rate);
/*------------------------------------------------------------------------*/
#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
/*
* For now, only the programmable clocks support reparenting (MCK could
* do this too, with care) or rate changing (the PLLs could do this too,
* ditto MCK but that's more for cpufreq). Drivers may reparent to get
* a better rate match; we don't.
*/
long clk_round_rate(struct clk *clk, unsigned long rate)
{
unsigned long flags;
unsigned prescale;
unsigned long actual;
if (!clk->programmable)
return -EINVAL;
spin_lock_irqsave(&clk_lock, flags);
actual = clk->parent->rate_hz;
for (prescale = 0; prescale < 7; prescale++) {
if (actual && actual <= rate)
break;
actual >>= 1;
}
spin_unlock_irqrestore(&clk_lock, flags);
return (prescale < 7) ? actual : -ENOENT;
}
EXPORT_SYMBOL(clk_round_rate);
int clk_set_rate(struct clk *clk, unsigned long rate)
{
unsigned long flags;
unsigned prescale;
unsigned long actual;
if (!clk->programmable)
return -EINVAL;
if (clk->users)
return -EBUSY;
spin_lock_irqsave(&clk_lock, flags);
actual = clk->parent->rate_hz;
for (prescale = 0; prescale < 7; prescale++) {
if (actual && actual <= rate) {
u32 pckr;
pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
pckr &= 0x03;
pckr |= prescale << 2;
at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
clk->rate_hz = actual;
break;
}
actual >>= 1;
}
spin_unlock_irqrestore(&clk_lock, flags);
return (prescale < 7) ? actual : -ENOENT;
}
EXPORT_SYMBOL(clk_set_rate);
struct clk *clk_get_parent(struct clk *clk)
{
return clk->parent;
}
EXPORT_SYMBOL(clk_get_parent);
int clk_set_parent(struct clk *clk, struct clk *parent)
{
unsigned long flags;
if (clk->users)
return -EBUSY;
if (!parent->primary || !clk->programmable)
return -EINVAL;
spin_lock_irqsave(&clk_lock, flags);
clk->rate_hz = parent->rate_hz;
clk->parent = parent;
at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);
spin_unlock_irqrestore(&clk_lock, flags);
return 0;
}
EXPORT_SYMBOL(clk_set_parent);
#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
/*------------------------------------------------------------------------*/
#ifdef CONFIG_DEBUG_FS
static int at91_clk_show(struct seq_file *s, void *unused)
{
u32 scsr, pcsr, sr;
unsigned i;
seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));
seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR));
seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
for (i = 0; i < 4; i++)
seq_printf(s, "PCK%d = %8x\n", i, at91_sys_read(AT91_PMC_PCKR(i)));
seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
seq_printf(s, "\n");
for (i = 0; i < ARRAY_SIZE(clock_list); i++) {
char *state;
struct clk *clk = clock_list[i];
if (clk->mode == pmc_sys_mode)
state = (scsr & clk->pmc_mask) ? "on" : "off";
else if (clk->mode == pmc_periph_mode)
state = (pcsr & clk->pmc_mask) ? "on" : "off";
else if (clk->pmc_mask)
state = (sr & clk->pmc_mask) ? "on" : "off";
else if (clk == &clk32k || clk == &main_clk)
state = "on";
else
state = "";
seq_printf(s, "%-10s users=%d %-3s %9ld Hz %s\n",
clk->name, clk->users, state, clk_get_rate(clk),
clk->parent ? clk->parent->name : "");
}
return 0;
}
static int at91_clk_open(struct inode *inode, struct file *file)
{
return single_open(file, at91_clk_show, NULL);
}
static struct file_operations at91_clk_operations = {
.open = at91_clk_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static int __init at91_clk_debugfs_init(void)
{
/* /sys/kernel/debug/at91_clk */
(void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);
return 0;
}
postcore_initcall(at91_clk_debugfs_init);
#endif
/*------------------------------------------------------------------------*/
static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
{
unsigned mul, div;
div = reg & 0xff;
mul = (reg >> 16) & 0x7ff;
if (div && mul) {
freq /= div;
freq *= mul + 1;
} else
freq = 0;
if (pll == &pllb && (reg & (1 << 28)))
freq /= 2;
return freq;
}
static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
{
unsigned i, div = 0, mul = 0, diff = 1 << 30;
unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
/* PLL output max 240 MHz (or 180 MHz per errata) */
if (out_freq > 240000000)
goto fail;
for (i = 1; i < 256; i++) {
int diff1;
unsigned input, mul1;
/*
* PLL input between 1MHz and 32MHz per spec, but lower
* frequences seem necessary in some cases so allow 100K.
*/
input = main_freq / i;
if (input < 100000)
continue;
if (input > 32000000)
continue;
mul1 = out_freq / input;
if (mul1 > 2048)
continue;
if (mul1 < 2)
goto fail;
diff1 = out_freq - input * mul1;
if (diff1 < 0)
diff1 = -diff1;
if (diff > diff1) {
diff = diff1;
div = i;
mul = mul1;
if (diff == 0)
break;
}
}
if (i == 256 && diff > (out_freq >> 5))
goto fail;
return ret | ((mul - 1) << 16) | div;
fail:
return 0;
}
int __init at91_clock_init(unsigned long main_clock)
{
unsigned tmp, freq, mckr;
spin_lock_init(&clk_lock);
/*
* When the bootloader initialized the main oscillator correctly,
* there's no problem using the cycle counter. But if it didn't,
* or when using oscillator bypass mode, we must be told the speed
* of the main clock.
*/
if (!main_clock) {
do {
tmp = at91_sys_read(AT91_CKGR_MCFR);
} while (!(tmp & 0x10000));
main_clock = (tmp & 0xffff) * (AT91_SLOW_CLOCK / 16);
}
main_clk.rate_hz = main_clock;
/* report if PLLA is more than mildly overclocked */
plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
if (plla.rate_hz > 209000000)
pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
/*
* USB clock init: choose 48 MHz PLLB value, turn all clocks off,
* disable 48MHz clock during usb peripheral suspend.
*
* REVISIT: assumes MCK doesn't derive from PLLB!
*/
at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | 0x10000000;
pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
at91_sys_write(AT91_PMC_PCDR, (1 << AT91_ID_UHP) | (1 << AT91_ID_UDP));
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP | AT91_PMC_UDP);
at91_sys_write(AT91_CKGR_PLLBR, 0);
at91_sys_write(AT91_PMC_SCER, AT91_PMC_MCKUDP);
/*
* MCK and CPU derive from one of those primary clocks.
* For now, assume this parentage won't change.
*/
mckr = at91_sys_read(AT91_PMC_MCKR);
mck.parent = clock_list[mckr & AT91_PMC_CSS];
mck.parent->users++;
freq = mck.parent->rate_hz;
freq /= (1 << ((mckr >> 2) & 3)); /* prescale */
mck.rate_hz = freq / (1 + ((mckr >> 8) & 3)); /* mdiv */
printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
freq / 1000000, (unsigned) mck.rate_hz / 1000000,
(unsigned) main_clock / 1000000,
((unsigned) main_clock % 1000000) / 1000);
/* FIXME get rid of master_clock global */
at91_master_clock = mck.rate_hz;
#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
/* establish PCK0..PCK3 parentage */
for (tmp = 0; tmp < ARRAY_SIZE(clock_list); tmp++) {
struct clk *clk = clock_list[tmp], *parent;
u32 pckr;
if (!clk->programmable)
continue;
pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
parent = clock_list[pckr & 3];
clk->parent = parent;
clk->rate_hz = parent->rate_hz / (1 << ((pckr >> 2) & 3));
}
#else
/* disable unused clocks */
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK0 | AT91_PMC_PCK1 | AT91_PMC_PCK2 | AT91_PMC_PCK3);
#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
/* FIXME several unused clocks may still be active... provide
* a CONFIG option to turn off all unused clocks at some point
* before driver init starts.
*/
return 0;
}

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/*
* arch/arm/mach-at91rm9200/common.c
*
* Copyright (C) 2005 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#include <linux/config.h>
#include <linux/module.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/arch/hardware.h>
static struct map_desc at91rm9200_io_desc[] __initdata = {
{
.virtual = AT91_VA_BASE_SYS,
.pfn = __phys_to_pfn(AT91_BASE_SYS),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = AT91_VA_BASE_SPI,
.pfn = __phys_to_pfn(AT91_BASE_SPI),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_VA_BASE_SSC2,
.pfn = __phys_to_pfn(AT91_BASE_SSC2),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_VA_BASE_SSC1,
.pfn = __phys_to_pfn(AT91_BASE_SSC1),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_VA_BASE_SSC0,
.pfn = __phys_to_pfn(AT91_BASE_SSC0),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_VA_BASE_US3,
.pfn = __phys_to_pfn(AT91_BASE_US3),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_VA_BASE_US2,
.pfn = __phys_to_pfn(AT91_BASE_US2),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_VA_BASE_US1,
.pfn = __phys_to_pfn(AT91_BASE_US1),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_VA_BASE_US0,
.pfn = __phys_to_pfn(AT91_BASE_US0),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_VA_BASE_EMAC,
.pfn = __phys_to_pfn(AT91_BASE_EMAC),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_VA_BASE_TWI,
.pfn = __phys_to_pfn(AT91_BASE_TWI),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_VA_BASE_MCI,
.pfn = __phys_to_pfn(AT91_BASE_MCI),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_VA_BASE_UDP,
.pfn = __phys_to_pfn(AT91_BASE_UDP),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_VA_BASE_TCB1,
.pfn = __phys_to_pfn(AT91_BASE_TCB1),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_VA_BASE_TCB0,
.pfn = __phys_to_pfn(AT91_BASE_TCB0),
.length = SZ_16K,
.type = MT_DEVICE,
},
};
void __init at91rm9200_map_io(void)
{
iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc));
}
unsigned long at91_master_clock;
EXPORT_SYMBOL(at91_master_clock);
int at91_serial_map[AT91_NR_UART];
int at91_console_port;
EXPORT_SYMBOL(at91_serial_map);
EXPORT_SYMBOL(at91_console_port);

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/*
* arch/arm/mach-at91rm9200/devices.c
*
* Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
* Copyright (C) 2005 David Brownell
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <linux/config.h>
#include <linux/platform_device.h>
#include <asm/arch/board.h>
#include <asm/arch/pio.h>
/* --------------------------------------------------------------------
* USB Host
* -------------------------------------------------------------------- */
#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
static u64 ohci_dmamask = 0xffffffffUL;
static struct at91_usbh_data usbh_data;
static struct resource at91rm9200_usbh_resource[] = {
[0] = {
.start = AT91_UHP_BASE,
.end = AT91_UHP_BASE + SZ_1M -1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AT91_ID_UHP,
.end = AT91_ID_UHP,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device at91rm9200_usbh_device = {
.name = "at91rm9200-ohci",
.id = -1,
.dev = {
.dma_mask = &ohci_dmamask,
.coherent_dma_mask = 0xffffffff,
.platform_data = &usbh_data,
},
.resource = at91rm9200_usbh_resource,
.num_resources = ARRAY_SIZE(at91rm9200_usbh_resource),
};
void __init at91_add_device_usbh(struct at91_usbh_data *data)
{
if (!data)
return;
usbh_data = *data;
platform_device_register(&at91rm9200_usbh_device);
}
#else
void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
#endif
/* --------------------------------------------------------------------
* USB Device (Gadget)
* -------------------------------------------------------------------- */
#ifdef CONFIG_USB_GADGET_AT91
static struct at91_udc_data udc_data;
static struct resource at91_udc_resources[] = {
{
.start = AT91_BASE_UDP,
.end = AT91_BASE_UDP + SZ_16K - 1,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device at91rm9200_udc_device = {
.name = "at91_udc",
.id = -1,
.dev = {
.platform_data = &udc_data,
},
.resource = at91_udc_resources,
.num_resources = ARRAY_SIZE(at91_udc_resources),
};
void __init at91_add_device_udc(struct at91_udc_data *data)
{
if (!data)
return;
if (data->vbus_pin) {
at91_set_gpio_input(data->vbus_pin, 0);
at91_set_deglitch(data->vbus_pin, 1);
}
if (data->pullup_pin)
at91_set_gpio_output(data->pullup_pin, 0);
udc_data = *data;
platform_device_register(&at91rm9200_udc_device);
}
#else
void __init at91_add_device_udc(struct at91_udc_data *data) {}
#endif
/* --------------------------------------------------------------------
* Ethernet
* -------------------------------------------------------------------- */
#if defined(CONFIG_ARM_AT91_ETHER) || defined(CONFIG_ARM_AT91_ETHER_MODULE)
static u64 eth_dmamask = 0xffffffffUL;
static struct at91_eth_data eth_data;
static struct platform_device at91rm9200_eth_device = {
.name = "at91_ether",
.id = -1,
.dev = {
.dma_mask = &eth_dmamask,
.coherent_dma_mask = 0xffffffff,
.platform_data = &eth_data,
},
.num_resources = 0,
};
void __init at91_add_device_eth(struct at91_eth_data *data)
{
if (!data)
return;
if (data->phy_irq_pin) {
at91_set_gpio_input(data->phy_irq_pin, 0);
at91_set_deglitch(data->phy_irq_pin, 1);
}
/* Pins used for MII and RMII */
at91_set_A_periph(AT91_PIN_PA16, 0); /* EMDIO */
at91_set_A_periph(AT91_PIN_PA15, 0); /* EMDC */
at91_set_A_periph(AT91_PIN_PA14, 0); /* ERXER */
at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
at91_set_A_periph(AT91_PIN_PA11, 0); /* ECRS_ECRSDV */
at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX1 */
at91_set_A_periph(AT91_PIN_PA9, 0); /* ETX0 */
at91_set_A_periph(AT91_PIN_PA8, 0); /* ETXEN */
at91_set_A_periph(AT91_PIN_PA7, 0); /* ETXCK_EREFCK */
if (!data->is_rmii) {
at91_set_B_periph(AT91_PIN_PB19, 0); /* ERXCK */
at91_set_B_periph(AT91_PIN_PB18, 0); /* ECOL */
at91_set_B_periph(AT91_PIN_PB17, 0); /* ERXDV */
at91_set_B_periph(AT91_PIN_PB16, 0); /* ERX3 */
at91_set_B_periph(AT91_PIN_PB15, 0); /* ERX2 */
at91_set_B_periph(AT91_PIN_PB14, 0); /* ETXER */
at91_set_B_periph(AT91_PIN_PB13, 0); /* ETX3 */
at91_set_B_periph(AT91_PIN_PB12, 0); /* ETX2 */
}
eth_data = *data;
platform_device_register(&at91rm9200_eth_device);
}
#else
void __init at91_add_device_eth(struct at91_eth_data *data) {}
#endif
/* --------------------------------------------------------------------
* Compact Flash / PCMCIA
* -------------------------------------------------------------------- */
#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
static struct at91_cf_data cf_data;
static struct platform_device at91rm9200_cf_device = {
.name = "at91_cf",
.id = -1,
.dev = {
.platform_data = &cf_data,
},
.num_resources = 0,
};
void __init at91_add_device_cf(struct at91_cf_data *data)
{
if (!data)
return;
/* input/irq */
if (data->irq_pin) {
at91_set_gpio_input(data->irq_pin, 1);
at91_set_deglitch(data->irq_pin, 1);
}
at91_set_gpio_input(data->det_pin, 1);
at91_set_deglitch(data->det_pin, 1);
/* outputs, initially off */
if (data->vcc_pin)
at91_set_gpio_output(data->vcc_pin, 0);
at91_set_gpio_output(data->rst_pin, 0);
cf_data = *data;
platform_device_register(&at91rm9200_cf_device);
}
#else
void __init at91_add_device_cf(struct at91_cf_data *data) {}
#endif
/* --------------------------------------------------------------------
* MMC / SD
* -------------------------------------------------------------------- */
#if defined(CONFIG_MMC_AT91RM9200) || defined(CONFIG_MMC_AT91RM9200_MODULE)
static u64 mmc_dmamask = 0xffffffffUL;
static struct at91_mmc_data mmc_data;
static struct resource at91_mmc_resources[] = {
{
.start = AT91_BASE_MCI,
.end = AT91_BASE_MCI + SZ_16K - 1,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device at91rm9200_mmc_device = {
.name = "at91rm9200_mci",
.id = -1,
.dev = {
.dma_mask = &mmc_dmamask,
.coherent_dma_mask = 0xffffffff,
.platform_data = &mmc_data,
},
.resource = at91_mmc_resources,
.num_resources = ARRAY_SIZE(at91_mmc_resources),
};
void __init at91_add_device_mmc(struct at91_mmc_data *data)
{
if (!data)
return;
/* input/irq */
if (data->det_pin) {
at91_set_gpio_input(data->det_pin, 1);
at91_set_deglitch(data->det_pin, 1);
}
if (data->wp_pin)
at91_set_gpio_input(data->wp_pin, 1);
/* CLK */
at91_set_A_periph(AT91_PIN_PA27, 0);
if (data->is_b) {
/* CMD */
at91_set_B_periph(AT91_PIN_PA8, 0);
/* DAT0, maybe DAT1..DAT3 */
at91_set_B_periph(AT91_PIN_PA9, 0);
if (data->wire4) {
at91_set_B_periph(AT91_PIN_PA10, 0);
at91_set_B_periph(AT91_PIN_PA11, 0);
at91_set_B_periph(AT91_PIN_PA12, 0);
}
} else {
/* CMD */
at91_set_A_periph(AT91_PIN_PA28, 0);
/* DAT0, maybe DAT1..DAT3 */
at91_set_A_periph(AT91_PIN_PA29, 0);
if (data->wire4) {
at91_set_B_periph(AT91_PIN_PB3, 0);
at91_set_B_periph(AT91_PIN_PB4, 0);
at91_set_B_periph(AT91_PIN_PB5, 0);
}
}
mmc_data = *data;
platform_device_register(&at91rm9200_mmc_device);
}
#else
void __init at91_add_device_mmc(struct at91_mmc_data *data) {}
#endif
/* -------------------------------------------------------------------- */

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/*
* linux/arch/arm/mach-at91rm9200/generic.h
*
* Copyright (C) 2005 David Brownell
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
void at91_gpio_irq_setup(unsigned banks);
struct sys_timer;
extern struct sys_timer at91rm9200_timer;
extern void __init at91rm9200_map_io(void);
extern int __init at91_clock_init(unsigned long main_clock);

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/*
* linux/arch/arm/mach-at91rm9200/gpio.c
*
* Copyright (C) 2005 HP Labs
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/module.h>
#include <asm/io.h>
#include <asm/mach/irq.h>
#include <asm/arch/hardware.h>
#include <asm/arch/gpio.h>
static const u32 pio_controller_offset[4] = {
AT91_PIOA,
AT91_PIOB,
AT91_PIOC,
AT91_PIOD,
};
static inline void __iomem *pin_to_controller(unsigned pin)
{
void __iomem *sys_base = (void __iomem *) AT91_VA_BASE_SYS;
pin -= PIN_BASE;
pin /= 32;
if (likely(pin < BGA_GPIO_BANKS))
return sys_base + pio_controller_offset[pin];
return NULL;
}
static inline unsigned pin_to_mask(unsigned pin)
{
pin -= PIN_BASE;
return 1 << (pin % 32);
}
/*--------------------------------------------------------------------------*/
/* Not all hardware capabilities are exposed through these calls; they
* only encapsulate the most common features and modes. (So if you
* want to change signals in groups, do it directly.)
*
* Bootloaders will usually handle some of the pin multiplexing setup.
* The intent is certainly that by the time Linux is fully booted, all
* pins should have been fully initialized. These setup calls should
* only be used by board setup routines, or possibly in driver probe().
*
* For bootloaders doing all that setup, these calls could be inlined
* as NOPs so Linux won't duplicate any setup code
*/
/*
* mux the pin to the "A" internal peripheral role.
*/
int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
{
void __iomem *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
if (!pio)
return -EINVAL;
__raw_writel(mask, pio + PIO_IDR);
__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
__raw_writel(mask, pio + PIO_ASR);
__raw_writel(mask, pio + PIO_PDR);
return 0;
}
EXPORT_SYMBOL(at91_set_A_periph);
/*
* mux the pin to the "B" internal peripheral role.
*/
int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
{
void __iomem *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
if (!pio)
return -EINVAL;
__raw_writel(mask, pio + PIO_IDR);
__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
__raw_writel(mask, pio + PIO_BSR);
__raw_writel(mask, pio + PIO_PDR);
return 0;
}
EXPORT_SYMBOL(at91_set_B_periph);
/*
* mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
* configure it for an input.
*/
int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
{
void __iomem *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
if (!pio)
return -EINVAL;
__raw_writel(mask, pio + PIO_IDR);
__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
__raw_writel(mask, pio + PIO_ODR);
__raw_writel(mask, pio + PIO_PER);
return 0;
}
EXPORT_SYMBOL(at91_set_gpio_input);
/*
* mux the pin to the gpio controller (instead of "A" or "B" peripheral),
* and configure it for an output.
*/
int __init_or_module at91_set_gpio_output(unsigned pin, int value)
{
void __iomem *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
if (!pio)
return -EINVAL;
__raw_writel(mask, pio + PIO_IDR);
__raw_writel(mask, pio + PIO_PUDR);
__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
__raw_writel(mask, pio + PIO_OER);
__raw_writel(mask, pio + PIO_PER);
return 0;
}
EXPORT_SYMBOL(at91_set_gpio_output);
/*
* enable/disable the glitch filter; mostly used with IRQ handling.
*/
int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
{
void __iomem *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
if (!pio)
return -EINVAL;
__raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
return 0;
}
EXPORT_SYMBOL(at91_set_deglitch);
/*--------------------------------------------------------------------------*/
/*
* assuming the pin is muxed as a gpio output, set its value.
*/
int at91_set_gpio_value(unsigned pin, int value)
{
void __iomem *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
if (!pio)
return -EINVAL;
__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
return 0;
}
EXPORT_SYMBOL(at91_set_gpio_value);
/*
* read the pin's value (works even if it's not muxed as a gpio).
*/
int at91_get_gpio_value(unsigned pin)
{
void __iomem *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
u32 pdsr;
if (!pio)
return -EINVAL;
pdsr = __raw_readl(pio + PIO_PDSR);
return (pdsr & mask) != 0;
}
EXPORT_SYMBOL(at91_get_gpio_value);
/*--------------------------------------------------------------------------*/
/* Several AIC controller irqs are dispatched through this GPIO handler.
* To use any AT91_PIN_* as an externally triggered IRQ, first call
* at91_set_gpio_input() then maybe enable its glitch filter.
* Then just request_irq() with the pin ID; it works like any ARM IRQ
* handler, though it always triggers on rising and falling edges.
*
* Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
* configuring them with at91_set_a_periph() or at91_set_b_periph().
* IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
*/
static void gpio_irq_mask(unsigned pin)
{
void __iomem *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
if (pio)
__raw_writel(mask, pio + PIO_IDR);
}
static void gpio_irq_unmask(unsigned pin)
{
void __iomem *pio = pin_to_controller(pin);
unsigned mask = pin_to_mask(pin);
if (pio)
__raw_writel(mask, pio + PIO_IER);
}
static int gpio_irq_type(unsigned pin, unsigned type)
{
return (type == IRQT_BOTHEDGE) ? 0 : -EINVAL;
}
static struct irqchip gpio_irqchip = {
.mask = gpio_irq_mask,
.unmask = gpio_irq_unmask,
.set_type = gpio_irq_type,
};
static void gpio_irq_handler(unsigned irq, struct irqdesc *desc, struct pt_regs *regs)
{
unsigned pin;
struct irqdesc *gpio;
void __iomem *pio;
u32 isr;
pio = (void __force __iomem *) desc->chipdata;
/* temporarily mask (level sensitive) parent IRQ */
desc->chip->ack(irq);
for (;;) {
isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
if (!isr)
break;
pin = (unsigned) desc->data;
gpio = &irq_desc[pin];
while (isr) {
if (isr & 1)
gpio->handle(pin, gpio, regs);
pin++;
gpio++;
isr >>= 1;
}
}
desc->chip->unmask(irq);
/* now it may re-trigger */
}
/* call this from board-specific init_irq */
void __init at91_gpio_irq_setup(unsigned banks)
{
unsigned pioc, pin, id;
if (banks > 4)
banks = 4;
for (pioc = 0, pin = PIN_BASE, id = AT91_ID_PIOA;
pioc < banks;
pioc++, id++) {
void __iomem *controller;
unsigned i;
controller = (void __iomem *) AT91_VA_BASE_SYS + pio_controller_offset[pioc];
__raw_writel(~0, controller + PIO_IDR);
set_irq_data(id, (void *) pin);
set_irq_chipdata(id, (void __force *) controller);
for (i = 0; i < 32; i++, pin++) {
set_irq_chip(pin, &gpio_irqchip);
set_irq_handler(pin, do_simple_IRQ);
set_irq_flags(pin, IRQF_VALID);
}
set_irq_chained_handler(id, gpio_irq_handler);
/* enable the PIO peripheral clock */
at91_sys_write(AT91_PMC_PCER, 1 << id);
}
pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, banks);
}

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@ -0,0 +1,170 @@
/*
* linux/arch/arm/mach-at91rm9200/irq.c
*
* Copyright (C) 2004 SAN People
* Copyright (C) 2004 ATMEL
* Copyright (C) Rick Bronson
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/mm.h>
#include <linux/types.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <asm/setup.h>
#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include "generic.h"
/*
* The default interrupt priority levels (0 = lowest, 7 = highest).
*/
static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
7, /* Advanced Interrupt Controller */
7, /* System Peripheral */
0, /* Parallel IO Controller A */
0, /* Parallel IO Controller B */
0, /* Parallel IO Controller C */
0, /* Parallel IO Controller D */
6, /* USART 0 */
6, /* USART 1 */
6, /* USART 2 */
6, /* USART 3 */
0, /* Multimedia Card Interface */
4, /* USB Device Port */
0, /* Two-Wire Interface */
6, /* Serial Peripheral Interface */
5, /* Serial Synchronous Controller */
5, /* Serial Synchronous Controller */
5, /* Serial Synchronous Controller */
0, /* Timer Counter 0 */
0, /* Timer Counter 1 */
0, /* Timer Counter 2 */
0, /* Timer Counter 3 */
0, /* Timer Counter 4 */
0, /* Timer Counter 5 */
3, /* USB Host port */
3, /* Ethernet MAC */
0, /* Advanced Interrupt Controller */
0, /* Advanced Interrupt Controller */
0, /* Advanced Interrupt Controller */
0, /* Advanced Interrupt Controller */
0, /* Advanced Interrupt Controller */
0, /* Advanced Interrupt Controller */
0 /* Advanced Interrupt Controller */
};
static void at91rm9200_mask_irq(unsigned int irq)
{
/* Disable interrupt on AIC */
at91_sys_write(AT91_AIC_IDCR, 1 << irq);
}
static void at91rm9200_unmask_irq(unsigned int irq)
{
/* Enable interrupt on AIC */
at91_sys_write(AT91_AIC_IECR, 1 << irq);
}
static int at91rm9200_irq_type(unsigned irq, unsigned type)
{
unsigned int smr, srctype;
/* change triggering only for FIQ and external IRQ0..IRQ6 */
if ((irq < AT91_ID_IRQ0) && (irq != AT91_ID_FIQ))
return -EINVAL;
switch (type) {
case IRQT_HIGH:
srctype = AT91_AIC_SRCTYPE_HIGH;
break;
case IRQT_RISING:
srctype = AT91_AIC_SRCTYPE_RISING;
break;
case IRQT_LOW:
srctype = AT91_AIC_SRCTYPE_LOW;
break;
case IRQT_FALLING:
srctype = AT91_AIC_SRCTYPE_FALLING;
break;
default:
return -EINVAL;
}
smr = at91_sys_read(AT91_AIC_SMR(irq)) & ~AT91_AIC_SRCTYPE;
at91_sys_write(AT91_AIC_SMR(irq), smr | srctype);
return 0;
}
static struct irqchip at91rm9200_irq_chip = {
.ack = at91rm9200_mask_irq,
.mask = at91rm9200_mask_irq,
.unmask = at91rm9200_unmask_irq,
.set_type = at91rm9200_irq_type,
};
/*
* Initialize the AIC interrupt controller.
*/
void __init at91rm9200_init_irq(unsigned int priority[NR_AIC_IRQS])
{
unsigned int i;
/* No priority list specified for this board -> use defaults */
if (priority == NULL)
priority = at91rm9200_default_irq_priority;
/*
* The IVR is used by macro get_irqnr_and_base to read and verify.
* The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
*/
for (i = 0; i < NR_AIC_IRQS; i++) {
/* Put irq number in Source Vector Register: */
at91_sys_write(AT91_AIC_SVR(i), i);
/* Store the Source Mode Register as defined in table above */
at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
set_irq_chip(i, &at91rm9200_irq_chip);
set_irq_handler(i, do_level_IRQ);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
/* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
if (i < 8)
at91_sys_write(AT91_AIC_EOICR, 0);
}
/*
* Spurious Interrupt ID in Spurious Vector Register is NR_AIC_IRQS
* When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU
*/
at91_sys_write(AT91_AIC_SPU, NR_AIC_IRQS);
/* No debugging in AIC: Debug (Protect) Control Register */
at91_sys_write(AT91_AIC_DCR, 0);
/* Disable and clear all interrupts initially */
at91_sys_write(AT91_AIC_IDCR, 0xFFFFFFFF);
at91_sys_write(AT91_AIC_ICCR, 0xFFFFFFFF);
}

127
arch/arm/mach-at91rm9200/time.c Normal file
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@ -0,0 +1,127 @@
/*
* linux/arch/arm/mach-at91rm9200/time.c
*
* Copyright (C) 2003 SAN People
* Copyright (C) 2003 ATMEL
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/time.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mach/time.h>
/*
* The ST_CRTR is updated asynchronously to the master clock. It is therefore
* necessary to read it twice (with the same value) to ensure accuracy.
*/
static inline unsigned long read_CRTR(void) {
unsigned long x1, x2;
do {
x1 = at91_sys_read(AT91_ST_CRTR);
x2 = at91_sys_read(AT91_ST_CRTR);
} while (x1 != x2);
return x1;
}
/*
* Returns number of microseconds since last timer interrupt. Note that interrupts
* will have been disabled by do_gettimeofday()
* 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
* 'tick' is usecs per jiffy (linux/timex.h).
*/
static unsigned long at91rm9200_gettimeoffset(void)
{
unsigned long elapsed;
elapsed = (read_CRTR() - at91_sys_read(AT91_ST_RTAR)) & AT91_ST_ALMV;
return (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH;
}
/*
* IRQ handler for the timer.
*/
static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
unsigned long rtar;
if (at91_sys_read(AT91_ST_SR) & AT91_ST_PITS) { /* This is a shared interrupt */
write_seqlock(&xtime_lock);
do {
timer_tick(regs);
rtar = (at91_sys_read(AT91_ST_RTAR) + LATCH) & AT91_ST_ALMV;
at91_sys_write(AT91_ST_RTAR, rtar);
} while (((read_CRTR() - at91_sys_read(AT91_ST_RTAR)) & AT91_ST_ALMV) >= LATCH);
write_sequnlock(&xtime_lock);
return IRQ_HANDLED;
}
else
return IRQ_NONE; /* not handled */
}
static struct irqaction at91rm9200_timer_irq = {
.name = "at91_tick",
.flags = SA_SHIRQ | SA_INTERRUPT,
.handler = at91rm9200_timer_interrupt
};
/*
* Set up timer interrupt.
*/
void __init at91rm9200_timer_init(void)
{
/* Disable all timer interrupts */
at91_sys_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
(void) at91_sys_read(AT91_ST_SR); /* Clear any pending interrupts */
/*
* Make IRQs happen for the system timer.
*/
setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq);
/* Set initial alarm to 0 */
at91_sys_write(AT91_ST_RTAR, 0);
/* Real time counter incremented every 30.51758 microseconds */
at91_sys_write(AT91_ST_RTMR, 1);
/* Set Period Interval timer */
at91_sys_write(AT91_ST_PIMR, LATCH);
/* Change the kernel's 'tick' value to 10009 usec. (the default is 10000) */
tick_usec = (LATCH * 1000000) / CLOCK_TICK_RATE;
/* Enable Period Interval Timer interrupt */
at91_sys_write(AT91_ST_IER, AT91_ST_PITS);
}
struct sys_timer at91rm9200_timer = {
.init = at91rm9200_timer_init,
.offset = at91rm9200_gettimeoffset,
};

4
arch/arm/mm/Kconfig
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@ -62,8 +62,8 @@ config CPU_ARM720T
# ARM920T
config CPU_ARM920T
bool "Support ARM920T processor" if !ARCH_S3C2410
depends on ARCH_INTEGRATOR || ARCH_S3C2410 || ARCH_IMX || ARCH_AAEC2000
default y if ARCH_S3C2410
depends on ARCH_INTEGRATOR || ARCH_S3C2410 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
default y if ARCH_S3C2410 || ARCH_AT91RM9200
select CPU_32v4
select CPU_ABRT_EV4T
select CPU_CACHE_V4WT

261
include/asm-arm/arch-at91rm9200/at91rm9200.h Normal file
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@ -0,0 +1,261 @@
/*
* include/asm-arm/arch-at91rm9200/at91rm9200.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Common definitions.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91RM9200_H
#define AT91RM9200_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
#define AT91_ID_SYS 1 /* System Peripheral */
#define AT91_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91_ID_PIOC 4 /* Parallel IO Controller C */
#define AT91_ID_PIOD 5 /* Parallel IO Controller D */
#define AT91_ID_US0 6 /* USART 0 */
#define AT91_ID_US1 7 /* USART 1 */
#define AT91_ID_US2 8 /* USART 2 */
#define AT91_ID_US3 9 /* USART 3 */
#define AT91_ID_MCI 10 /* Multimedia Card Interface */
#define AT91_ID_UDP 11 /* USB Device Port */
#define AT91_ID_TWI 12 /* Two-Wire Interface */
#define AT91_ID_SPI 13 /* Serial Peripheral Interface */
#define AT91_ID_SSC0 14 /* Serial Synchronous Controller 0 */
#define AT91_ID_SSC1 15 /* Serial Synchronous Controller 1 */
#define AT91_ID_SSC2 16 /* Serial Synchronous Controller 2 */
#define AT91_ID_TC0 17 /* Timer Counter 0 */
#define AT91_ID_TC1 18 /* Timer Counter 1 */
#define AT91_ID_TC2 19 /* Timer Counter 2 */
#define AT91_ID_TC3 20 /* Timer Counter 3 */
#define AT91_ID_TC4 21 /* Timer Counter 4 */
#define AT91_ID_TC5 22 /* Timer Counter 5 */
#define AT91_ID_UHP 23 /* USB Host port */
#define AT91_ID_EMAC 24 /* Ethernet MAC */
#define AT91_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */
#define AT91_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */
#define AT91_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */
#define AT91_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */
#define AT91_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */
#define AT91_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */
#define AT91_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */
/*
* Peripheral physical base addresses.
*/
#define AT91_BASE_TCB0 0xfffa0000
#define AT91_BASE_TC0 0xfffa0000
#define AT91_BASE_TC1 0xfffa0040
#define AT91_BASE_TC2 0xfffa0080
#define AT91_BASE_TCB1 0xfffa4000
#define AT91_BASE_TC3 0xfffa4000
#define AT91_BASE_TC4 0xfffa4040
#define AT91_BASE_TC5 0xfffa4080
#define AT91_BASE_UDP 0xfffb0000
#define AT91_BASE_MCI 0xfffb4000
#define AT91_BASE_TWI 0xfffb8000
#define AT91_BASE_EMAC 0xfffbc000
#define AT91_BASE_US0 0xfffc0000
#define AT91_BASE_US1 0xfffc4000
#define AT91_BASE_US2 0xfffc8000
#define AT91_BASE_US3 0xfffcc000
#define AT91_BASE_SSC0 0xfffd0000
#define AT91_BASE_SSC1 0xfffd4000
#define AT91_BASE_SSC2 0xfffd8000
#define AT91_BASE_SPI 0xfffe0000
#define AT91_BASE_SYS 0xfffff000
/*
* PIO pin definitions (peripheral A/B multiplexing).
*/
#define AT91_PA0_MISO (1 << 0) /* A: SPI Master-In Slave-Out */
#define AT91_PA0_PCK3 (1 << 0) /* B: PMC Programmable Clock Output 3 */
#define AT91_PA1_MOSI (1 << 1) /* A: SPI Master-Out Slave-In */
#define AT91_PA1_PCK0 (1 << 1) /* B: PMC Programmable Clock Output 0 */
#define AT91_PA2_SPCK (1 << 2) /* A: SPI Serial Clock */
#define AT91_PA2_IRQ4 (1 << 2) /* B: External Interrupt 4 */
#define AT91_PA3_NPCS0 (1 << 3) /* A: SPI Peripheral Chip Select 0 */
#define AT91_PA3_IRQ5 (1 << 3) /* B: External Interrupt 5 */
#define AT91_PA4_NPCS1 (1 << 4) /* A: SPI Peripheral Chip Select 1 */
#define AT91_PA4_PCK1 (1 << 4) /* B: PMC Programmable Clock Output 1 */
#define AT91_PA5_NPCS2 (1 << 5) /* A: SPI Peripheral Chip Select 2 */
#define AT91_PA5_TXD3 (1 << 5) /* B: USART Transmit Data 3 */
#define AT91_PA6_NPCS3 (1 << 6) /* A: SPI Peripheral Chip Select 3 */
#define AT91_PA6_RXD3 (1 << 6) /* B: USART Receive Data 3 */
#define AT91_PA7_ETXCK_EREFCK (1 << 7) /* A: Ethernet Reference Clock / Transmit Clock */
#define AT91_PA7_PCK2 (1 << 7) /* B: PMC Programmable Clock Output 2 */
#define AT91_PA8_ETXEN (1 << 8) /* A: Ethernet Transmit Enable */
#define AT91_PA8_MCCDB (1 << 8) /* B: MMC Multimedia Card B Command */
#define AT91_PA9_ETX0 (1 << 9) /* A: Ethernet Transmit Data 0 */
#define AT91_PA9_MCDB0 (1 << 9) /* B: MMC Multimedia Card B Data 0 */
#define AT91_PA10_ETX1 (1 << 10) /* A: Ethernet Transmit Data 1 */
#define AT91_PA10_MCDB1 (1 << 10) /* B: MMC Multimedia Card B Data 1 */
#define AT91_PA11_ECRS_ECRSDV (1 << 11) /* A: Ethernet Carrier Sense / Data Valid */
#define AT91_PA11_MCDB2 (1 << 11) /* B: MMC Multimedia Card B Data 2 */
#define AT91_PA12_ERX0 (1 << 12) /* A: Ethernet Receive Data 0 */
#define AT91_PA12_MCDB3 (1 << 12) /* B: MMC Multimedia Card B Data 3 */
#define AT91_PA13_ERX1 (1 << 13) /* A: Ethernet Receive Data 1 */
#define AT91_PA13_TCLK0 (1 << 13) /* B: TC External Clock Input 0 */
#define AT91_PA14_ERXER (1 << 14) /* A: Ethernet Receive Error */
#define AT91_PA14_TCLK1 (1 << 14) /* B: TC External Clock Input 1 */
#define AT91_PA15_EMDC (1 << 15) /* A: Ethernet Management Data Clock */
#define AT91_PA15_TCLK2 (1 << 15) /* B: TC External Clock Input 2 */
#define AT91_PA16_EMDIO (1 << 16) /* A: Ethernet Management Data I/O */
#define AT91_PA16_IRQ6 (1 << 16) /* B: External Interrupt 6 */
#define AT91_PA17_TXD0 (1 << 17) /* A: USART Transmit Data 0 */
#define AT91_PA17_TIOA0 (1 << 17) /* B: TC I/O Line A 0 */
#define AT91_PA18_RXD0 (1 << 18) /* A: USART Receive Data 0 */
#define AT91_PA18_TIOB0 (1 << 18) /* B: TC I/O Line B 0 */
#define AT91_PA19_SCK0 (1 << 19) /* A: USART Serial Clock 0 */
#define AT91_PA19_TIOA1 (1 << 19) /* B: TC I/O Line A 1 */
#define AT91_PA20_CTS0 (1 << 20) /* A: USART Clear To Send 0 */
#define AT91_PA20_TIOB1 (1 << 20) /* B: TC I/O Line B 1 */
#define AT91_PA21_RTS0 (1 << 21) /* A: USART Ready To Send 0 */
#define AT91_PA21_TIOA2 (1 << 21) /* B: TC I/O Line A 2 */
#define AT91_PA22_RXD2 (1 << 22) /* A: USART Receive Data 2 */
#define AT91_PA22_TIOB2 (1 << 22) /* B: TC I/O Line B 2 */
#define AT91_PA23_TXD2 (1 << 23) /* A: USART Transmit Data 2 */
#define AT91_PA23_IRQ3 (1 << 23) /* B: External Interrupt 3 */
#define AT91_PA24_SCK2 (1 << 24) /* A: USART Serial Clock 2 */
#define AT91_PA24_PCK1 (1 << 24) /* B: PMC Programmable Clock Output 1 */
#define AT91_PA25_TWD (1 << 25) /* A: TWI Two-wire Serial Data */
#define AT91_PA25_IRQ2 (1 << 25) /* B: External Interrupt 2 */
#define AT91_PA26_TWCK (1 << 26) /* A: TWI Two-wire Serial Clock */
#define AT91_PA26_IRQ1 (1 << 26) /* B: External Interrupt 1 */
#define AT91_PA27_MCCK (1 << 27) /* A: MMC Multimedia Card Clock */
#define AT91_PA27_TCLK3 (1 << 27) /* B: TC External Clock Input 3 */
#define AT91_PA28_MCCDA (1 << 28) /* A: MMC Multimedia Card A Command */
#define AT91_PA28_TCLK4 (1 << 28) /* B: TC External Clock Input 4 */
#define AT91_PA29_MCDA0 (1 << 29) /* A: MMC Multimedia Card A Data 0 */
#define AT91_PA29_TCLK5 (1 << 29) /* B: TC External Clock Input 5 */
#define AT91_PA30_DRXD (1 << 30) /* A: DBGU Receive Data */
#define AT91_PA30_CTS2 (1 << 30) /* B: USART Clear To Send 2 */
#define AT91_PA31_DTXD (1 << 31) /* A: DBGU Transmit Data */
#define AT91_PA31_RTS2 (1 << 31) /* B: USART Ready To Send 2 */
#define AT91_PB0_TF0 (1 << 0) /* A: SSC Transmit Frame Sync 0 */
#define AT91_PB0_RTS3 (1 << 0) /* B: USART Ready To Send 3 */
#define AT91_PB1_TK0 (1 << 1) /* A: SSC Transmit Clock 0 */
#define AT91_PB1_CTS3 (1 << 1) /* B: USART Clear To Send 3 */
#define AT91_PB2_TD0 (1 << 2) /* A: SSC Transmit Data 0 */
#define AT91_PB2_SCK3 (1 << 2) /* B: USART Serial Clock 3 */
#define AT91_PB3_RD0 (1 << 3) /* A: SSC Receive Data 0 */
#define AT91_PB3_MCDA1 (1 << 3) /* B: MMC Multimedia Card A Data 1 */
#define AT91_PB4_RK0 (1 << 4) /* A: SSC Receive Clock 0 */
#define AT91_PB4_MCDA2 (1 << 4) /* B: MMC Multimedia Card A Data 2 */
#define AT91_PB5_RF0 (1 << 5) /* A: SSC Receive Frame Sync 0 */
#define AT91_PB5_MCDA3 (1 << 5) /* B: MMC Multimedia Card A Data 3 */
#define AT91_PB6_TF1 (1 << 6) /* A: SSC Transmit Frame Sync 1 */
#define AT91_PB6_TIOA3 (1 << 6) /* B: TC I/O Line A 3 */
#define AT91_PB7_TK1 (1 << 7) /* A: SSC Transmit Clock 1 */
#define AT91_PB7_TIOB3 (1 << 7) /* B: TC I/O Line B 3 */
#define AT91_PB8_TD1 (1 << 8) /* A: SSC Transmit Data 1 */
#define AT91_PB8_TIOA4 (1 << 8) /* B: TC I/O Line A 4 */
#define AT91_PB9_RD1 (1 << 9) /* A: SSC Receive Data 1 */
#define AT91_PB9_TIOB4 (1 << 9) /* B: TC I/O Line B 4 */
#define AT91_PB10_RK1 (1 << 10) /* A: SSC Receive Clock 1 */
#define AT91_PB10_TIOA5 (1 << 10) /* B: TC I/O Line A 5 */
#define AT91_PB11_RF1 (1 << 11) /* A: SSC Receive Frame Sync 1 */
#define AT91_PB11_TIOB5 (1 << 11) /* B: TC I/O Line B 5 */
#define AT91_PB12_TF2 (1 << 12) /* A: SSC Transmit Frame Sync 2 */
#define AT91_PB12_ETX2 (1 << 12) /* B: Ethernet Transmit Data 2 */
#define AT91_PB13_TK2 (1 << 13) /* A: SSC Transmit Clock 3 */
#define AT91_PB13_ETX3 (1 << 13) /* B: Ethernet Transmit Data 3 */
#define AT91_PB14_TD2 (1 << 14) /* A: SSC Transmit Data 2 */
#define AT91_PB14_ETXER (1 << 14) /* B: Ethernet Transmit Coding Error */
#define AT91_PB15_RD2 (1 << 15) /* A: SSC Receive Data 2 */
#define AT91_PB15_ERX2 (1 << 15) /* B: Ethernet Receive Data 2 */
#define AT91_PB16_RK2 (1 << 16) /* A: SSC Receive Clock 2 */
#define AT91_PB16_ERX3 (1 << 16) /* B: Ethernet Receive Data 3 */
#define AT91_PB17_RF2 (1 << 17) /* A: SSC Receive Frame Sync 2 */
#define AT91_PB17_ERXDV (1 << 17) /* B: Ethernet Receive Data Valid */
#define AT91_PB18_RI1 (1 << 18) /* A: USART Ring Indicator 1 */
#define AT91_PB18_ECOL (1 << 18) /* B: Ethernet Collision Detected */
#define AT91_PB19_DTR1 (1 << 19) /* A: USART Data Terminal Ready 1 */
#define AT91_PB19_ERXCK (1 << 19) /* B: Ethernet Receive Clock */
#define AT91_PB20_TXD1 (1 << 20) /* A: USART Transmit Data 1 */
#define AT91_PB21_RXD1 (1 << 21) /* A: USART Receive Data 1 */
#define AT91_PB22_SCK1 (1 << 22) /* A: USART Serial Clock 1 */
#define AT91_PB23_DCD1 (1 << 23) /* A: USART Data Carrier Detect 1 */
#define AT91_PB24_CTS1 (1 << 24) /* A: USART Clear To Send 1 */
#define AT91_PB25_DSR1 (1 << 25) /* A: USART Data Set Ready 1 */
#define AT91_PB25_EF100 (1 << 25) /* B: Ethernet Force 100 Mbit */
#define AT91_PB26_RTS1 (1 << 26) /* A: USART Ready To Send 1 */
#define AT91_PB27_PCK0 (1 << 27) /* B: PMC Programmable Clock Output 0 */
#define AT91_PB28_FIQ (1 << 28) /* A: Fast Interrupt */
#define AT91_PB29_IRQ0 (1 << 29) /* A: External Interrupt 0 */
#define AT91_PC0_BFCK (1 << 0) /* A: Burst Flash Clock */
#define AT91_PC1_BFRDY_SMOE (1 << 1) /* A: Burst Flash Ready / SmartMedia Output Enable */
#define AT91_PC2_BFAVD (1 << 2) /* A: Burst Flash Address Valid */
#define AT91_PC3_BFBAA_SMWE (1 << 3) /* A: Burst Flash Address Advance / SmartMedia Write Enable */
#define AT91_PC4_BFOE (1 << 4) /* A: Burst Flash Output Enable */
#define AT91_PC5_BFWE (1 << 5) /* A: Burst Flash Write Enable */
#define AT91_PC6_NWAIT (1 << 6) /* A: SMC Wait Signal */
#define AT91_PC7_A23 (1 << 7) /* A: Address Bus 23 */
#define AT91_PC8_A24 (1 << 8) /* A: Address Bus 24 */
#define AT91_PC9_A25_CFRNW (1 << 9) /* A: Address Bus 25 / Compact Flash Read Not Write */
#define AT91_PC10_NCS4_CFCS (1 << 10) /* A: SMC Chip Select 4 / Compact Flash Chip Select */
#define AT91_PC11_NCS5_CFCE1 (1 << 11) /* A: SMC Chip Select 5 / Compact Flash Chip Enable 1 */
#define AT91_PC12_NCS6_CFCE2 (1 << 12) /* A: SMC Chip Select 6 / Compact Flash Chip Enable 2 */
#define AT91_PC13_NCS7 (1 << 13) /* A: Chip Select 7 */
#define AT91_PD0_ETX0 (1 << 0) /* A: Ethernet Transmit Data 0 */
#define AT91_PD1_ETX1 (1 << 1) /* A: Ethernet Transmit Data 1 */
#define AT91_PD2_ETX2 (1 << 2) /* A: Ethernet Transmit Data 2 */
#define AT91_PD3_ETX3 (1 << 3) /* A: Ethernet Transmit Data 3 */
#define AT91_PD4_ETXEN (1 << 4) /* A: Ethernet Transmit Enable */
#define AT91_PD5_ETXER (1 << 5) /* A: Ethernet Transmit Coding Error */
#define AT91_PD6_DTXD (1 << 6) /* A: DBGU Transmit Data */
#define AT91_PD7_PCK0 (1 << 7) /* A: PMC Programmable Clock Output 0 */
#define AT91_PD7_TSYNC (1 << 7) /* B: ETM Trace Synchronization Signal */
#define AT91_PD8_PCK1 (1 << 8) /* A: PMC Programmable Clock Output 1 */
#define AT91_PD8_TCLK (1 << 8) /* B: ETM Trace Clock */
#define AT91_PD9_PCK2 (1 << 9) /* A: PMC Programmable Clock Output 2 */
#define AT91_PD9_TPS0 (1 << 9) /* B: ETM Trace ARM Pipeline Status 0 */
#define AT91_PD10_PCK3 (1 << 10) /* A: PMC Programmable Clock Output 3 */
#define AT91_PD10_TPS1 (1 << 10) /* B: ETM Trace ARM Pipeline Status 1 */
#define AT91_PD11_TPS2 (1 << 11) /* B: ETM Trace ARM Pipeline Status 2 */
#define AT91_PD12_TPK0 (1 << 12) /* B: ETM Trace Packet Port 0 */
#define AT91_PD13_TPK1 (1 << 13) /* B: ETM Trace Packet Port 1 */
#define AT91_PD14_TPK2 (1 << 14) /* B: ETM Trace Packet Port 2 */
#define AT91_PD15_TD0 (1 << 15) /* A: SSC Transmit Data 0 */
#define AT91_PD15_TPK3 (1 << 15) /* B: ETM Trace Packet Port 3 */
#define AT91_PD16_TD1 (1 << 16) /* A: SSC Transmit Data 1 */
#define AT91_PD16_TPK4 (1 << 16) /* B: ETM Trace Packet Port 4 */
#define AT91_PD17_TD2 (1 << 17) /* A: SSC Transmit Data 2 */
#define AT91_PD17_TPK5 (1 << 17) /* B: ETM Trace Packet Port 5 */
#define AT91_PD18_NPCS1 (1 << 18) /* A: SPI Peripheral Chip Select 1 */
#define AT91_PD18_TPK6 (1 << 18) /* B: ETM Trace Packet Port 6 */
#define AT91_PD19_NPCS2 (1 << 19) /* A: SPI Peripheral Chip Select 2 */
#define AT91_PD19_TPK7 (1 << 19) /* B: ETM Trace Packet Port 7 */
#define AT91_PD20_NPCS3 (1 << 20) /* A: SPI Peripheral Chip Select 3 */
#define AT91_PD20_TPK8 (1 << 20) /* B: ETM Trace Packet Port 8 */
#define AT91_PD21_RTS0 (1 << 21) /* A: USART Ready To Send 0 */
#define AT91_PD21_TPK9 (1 << 21) /* B: ETM Trace Packet Port 9 */
#define AT91_PD22_RTS1 (1 << 22) /* A: USART Ready To Send 1 */
#define AT91_PD22_TPK10 (1 << 22) /* B: ETM Trace Packet Port 10 */
#define AT91_PD23_RTS2 (1 << 23) /* A: USART Ready To Send 2 */
#define AT91_PD23_TPK11 (1 << 23) /* B: ETM Trace Packet Port 11 */
#define AT91_PD24_RTS3 (1 << 24) /* A: USART Ready To Send 3 */
#define AT91_PD24_TPK12 (1 << 24) /* B: ETM Trace Packet Port 12 */
#define AT91_PD25_DTR1 (1 << 25) /* A: USART Data Terminal Ready 1 */
#define AT91_PD25_TPK13 (1 << 25) /* B: ETM Trace Packet Port 13 */
#define AT91_PD26_TPK14 (1 << 26) /* B: ETM Trace Packet Port 14 */
#define AT91_PD27_TPK15 (1 << 27) /* B: ETM Trace Packet Port 15 */
#endif

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/*
* include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91RM9200_SYS_H
#define AT91RM9200_SYS_H
/*
* Advanced Interrupt Controller.
*/
#define AT91_AIC 0x000
#define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */
#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */
#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */
#define AT91_AIC_SRCTYPE_LOW (0 << 5)
#define AT91_AIC_SRCTYPE_FALLING (1 << 5)
#define AT91_AIC_SRCTYPE_HIGH (2 << 5)
#define AT91_AIC_SRCTYPE_RISING (3 << 5)
#define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */
#define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */
#define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */
#define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */
#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */
#define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */
#define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */
#define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */
#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */
#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */
#define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */
#define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */
#define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */
#define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */
#define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */
#define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */
#define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */
#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */
#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */
/*
* Debug Unit.
*/
#define AT91_DBGU 0x200
#define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */
#define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */
#define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */
#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
#define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */
#define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */
#define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */
#define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */
#define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */
#define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */
#define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */
#define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */
/*
* PIO Controllers.
*/
#define AT91_PIOA 0x400
#define AT91_PIOB 0x600
#define AT91_PIOC 0x800
#define AT91_PIOD 0xa00
#define PIO_PER 0x00 /* Enable Register */
#define PIO_PDR 0x04 /* Disable Register */
#define PIO_PSR 0x08 /* Status Register */
#define PIO_OER 0x10 /* Output Enable Register */
#define PIO_ODR 0x14 /* Output Disable Register */
#define PIO_OSR 0x18 /* Output Status Register */
#define PIO_IFER 0x20 /* Glitch Input Filter Enable */
#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
#define PIO_IFSR 0x28 /* Glitch Input Filter Status */
#define PIO_SODR 0x30 /* Set Output Data Register */
#define PIO_CODR 0x34 /* Clear Output Data Register */
#define PIO_ODSR 0x38 /* Output Data Status Register */
#define PIO_PDSR 0x3c /* Pin Data Status Register */
#define PIO_IER 0x40 /* Interrupt Enable Register */
#define PIO_IDR 0x44 /* Interrupt Disable Register */
#define PIO_IMR 0x48 /* Interrupt Mask Register */
#define PIO_ISR 0x4c /* Interrupt Status Register */
#define PIO_MDER 0x50 /* Multi-driver Enable Register */
#define PIO_MDDR 0x54 /* Multi-driver Disable Register */
#define PIO_MDSR 0x58 /* Multi-driver Status Register */
#define PIO_PUDR 0x60 /* Pull-up Disable Register */
#define PIO_PUER 0x64 /* Pull-up Enable Register */
#define PIO_PUSR 0x68 /* Pull-up Status Register */
#define PIO_ASR 0x70 /* Peripheral A Select Register */
#define PIO_BSR 0x74 /* Peripheral B Select Register */
#define PIO_ABSR 0x78 /* AB Status Register */
#define PIO_OWER 0xa0 /* Output Write Enable Register */
#define PIO_OWDR 0xa4 /* Output Write Disable Register */
#define PIO_OWSR 0xa8 /* Output Write Status Register */
#define AT91_PIO_P(n) (1 << (n))
/*
* Power Management Controller.
*/
#define AT91_PMC 0xc00
#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
#define AT91_PMC_UDP (1 << 1) /* USB Devcice Port Clock */
#define AT91_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend */
#define AT91_PMC_UHP (1 << 4) /* USB Host Port Clock */
#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register */
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
#define AT91_PMC_DIV (0xff << 0) /* Divider */
#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
#define AT91_PMC_CSS_SLOW (0 << 0)
#define AT91_PMC_CSS_MAIN (1 << 0)
#define AT91_PMC_CSS_PLLA (2 << 0)
#define AT91_PMC_CSS_PLLB (3 << 0)
#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
#define AT91_PMC_PRES_1 (0 << 2)
#define AT91_PMC_PRES_2 (1 << 2)
#define AT91_PMC_PRES_4 (2 << 2)
#define AT91_PMC_PRES_8 (3 << 2)
#define AT91_PMC_PRES_16 (4 << 2)
#define AT91_PMC_PRES_32 (5 << 2)
#define AT91_PMC_PRES_64 (6 << 2)
#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
#define AT91_PMC_MDIV_1 (0 << 8)
#define AT91_PMC_MDIV_2 (1 << 8)
#define AT91_PMC_MDIV_3 (2 << 8)
#define AT91_PMC_MDIV_4 (3 << 8)
#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
/*
* System Timer.
*/
#define AT91_ST 0xd00
#define AT91_ST_CR (AT91_ST + 0x00) /* Control Register */
#define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */
#define AT91_ST_PIMR (AT91_ST + 0x04) /* Period Interval Mode Register */
#define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */
#define AT91_ST_WDMR (AT91_ST + 0x08) /* Watchdog Mode Register */
#define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */
#define AT91_ST_RSTEN (1 << 16) /* Reset Enable */
#define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */
#define AT91_ST_RTMR (AT91_ST + 0x0c) /* Real-time Mode Register */
#define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */
#define AT91_ST_SR (AT91_ST + 0x10) /* Status Register */
#define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */
#define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */
#define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */
#define AT91_ST_ALMS (1 << 3) /* Alarm Status */
#define AT91_ST_IER (AT91_ST + 0x14) /* Interrupt Enable Register */
#define AT91_ST_IDR (AT91_ST + 0x18) /* Interrupt Disable Register */
#define AT91_ST_IMR (AT91_ST + 0x1c) /* Interrupt Mask Register */
#define AT91_ST_RTAR (AT91_ST + 0x20) /* Real-time Alarm Register */
#define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */
#define AT91_ST_CRTR (AT91_ST + 0x24) /* Current Real-time Register */
#define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */
/*
* Real-time Clock.
*/
#define AT91_RTC 0xe00
#define AT91_RTC_CR (AT91_RTC + 0x00) /* Control Register */
#define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time Register */
#define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */
#define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */
#define AT91_RTC_TIMEVSEL_MINUTE (0 << 8)
#define AT91_RTC_TIMEVSEL_HOUR (1 << 8)
#define AT91_RTC_TIMEVSEL_DAY24 (2 << 8)
#define AT91_RTC_TIMEVSEL_DAY12 (3 << 8)
#define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */
#define AT91_RTC_CALEVSEL_WEEK (0 << 16)
#define AT91_RTC_CALEVSEL_MONTH (1 << 16)
#define AT91_RTC_CALEVSEL_YEAR (2 << 16)
#define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */
#define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */
#define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */
#define AT91_RTC_SEC (0x7f << 0) /* Current Second */
#define AT91_RTC_MIN (0x7f << 8) /* Current Minute */
#define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */
#define At91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */
#define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */
#define AT91_RTC_CENT (0x7f << 0) /* Current Century */
#define AT91_RTC_YEAR (0xff << 8) /* Current Year */
#define AT91_RTC_MONTH (0x1f << 16) /* Current Month */
#define AT91_RTC_DAY (7 << 21) /* Current Day */
#define AT91_RTC_DATE (0x3f << 24) /* Current Date */
#define AT91_RTC_TIMALR (AT91_RTC + 0x10) /* Time Alarm Register */
#define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enable */
#define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enable */
#define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */
#define AT91_RTC_CALALR (AT91_RTC + 0x14) /* Calendar Alarm Register */
#define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */
#define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */
#define AT91_RTC_SR (AT91_RTC + 0x18) /* Status Register */
#define AT91_RTC_ACKUPD (1 << 0) /* Acknowledge for Update */
#define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */
#define AT91_RTC_SECEV (1 << 2) /* Second Event */
#define AT91_RTC_TIMEV (1 << 3) /* Time Event */
#define AT91_RTC_CALEV (1 << 4) /* Calendar Event */
#define AT91_RTC_SCCR (AT91_RTC + 0x1c) /* Status Clear Command Register */
#define AT91_RTC_IER (AT91_RTC + 0x20) /* Interrupt Enable Register */
#define AT91_RTC_IDR (AT91_RTC + 0x24) /* Interrupt Disable Register */
#define AT91_RTC_IMR (AT91_RTC + 0x28) /* Interrupt Mask Register */
#define AT91_RTC_VER (AT91_RTC + 0x2c) /* Valid Entry Register */
#define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */
#define AT91_RTC_NVCAL (1 << 1) /* Non valid Calendar */
#define AT91_RTC_NVTIMALR (1 << 2) /* Non valid Time Alarm */
#define AT91_RTC_NVCALALR (1 << 3) /* Non valid Calendar Alarm */
/*
* Memory Controller.
*/
#define AT91_MC 0xf00
#define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */
#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
#define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */
#define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */
#define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */
/* External Bus Interface (EBI) registers */
#define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */
#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */
#define AT91_EBI_CS0A_SMC (0 << 0)
#define AT91_EBI_CS0A_BFC (1 << 0)
#define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_EBI_CS1A_SMC (0 << 1)
#define AT91_EBI_CS1A_SDRAMC (1 << 1)
#define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */
#define AT91_EBI_CS3A_SMC (0 << 3)
#define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
#define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */
#define AT91_EBI_CS4A_SMC (0 << 4)
#define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4)
#define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */
#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */
/* Static Memory Controller (SMC) registers */
#define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
#define AT91_SMC_TDF (0xf << 8) /* Data Float Time */
#define AT91_SMC_BAT (1 << 12) /* Byte Access Type */
#define AT91_SMC_DBW (3 << 13) /* Data Bus Width */
#define AT91_SMC_DBW_16 (1 << 13)
#define AT91_SMC_DBW_8 (2 << 13)
#define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */
#define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */
#define AT91_SMC_ACSS_STD (0 << 16)
#define AT91_SMC_ACSS_1 (1 << 16)
#define AT91_SMC_ACSS_2 (2 << 16)
#define AT91_SMC_ACSS_3 (3 << 16)
#define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */
#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
#endif

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/*
* include/asm-arm/arch-at91rm9200/board.h
*
* Copyright (C) 2005 HP Labs
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
* These are data structures found in platform_device.dev.platform_data,
* and describing board-specfic data needed by drivers. For example,
* which pin is used for a given GPIO role.
*
* In 2.6, drivers should strongly avoid board-specific knowledge so
* that supporting new boards normally won't require driver patches.
* Most board-specific knowledge should be in arch/.../board-*.c files.
*/
#ifndef __ASM_ARCH_BOARD_H
#define __ASM_ARCH_BOARD_H
/* Clocks */
extern unsigned long at91_master_clock;
/* Serial Port */
extern int at91_serial_map[AT91_NR_UART];
extern int at91_console_port;
/* USB Device */
struct at91_udc_data {
u8 vbus_pin; /* high == host powering us */
u8 pullup_pin; /* high == D+ pulled up */
};
extern void __init at91_add_device_udc(struct at91_udc_data *data);
/* Compact Flash */
struct at91_cf_data {
u8 irq_pin; /* I/O IRQ */
u8 det_pin; /* Card detect */
u8 vcc_pin; /* power switching */
u8 rst_pin; /* card reset */
};
extern void __init at91_add_device_cf(struct at91_cf_data *data);
/* MMC / SD */
struct at91_mmc_data {
u8 det_pin; /* card detect IRQ */
unsigned is_b:1; /* uses B side (vs A) */
unsigned wire4:1; /* (SD) supports DAT0..DAT3 */
u8 wp_pin; /* (SD) writeprotect detect */
u8 vcc_pin; /* power switching (high == on) */
};
extern void __init at91_add_device_mmc(struct at91_mmc_data *data);
/* Ethernet */
struct at91_eth_data {
u8 phy_irq_pin; /* PHY IRQ */
u8 is_rmii; /* using RMII interface? */
};
extern void __init at91_add_device_eth(struct at91_eth_data *data);
/* USB Host */
struct at91_usbh_data {
u8 ports; /* number of ports on root hub */
};
extern void __init at91_add_device_usbh(struct at91_usbh_data *data);
#endif

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/*
* include/asm-arm/arch-at91rm9200/debug-macro.S
*
* Copyright (C) 2003-2005 SAN People
*
* Debugging macro include header
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <asm/hardware.h>
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
ldreq \rx, =AT91_BASE_SYS @ System peripherals (phys address)
ldrne \rx, =AT91_VA_BASE_SYS @ System peripherals (virt address)
.endm
.macro senduart,rd,rx
strb \rd, [\rx, #AT91_DBGU_THR] @ Write to Transmitter Holding Register
.endm
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #AT91_DBGU_SR] @ Read Status Register
tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit
beq 1001b
.endm
.macro busyuart,rd,rx
1001: ldr \rd, [\rx, #AT91_DBGU_SR] @ Read Status Register
tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete
beq 1001b
.endm

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/*
* include/asm-arm/arch-at91rm9200/dma.h
*
* Copyright (C) 2003 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H
#define MAX_DMA_ADDRESS 0xffffffff
#define MAX_DMA_CHANNELS 0
#endif /* _ASM_ARCH_DMA_H */

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/*
* include/asm-arm/arch-at91rm9200/entry-macro.S
*
* Copyright (C) 2003-2005 SAN People
*
* Low-level IRQ helper macros for AT91RM9200 platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <asm/hardware.h>
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \base, =(AT91_VA_BASE_SYS) @ base virtual address of SYS peripherals
ldr \irqnr, [\base, #AT91_AIC_IVR] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
ldr \irqstat, [\base, #AT91_AIC_ISR] @ read interrupt source number
teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt
streq \tmp, [\base, #AT91_AIC_EOICR] @ not going to be handled further, then ACK it now.
.endm

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/*
* include/asm-arm/arch-at91rm9200/gpio.h
*
* Copyright (C) 2005 HP Labs
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef __ASM_ARCH_AT91RM9200_GPIO_H
#define __ASM_ARCH_AT91RM9200_GPIO_H
#define PIN_BASE NR_AIC_IRQS
#define PQFP_GPIO_BANKS 3 /* PQFP package has 3 banks */
#define BGA_GPIO_BANKS 4 /* BGA package has 4 banks */
/* these pin numbers double as IRQ numbers, like AT91_ID_* values */
#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0)
#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1)
#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2)
#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3)
#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4)
#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5)
#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6)
#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7)
#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8)
#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9)
#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10)
#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11)
#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12)
#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13)
#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14)
#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15)
#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16)
#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17)
#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18)
#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19)
#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20)
#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21)
#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22)
#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23)
#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24)
#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25)
#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26)
#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27)
#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28)
#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29)
#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30)
#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31)
#define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0)
#define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1)
#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2)
#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3)
#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4)
#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5)
#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6)
#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7)
#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8)
#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9)
#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10)
#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11)
#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12)
#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13)
#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14)
#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15)
#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16)
#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17)
#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18)
#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19)
#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20)
#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21)
#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22)
#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23)
#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24)
#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25)
#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26)
#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27)
#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28)
#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29)
#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30)
#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31)
#define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0)
#define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1)
#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2)
#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3)
#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4)
#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5)
#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6)
#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7)
#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8)
#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9)
#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10)
#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11)
#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12)
#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13)
#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14)
#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15)
#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16)
#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17)
#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18)
#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19)
#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20)
#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21)
#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22)
#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23)
#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24)
#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25)
#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26)
#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27)
#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28)
#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29)
#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30)
#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31)
#define AT91_PIN_PD0 (PIN_BASE + 0x60 + 0)
#define AT91_PIN_PD1 (PIN_BASE + 0x60 + 1)
#define AT91_PIN_PD2 (PIN_BASE + 0x60 + 2)
#define AT91_PIN_PD3 (PIN_BASE + 0x60 + 3)
#define AT91_PIN_PD4 (PIN_BASE + 0x60 + 4)
#define AT91_PIN_PD5 (PIN_BASE + 0x60 + 5)
#define AT91_PIN_PD6 (PIN_BASE + 0x60 + 6)
#define AT91_PIN_PD7 (PIN_BASE + 0x60 + 7)
#define AT91_PIN_PD8 (PIN_BASE + 0x60 + 8)
#define AT91_PIN_PD9 (PIN_BASE + 0x60 + 9)
#define AT91_PIN_PD10 (PIN_BASE + 0x60 + 10)
#define AT91_PIN_PD11 (PIN_BASE + 0x60 + 11)
#define AT91_PIN_PD12 (PIN_BASE + 0x60 + 12)
#define AT91_PIN_PD13 (PIN_BASE + 0x60 + 13)
#define AT91_PIN_PD14 (PIN_BASE + 0x60 + 14)
#define AT91_PIN_PD15 (PIN_BASE + 0x60 + 15)
#define AT91_PIN_PD16 (PIN_BASE + 0x60 + 16)
#define AT91_PIN_PD17 (PIN_BASE + 0x60 + 17)
#define AT91_PIN_PD18 (PIN_BASE + 0x60 + 18)
#define AT91_PIN_PD19 (PIN_BASE + 0x60 + 19)
#define AT91_PIN_PD20 (PIN_BASE + 0x60 + 20)
#define AT91_PIN_PD21 (PIN_BASE + 0x60 + 21)
#define AT91_PIN_PD22 (PIN_BASE + 0x60 + 22)
#define AT91_PIN_PD23 (PIN_BASE + 0x60 + 23)
#define AT91_PIN_PD24 (PIN_BASE + 0x60 + 24)
#define AT91_PIN_PD25 (PIN_BASE + 0x60 + 25)
#define AT91_PIN_PD26 (PIN_BASE + 0x60 + 26)
#define AT91_PIN_PD27 (PIN_BASE + 0x60 + 27)
#define AT91_PIN_PD28 (PIN_BASE + 0x60 + 28)
#define AT91_PIN_PD29 (PIN_BASE + 0x60 + 29)
#define AT91_PIN_PD30 (PIN_BASE + 0x60 + 30)
#define AT91_PIN_PD31 (PIN_BASE + 0x60 + 31)
#ifndef __ASSEMBLY__
/* setup setup routines, called from board init or driver probe() */
extern int at91_set_A_periph(unsigned pin, int use_pullup);
extern int at91_set_B_periph(unsigned pin, int use_pullup);
extern int at91_set_gpio_input(unsigned pin, int use_pullup);
extern int at91_set_gpio_output(unsigned pin, int value);
extern int at91_set_deglitch(unsigned pin, int is_on);
/* callable at any time */
extern int at91_set_gpio_value(unsigned pin, int value);
extern int at91_get_gpio_value(unsigned pin);
#endif
#endif

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/*
* include/asm-arm/arch-at91rm9200/hardware.h
*
* Copyright (C) 2003 SAN People
* Copyright (C) 2003 ATMEL
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <asm/sizes.h>
#include <asm/arch/at91rm9200.h>
#include <asm/arch/at91rm9200_sys.h>
/*
* Remap the peripherals from address 0xFFFA0000 .. 0xFFFFFFFF
* to 0xFEFA0000 .. 0xFF000000. (384Kb)
*/
#define AT91_IO_PHYS_BASE 0xFFFA0000
#define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1)
#define AT91_IO_VIRT_BASE (0xFF000000 - AT91_IO_SIZE)
/* Convert a physical IO address to virtual IO address */
#define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE)
/*
* Virtual to Physical Address mapping for IO devices.
*/
#define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS)
#define AT91_VA_BASE_SPI AT91_IO_P2V(AT91_BASE_SPI)
#define AT91_VA_BASE_SSC2 AT91_IO_P2V(AT91_BASE_SSC2)
#define AT91_VA_BASE_SSC1 AT91_IO_P2V(AT91_BASE_SSC1)
#define AT91_VA_BASE_SSC0 AT91_IO_P2V(AT91_BASE_SSC0)
#define AT91_VA_BASE_US3 AT91_IO_P2V(AT91_BASE_US3)
#define AT91_VA_BASE_US2 AT91_IO_P2V(AT91_BASE_US2)
#define AT91_VA_BASE_US1 AT91_IO_P2V(AT91_BASE_US1)
#define AT91_VA_BASE_US0 AT91_IO_P2V(AT91_BASE_US0)
#define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91_BASE_EMAC)
#define AT91_VA_BASE_TWI AT91_IO_P2V(AT91_BASE_TWI)
#define AT91_VA_BASE_MCI AT91_IO_P2V(AT91_BASE_MCI)
#define AT91_VA_BASE_UDP AT91_IO_P2V(AT91_BASE_UDP)
#define AT91_VA_BASE_TCB1 AT91_IO_P2V(AT91_BASE_TCB1)
#define AT91_VA_BASE_TCB0 AT91_IO_P2V(AT91_BASE_TCB0)
/* Internal SRAM */
#define AT91_BASE_SRAM 0x00200000 /* Internal SRAM base address */
#define AT91_SRAM_SIZE 0x00004000 /* Internal SRAM SIZE (16Kb) */
/* Serial ports */
#define AT91_NR_UART 5 /* 4 USART3's and one DBGU port */
/* FLASH */
#define AT91_FLASH_BASE 0x10000000 /* NCS0: Flash physical base address */
/* SDRAM */
#define AT91_SDRAM_BASE 0x20000000 /* NCS1: SDRAM physical base address */
/* SmartMedia */
#define AT91_SMARTMEDIA_BASE 0x40000000 /* NCS3: Smartmedia physical base address */
/* Multi-Master Memory controller */
#define AT91_UHP_BASE 0x00300000 /* USB Host controller */
/* Clocks */
#define AT91_SLOW_CLOCK 32768 /* slow clock */
#ifndef __ASSEMBLY__
#include <asm/io.h>
static inline unsigned int at91_sys_read(unsigned int reg_offset)
{
void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
return readl(addr + reg_offset);
}
static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
{
void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
writel(value, addr + reg_offset);
}
#endif
#endif

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/*
* include/asm-arm/arch-at91rm9200/io.h
*
* Copyright (C) 2003 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_IO_H
#define __ASM_ARCH_IO_H
#include <asm/arch/at91rm9200.h>
#include <asm/io.h>
#define IO_SPACE_LIMIT 0xFFFFFFFF
#define __io(a) ((void __iomem *)(a))
#define __mem_pci(a) (a)
#endif

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/*
* include/asm-arm/arch-at91rm9200/irqs.h
*
* Copyright (C) 2004 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
#define NR_AIC_IRQS 32
/*
* Acknowledge interrupt with AIC after interrupt has been handled.
* (by kernel/irq.c)
*/
#define irq_finish(irq) do { at91_sys_write(AT91_AIC_EOICR, 0); } while (0)
/*
* IRQ interrupt symbols are the AT91_ID_* symbols in at91rm9200.h
* for IRQs handled directly through the AIC, or else the AT91_PIN_*
* symbols in gpio.h for ones handled indirectly as GPIOs.
* We make provision for 4 banks of GPIO.
*/
#include <asm/arch/gpio.h>
#define NR_IRQS (NR_AIC_IRQS + (4 * 32))
#ifndef __ASSEMBLY__
/*
* Initialize the IRQ controller.
*/
extern void at91rm9200_init_irq(unsigned int priority[]);
#endif
#endif

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/*
* include/asm-arm/arch-at91rm9200/memory.h
*
* Copyright (C) 2004 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
#include <asm/arch/hardware.h>
#define PHYS_OFFSET (AT91_SDRAM_BASE)
/*
* Virtual view <-> DMA view memory address translations
* virt_to_bus: Used to translate the virtual address to an
* address suitable to be passed to set_dma_addr
* bus_to_virt: Used to convert an address for DMA operations
* to an address that the kernel can use.
*/
#define __virt_to_bus__is_a_macro
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt__is_a_macro
#define __bus_to_virt(x) __phys_to_virt(x)
#endif

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/*
* include/asm-arm/arch-at91rm9200/param.h
*
* Copyright (C) 2003 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_PARAM_H
#define __ASM_ARCH_PARAM_H
/*
* We use default params
*/
#endif

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/*
* include/asm-arm/arch-at91rm9200/pio.h
*
* Copyright (C) 2003 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef __ASM_ARCH_PIO_H
#define __ASM_ARCH_PIO_H
#include <asm/arch/hardware.h>
static inline void AT91_CfgPIO_USART0(void) {
at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA17_TXD0 | AT91_PA18_RXD0 | AT91_PA20_CTS0);
/*
* Errata #39 - RTS0 is not internally connected to PA21. We need to drive
* the pin manually. Default is off (RTS is active low).
*/
at91_sys_write(AT91_PIOA + PIO_PER, AT91_PA21_RTS0);
at91_sys_write(AT91_PIOA + PIO_OER, AT91_PA21_RTS0);
at91_sys_write(AT91_PIOA + PIO_SODR, AT91_PA21_RTS0);
}
static inline void AT91_CfgPIO_USART1(void) {
at91_sys_write(AT91_PIOB + PIO_PDR, AT91_PB18_RI1 | AT91_PB19_DTR1
| AT91_PB20_TXD1 | AT91_PB21_RXD1 | AT91_PB23_DCD1
| AT91_PB24_CTS1 | AT91_PB25_DSR1 | AT91_PB26_RTS1);
}
static inline void AT91_CfgPIO_USART2(void) {
at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA22_RXD2 | AT91_PA23_TXD2);
}
static inline void AT91_CfgPIO_USART3(void) {
at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA5_TXD3 | AT91_PA6_RXD3);
at91_sys_write(AT91_PIOA + PIO_BSR, AT91_PA5_TXD3 | AT91_PA6_RXD3);
}
static inline void AT91_CfgPIO_DBGU(void) {
at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA31_DTXD | AT91_PA30_DRXD);
}
/*
* Enable the Two-Wire interface.
*/
static inline void AT91_CfgPIO_TWI(void) {
at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA25_TWD | AT91_PA26_TWCK);
at91_sys_write(AT91_PIOA + PIO_ASR, AT91_PA25_TWD | AT91_PA26_TWCK);
at91_sys_write(AT91_PIOA + PIO_MDER, AT91_PA25_TWD | AT91_PA26_TWCK); /* open drain */
}
/*
* Enable the Serial Peripheral Interface.
*/
static inline void AT91_CfgPIO_SPI(void) {
at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA0_MISO | AT91_PA1_MOSI | AT91_PA2_SPCK);
}
static inline void AT91_CfgPIO_SPI_CS0(void) {
at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA3_NPCS0);
}
static inline void AT91_CfgPIO_SPI_CS1(void) {
at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA4_NPCS1);
}
static inline void AT91_CfgPIO_SPI_CS2(void) {
at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA5_NPCS2);
}
static inline void AT91_CfgPIO_SPI_CS3(void) {
at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA6_NPCS3);
}
/*
* Select the DataFlash card.
*/
static inline void AT91_CfgPIO_DataFlashCard(void) {
at91_sys_write(AT91_PIOB + PIO_PER, AT91_PIO_P(7));
at91_sys_write(AT91_PIOB + PIO_OER, AT91_PIO_P(7));
at91_sys_write(AT91_PIOB + PIO_CODR, AT91_PIO_P(7));
}
/*
* Enable NAND Flash (SmartMedia) interface.
*/
static inline void AT91_CfgPIO_SmartMedia(void) {
/* enable PC0=SMCE, PC1=SMOE, PC3=SMWE, A21=CLE, A22=ALE */
at91_sys_write(AT91_PIOC + PIO_ASR, AT91_PC0_BFCK | AT91_PC1_BFRDY_SMOE | AT91_PC3_BFBAA_SMWE);
at91_sys_write(AT91_PIOC + PIO_PDR, AT91_PC0_BFCK | AT91_PC1_BFRDY_SMOE | AT91_PC3_BFBAA_SMWE);
/* Configure PC2 as input (signal READY of the SmartMedia) */
at91_sys_write(AT91_PIOC + PIO_PER, AT91_PC2_BFAVD); /* enable direct output enable */
at91_sys_write(AT91_PIOC + PIO_ODR, AT91_PC2_BFAVD); /* disable output */
/* Configure PB1 as input (signal Card Detect of the SmartMedia) */
at91_sys_write(AT91_PIOB + PIO_PER, AT91_PIO_P(1)); /* enable direct output enable */
at91_sys_write(AT91_PIOB + PIO_ODR, AT91_PIO_P(1)); /* disable output */
}
static inline int AT91_PIO_SmartMedia_RDY(void) {
return (at91_sys_read(AT91_PIOC + PIO_PDSR) & AT91_PIO_P(2)) ? 1 : 0;
}
static inline int AT91_PIO_SmartMedia_CardDetect(void) {
return (at91_sys_read(AT91_PIOB + PIO_PDSR) & AT91_PIO_P(1)) ? 1 : 0;
}
#endif

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/*
* include/asm-arm/arch-at91rm9200/system.h
*
* Copyright (C) 2003 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
#include <asm/arch/hardware.h>
static inline void arch_idle(void)
{
/*
* Disable the processor clock. The processor will be automatically
* re-enabled by an interrupt or by a reset.
*/
// at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
/*
* Set the processor (CP15) into 'Wait for Interrupt' mode.
* Unlike disabling the processor clock via the PMC (above)
* this allows the processor to be woken via JTAG.
*/
cpu_do_idle();
}
static inline void arch_reset(char mode)
{
/*
* Perform a hardware reset with the use of the Watchdog timer.
*/
at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
}
#endif

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include/asm-arm/arch-at91rm9200/timex.h Normal file
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/*
* include/asm-arm/arch-at91rm9200/timex.h
*
* Copyright (C) 2003 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_TIMEX_H
#define __ASM_ARCH_TIMEX_H
#include <asm/arch/hardware.h>
#define CLOCK_TICK_RATE (AT91_SLOW_CLOCK)
#endif

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include/asm-arm/arch-at91rm9200/uncompress.h Normal file
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/*
* include/asm-arm/arch-at91rm9200/uncompress.h
*
* Copyright (C) 2003 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_UNCOMPRESS_H
#define __ASM_ARCH_UNCOMPRESS_H
#include <asm/arch/hardware.h>
/*
* The following code assumes the serial port has already been
* initialized by the bootloader. We search for the first enabled
* port in the most probable order. If you didn't setup a port in
* your bootloader then nothing will appear (which might be desired).
*
* This does not append a newline
*/
static void putstr(const char *s)
{
void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */
while (*s) {
while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) { barrier(); }
__raw_writel(*s, sys + AT91_DBGU_THR);
if (*s == '\n') {
while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) { barrier(); }
__raw_writel('\r', sys + AT91_DBGU_THR);
}
s++;
}
/* wait for transmission to complete */
while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXEMPTY)) { barrier(); }
}
#define arch_decomp_setup()
#define arch_decomp_wdog()
#endif

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include/asm-arm/arch-at91rm9200/vmalloc.h Normal file
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/*
* include/asm-arm/arch-at91rm9200/vmalloc.h
*
* Copyright (C) 2003 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
#define VMALLOC_END (AT91_IO_VIRT_BASE & PGDIR_MASK)
#endif