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GPIO: xilinx: Add support for dual channel
Supporting the second channel in the driver. Offset is 0x8 and both channnels share the same IRQ. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Michal Simek
Linus Walleij
parent
6f8bf50031
commit
74600ee017
@ -1,7 +1,7 @@
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/*
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* Xilinx gpio driver
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* Xilinx gpio driver for xps/axi_gpio IP.
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*
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* Copyright 2008 Xilinx, Inc.
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* Copyright 2008 - 2013 Xilinx, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2
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@ -12,6 +12,7 @@
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/bitops.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/module.h>
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@ -26,11 +27,26 @@
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#define XGPIO_DATA_OFFSET (0x0) /* Data register */
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#define XGPIO_TRI_OFFSET (0x4) /* I/O direction register */
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#define XGPIO_CHANNEL_OFFSET 0x8
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/* Read/Write access to the GPIO registers */
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#define xgpio_readreg(offset) in_be32(offset)
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#define xgpio_writereg(offset, val) out_be32(offset, val)
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/**
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* struct xgpio_instance - Stores information about GPIO device
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* struct of_mm_gpio_chip mmchip: OF GPIO chip for memory mapped banks
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* gpio_state: GPIO state shadow register
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* gpio_dir: GPIO direction shadow register
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* offset: GPIO channel offset
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* gpio_lock: Lock used for synchronization
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*/
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struct xgpio_instance {
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struct of_mm_gpio_chip mmchip;
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u32 gpio_state; /* GPIO state shadow register */
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u32 gpio_dir; /* GPIO direction shadow register */
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spinlock_t gpio_lock; /* Lock used for synchronization */
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u32 gpio_state;
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u32 gpio_dir;
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u32 offset;
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spinlock_t gpio_lock;
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};
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/**
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@ -44,8 +60,12 @@ struct xgpio_instance {
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static int xgpio_get(struct gpio_chip *gc, unsigned int gpio)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct xgpio_instance *chip =
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container_of(mm_gc, struct xgpio_instance, mmchip);
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return (in_be32(mm_gc->regs + XGPIO_DATA_OFFSET) >> gpio) & 1;
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void __iomem *regs = mm_gc->regs + chip->offset;
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return !!(xgpio_readreg(regs + XGPIO_DATA_OFFSET) & BIT(gpio));
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}
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/**
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@ -63,6 +83,7 @@ static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct xgpio_instance *chip =
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container_of(mm_gc, struct xgpio_instance, mmchip);
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void __iomem *regs = mm_gc->regs;
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spin_lock_irqsave(&chip->gpio_lock, flags);
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@ -71,7 +92,9 @@ static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
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chip->gpio_state |= 1 << gpio;
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else
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chip->gpio_state &= ~(1 << gpio);
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out_be32(mm_gc->regs + XGPIO_DATA_OFFSET, chip->gpio_state);
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xgpio_writereg(regs + chip->offset + XGPIO_DATA_OFFSET,
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chip->gpio_state);
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spin_unlock_irqrestore(&chip->gpio_lock, flags);
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}
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@ -91,12 +114,13 @@ static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct xgpio_instance *chip =
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container_of(mm_gc, struct xgpio_instance, mmchip);
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void __iomem *regs = mm_gc->regs;
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spin_lock_irqsave(&chip->gpio_lock, flags);
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/* Set the GPIO bit in shadow register and set direction as input */
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chip->gpio_dir |= (1 << gpio);
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out_be32(mm_gc->regs + XGPIO_TRI_OFFSET, chip->gpio_dir);
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xgpio_writereg(regs + chip->offset + XGPIO_TRI_OFFSET, chip->gpio_dir);
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spin_unlock_irqrestore(&chip->gpio_lock, flags);
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@ -119,6 +143,7 @@ static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct xgpio_instance *chip =
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container_of(mm_gc, struct xgpio_instance, mmchip);
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void __iomem *regs = mm_gc->regs;
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spin_lock_irqsave(&chip->gpio_lock, flags);
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@ -127,11 +152,12 @@ static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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chip->gpio_state |= 1 << gpio;
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else
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chip->gpio_state &= ~(1 << gpio);
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out_be32(mm_gc->regs + XGPIO_DATA_OFFSET, chip->gpio_state);
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xgpio_writereg(regs + chip->offset + XGPIO_DATA_OFFSET,
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chip->gpio_state);
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/* Clear the GPIO bit in shadow register and set direction as output */
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chip->gpio_dir &= (~(1 << gpio));
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out_be32(mm_gc->regs + XGPIO_TRI_OFFSET, chip->gpio_dir);
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xgpio_writereg(regs + chip->offset + XGPIO_TRI_OFFSET, chip->gpio_dir);
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spin_unlock_irqrestore(&chip->gpio_lock, flags);
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@ -147,8 +173,10 @@ static void xgpio_save_regs(struct of_mm_gpio_chip *mm_gc)
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struct xgpio_instance *chip =
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container_of(mm_gc, struct xgpio_instance, mmchip);
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out_be32(mm_gc->regs + XGPIO_DATA_OFFSET, chip->gpio_state);
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out_be32(mm_gc->regs + XGPIO_TRI_OFFSET, chip->gpio_dir);
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xgpio_writereg(mm_gc->regs + chip->offset + XGPIO_DATA_OFFSET,
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chip->gpio_state);
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xgpio_writereg(mm_gc->regs + chip->offset + XGPIO_TRI_OFFSET,
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chip->gpio_dir);
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}
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/**
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@ -202,6 +230,57 @@ static int xgpio_of_probe(struct device_node *np)
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np->full_name, status);
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return status;
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}
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pr_info("XGpio: %s: registered, base is %d\n", np->full_name,
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chip->mmchip.gc.base);
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tree_info = of_get_property(np, "xlnx,is-dual", NULL);
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if (tree_info && be32_to_cpup(tree_info)) {
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chip = kzalloc(sizeof(*chip), GFP_KERNEL);
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if (!chip)
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return -ENOMEM;
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/* Add dual channel offset */
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chip->offset = XGPIO_CHANNEL_OFFSET;
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/* Update GPIO state shadow register with default value */
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of_property_read_u32(np, "xlnx,dout-default-2",
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&chip->gpio_state);
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/* By default, all pins are inputs */
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chip->gpio_dir = 0xFFFFFFFF;
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/* Update GPIO direction shadow register with default value */
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of_property_read_u32(np, "xlnx,tri-default-2", &chip->gpio_dir);
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/* By default assume full GPIO controller */
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chip->mmchip.gc.ngpio = 32;
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/* Check device node and parent device node for device width */
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of_property_read_u32(np, "xlnx,gpio2-width",
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(u32 *)&chip->mmchip.gc.ngpio);
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spin_lock_init(&chip->gpio_lock);
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chip->mmchip.gc.direction_input = xgpio_dir_in;
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chip->mmchip.gc.direction_output = xgpio_dir_out;
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chip->mmchip.gc.get = xgpio_get;
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chip->mmchip.gc.set = xgpio_set;
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chip->mmchip.save_regs = xgpio_save_regs;
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/* Call the OF gpio helper to setup and register the GPIO dev */
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status = of_mm_gpiochip_add(np, &chip->mmchip);
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if (status) {
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kfree(chip);
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pr_err("%s: error in probe function with status %d\n",
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np->full_name, status);
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return status;
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}
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pr_info("XGpio: %s: dual channel registered, base is %d\n",
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np->full_name, chip->mmchip.gc.base);
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}
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return 0;
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}
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