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Merge branch 'next/devel-samsung-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc
From Kukjin Kim: This is including Samsung small updates(developments) for v3.8. Add node PL330 MDMA1 and UART3 for DEBUG_LL and secondary cpu bring-up for exynos4412. * 'next/devel-samsung-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: dts: add node for PL330 MDMA1 controller for exynos4 ARM: EXYNOS: Add support for secondary CPU bring-up on Exynos4412 ARM: EXYNOS: add UART3 to DEBUG_LL ports Signed-off-by: Olof Johansson <olof@lixom.net>
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commit
79870b7bca
@ -338,6 +338,17 @@ choice
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The uncompressor code port configuration is now handled
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by CONFIG_S3C_LOWLEVEL_UART_PORT.
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config DEBUG_S3C_UART3
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depends on PLAT_SAMSUNG && ARCH_EXYNOS
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bool "Use S3C UART 3 for low-level debug"
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help
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Say Y here if you want the debug print routines to direct
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their output to UART 3. The port must have been initialised
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by the boot-loader before use.
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The uncompressor code port configuration is now handled
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by CONFIG_S3C_LOWLEVEL_UART_PORT.
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config DEBUG_SOCFPGA_UART
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depends on ARCH_SOCFPGA
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bool "Use SOCFPGA UART for low-level debug"
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@ -244,5 +244,11 @@
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reg = <0x12690000 0x1000>;
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interrupts = <0 36 0>;
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};
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mdma1: mdma@12850000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x12850000 0x1000>;
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interrupts = <0 34 0>;
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};
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};
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};
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@ -77,6 +77,7 @@ static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
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"exynos4210-spi.2", NULL),
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OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
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OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
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OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_MDMA1, "dma-pl330.2", NULL),
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{},
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};
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@ -36,8 +36,22 @@
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extern void exynos4_secondary_startup(void);
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#define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
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S5P_INFORM5 : S5P_VA_SYSRAM)
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static inline void __iomem *cpu_boot_reg_base(void)
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{
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if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
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return S5P_INFORM5;
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return S5P_VA_SYSRAM;
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}
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static inline void __iomem *cpu_boot_reg(int cpu)
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{
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void __iomem *boot_reg;
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boot_reg = cpu_boot_reg_base();
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if (soc_is_exynos4412())
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boot_reg += 4*cpu;
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return boot_reg;
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}
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/*
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* Write pen_release in a way that is guaranteed to be visible to all
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@ -84,6 +98,7 @@ static void __cpuinit exynos_secondary_init(unsigned int cpu)
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static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long timeout;
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unsigned long phys_cpu = cpu_logical_map(cpu);
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/*
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* Set synchronisation state between this boot processor
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@ -99,7 +114,7 @@ static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct
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* Note that "pen_release" is the hardware CPU ID, whereas
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* "cpu" is Linux's internal ID.
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*/
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write_pen_release(cpu_logical_map(cpu));
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write_pen_release(phys_cpu);
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if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
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__raw_writel(S5P_CORE_LOCAL_PWR_EN,
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@ -133,7 +148,7 @@ static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct
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smp_rmb();
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__raw_writel(virt_to_phys(exynos4_secondary_startup),
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CPU1_BOOT_REG);
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cpu_boot_reg(phys_cpu));
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gic_raise_softirq(cpumask_of(cpu), 0);
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if (pen_release == -1)
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@ -181,6 +196,8 @@ static void __init exynos_smp_init_cpus(void)
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static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
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{
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int i;
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if (!soc_is_exynos5250())
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scu_enable(scu_base_addr());
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@ -190,8 +207,9 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
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* until it receives a soft interrupt, and then the
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* secondary CPU branches to this address.
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*/
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__raw_writel(virt_to_phys(exynos4_secondary_startup),
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CPU1_BOOT_REG);
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for (i = 1; i < max_cpus; ++i)
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__raw_writel(virt_to_phys(exynos4_secondary_startup),
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cpu_boot_reg(cpu_logical_map(i)));
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}
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struct smp_operations exynos_smp_ops __initdata = {
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@ -507,5 +507,6 @@ config DEBUG_S3C_UART
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default "0" if DEBUG_S3C_UART0
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default "1" if DEBUG_S3C_UART1
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default "2" if DEBUG_S3C_UART2
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default "3" if DEBUG_S3C_UART3
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endif
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