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ath9k_hw: Optimize ath9k_hw_ar9287_set_board_values

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Rather than doing a series of RMWs, calculate the
value to be written to the register in question and
do a single REGWRITE. This improves bringup time.

This depends on the analog_shiftreg configuration option,
which is currently buggy. For AP mode, a delay of 100us
has to be the default. For station mode, this knob has to
be enabled on a per-case basis, though it is a little
unclear on when to enable a delay. This can be fixed later though.

Signed-off-by: Sujith <Sujith.Manoharan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Sujith 2010-06-01 15:14:06 +05:30 committed by John W. Linville
parent 16c94ac6cf
commit 79d7f4bcf8
3 changed files with 40 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/net/wireless/ath/ath9k/eeprom.c
View File

@ -24,6 +24,14 @@ static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin)); return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
} }
void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val)
{
REG_WRITE(ah, reg, val);
if (ah->config.analog_shiftreg)
udelay(100);
}
void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask, void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
u32 shift, u32 val) u32 shift, u32 val)
{ {

1
drivers/net/wireless/ath/ath9k/eeprom.h
View File

@ -679,6 +679,7 @@ struct eeprom_ops {
u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz); u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz);
}; };
void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val);
void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask, void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
u32 shift, u32 val); u32 shift, u32 val);
int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight, int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,

67
drivers/net/wireless/ath/ath9k/eeprom_9287.c
View File

@ -988,7 +988,7 @@ static void ath9k_hw_ar9287_set_board_values(struct ath_hw *ah,
struct ar9287_eeprom *eep = &ah->eeprom.map9287; struct ar9287_eeprom *eep = &ah->eeprom.map9287;
struct modal_eep_ar9287_header *pModal = &eep->modalHeader; struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
u16 antWrites[AR9287_ANT_16S]; u16 antWrites[AR9287_ANT_16S];
u32 regChainOffset; u32 regChainOffset, regval;
u8 txRxAttenLocal; u8 txRxAttenLocal;
int i, j, offset_num; int i, j, offset_num;
@ -1075,42 +1075,37 @@ static void ath9k_hw_ar9287_set_board_values(struct ath_hw *ah,
REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
AR_PHY_EXT_CCA0_THRESH62, pModal->thresh62); AR_PHY_EXT_CCA0_THRESH62, pModal->thresh62);
ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH0, AR9287_AN_RF2G3_DB1, regval = REG_READ(ah, AR9287_AN_RF2G3_CH0);
AR9287_AN_RF2G3_DB1_S, pModal->db1); regval &= ~(AR9287_AN_RF2G3_DB1 |
ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH0, AR9287_AN_RF2G3_DB2, AR9287_AN_RF2G3_DB2 |
AR9287_AN_RF2G3_DB2_S, pModal->db2); AR9287_AN_RF2G3_OB_CCK |
ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH0, AR9287_AN_RF2G3_OB_PSK |
AR9287_AN_RF2G3_OB_CCK, AR9287_AN_RF2G3_OB_QAM |
AR9287_AN_RF2G3_OB_CCK_S, pModal->ob_cck); AR9287_AN_RF2G3_OB_PAL_OFF);
ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH0, regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) |
AR9287_AN_RF2G3_OB_PSK, SM(pModal->db2, AR9287_AN_RF2G3_DB2) |
AR9287_AN_RF2G3_OB_PSK_S, pModal->ob_psk); SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) |
ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH0, SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) |
AR9287_AN_RF2G3_OB_QAM, SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) |
AR9287_AN_RF2G3_OB_QAM_S, pModal->ob_qam); SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF));
ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH0,
AR9287_AN_RF2G3_OB_PAL_OFF,
AR9287_AN_RF2G3_OB_PAL_OFF_S,
pModal->ob_pal_off);
ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH1, ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH0, regval);
AR9287_AN_RF2G3_DB1, AR9287_AN_RF2G3_DB1_S,
pModal->db1); regval = REG_READ(ah, AR9287_AN_RF2G3_CH1);
ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH1, AR9287_AN_RF2G3_DB2, regval &= ~(AR9287_AN_RF2G3_DB1 |
AR9287_AN_RF2G3_DB2_S, pModal->db2); AR9287_AN_RF2G3_DB2 |
ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH1, AR9287_AN_RF2G3_OB_CCK |
AR9287_AN_RF2G3_OB_CCK, AR9287_AN_RF2G3_OB_PSK |
AR9287_AN_RF2G3_OB_CCK_S, pModal->ob_cck); AR9287_AN_RF2G3_OB_QAM |
ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH1, AR9287_AN_RF2G3_OB_PAL_OFF);
AR9287_AN_RF2G3_OB_PSK, regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) |
AR9287_AN_RF2G3_OB_PSK_S, pModal->ob_psk); SM(pModal->db2, AR9287_AN_RF2G3_DB2) |
ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH1, SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) |
AR9287_AN_RF2G3_OB_QAM, SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) |
AR9287_AN_RF2G3_OB_QAM_S, pModal->ob_qam); SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) |
ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH1, SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF));
AR9287_AN_RF2G3_OB_PAL_OFF,
AR9287_AN_RF2G3_OB_PAL_OFF_S, ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH1, regval);
pModal->ob_pal_off);
REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
AR_PHY_TX_END_DATA_START, pModal->txFrameToDataStart); AR_PHY_TX_END_DATA_START, pModal->txFrameToDataStart);