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powerpc/perf: Export memory hierarchy info to user space
The LDST field and DATA_SRC in SIER identifies the memory hierarchy level (eg: L1, L2 etc), from which a data-cache miss for a marked instruction was satisfied. Use the 'perf_mem_data_src' object to export this hierarchy level to user space. Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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@ -38,6 +38,8 @@ struct power_pmu {
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unsigned long *valp);
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int (*get_alternatives)(u64 event_id, unsigned int flags,
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u64 alt[]);
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void (*get_mem_data_src)(union perf_mem_data_src *dsrc,
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u32 flags, struct pt_regs *regs);
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u64 (*bhrb_filter_map)(u64 branch_sample_type);
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void (*config_bhrb)(u64 pmu_bhrb_filter);
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void (*disable_pmc)(unsigned int pmc, unsigned long mmcr[]);
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@ -2049,6 +2049,10 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
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data.br_stack = &cpuhw->bhrb_stack;
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}
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if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC &&
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ppmu->get_mem_data_src)
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ppmu->get_mem_data_src(&data.data_src, ppmu->flags, regs);
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if (perf_event_overflow(event, &data, regs))
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power_pmu_stop(event, 0);
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}
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@ -148,6 +148,80 @@ static bool is_thresh_cmp_valid(u64 event)
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return true;
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}
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static inline u64 isa207_find_source(u64 idx, u32 sub_idx)
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{
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u64 ret = PERF_MEM_NA;
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switch(idx) {
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case 0:
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/* Nothing to do */
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break;
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case 1:
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ret = PH(LVL, L1);
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break;
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case 2:
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ret = PH(LVL, L2);
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break;
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case 3:
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ret = PH(LVL, L3);
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break;
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case 4:
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if (sub_idx <= 1)
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ret = PH(LVL, LOC_RAM);
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else if (sub_idx > 1 && sub_idx <= 2)
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ret = PH(LVL, REM_RAM1);
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else
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ret = PH(LVL, REM_RAM2);
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ret |= P(SNOOP, HIT);
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break;
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case 5:
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ret = PH(LVL, REM_CCE1);
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if ((sub_idx == 0) || (sub_idx == 2) || (sub_idx == 4))
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ret |= P(SNOOP, HIT);
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else if ((sub_idx == 1) || (sub_idx == 3) || (sub_idx == 5))
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ret |= P(SNOOP, HITM);
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break;
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case 6:
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ret = PH(LVL, REM_CCE2);
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if ((sub_idx == 0) || (sub_idx == 2))
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ret |= P(SNOOP, HIT);
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else if ((sub_idx == 1) || (sub_idx == 3))
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ret |= P(SNOOP, HITM);
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break;
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case 7:
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ret = PM(LVL, L1);
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break;
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}
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return ret;
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}
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void isa207_get_mem_data_src(union perf_mem_data_src *dsrc, u32 flags,
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struct pt_regs *regs)
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{
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u64 idx;
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u32 sub_idx;
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u64 sier;
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u64 val;
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/* Skip if no SIER support */
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if (!(flags & PPMU_HAS_SIER)) {
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dsrc->val = 0;
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return;
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}
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sier = mfspr(SPRN_SIER);
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val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT;
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if (val == 1 || val == 2) {
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idx = (sier & ISA207_SIER_LDST_MASK) >> ISA207_SIER_LDST_SHIFT;
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sub_idx = (sier & ISA207_SIER_DATA_SRC_MASK) >> ISA207_SIER_DATA_SRC_SHIFT;
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dsrc->val = isa207_find_source(idx, sub_idx);
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dsrc->val |= (val == 1) ? P(OP, LOAD) : P(OP, STORE);
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}
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}
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int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp)
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{
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unsigned int unit, pmc, cache, ebb;
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@ -260,6 +260,19 @@
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#define MAX_ALT 2
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#define MAX_PMU_COUNTERS 6
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#define ISA207_SIER_TYPE_SHIFT 15
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#define ISA207_SIER_TYPE_MASK (0x7ull << ISA207_SIER_TYPE_SHIFT)
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#define ISA207_SIER_LDST_SHIFT 1
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#define ISA207_SIER_LDST_MASK (0x7ull << ISA207_SIER_LDST_SHIFT)
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#define ISA207_SIER_DATA_SRC_SHIFT 53
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#define ISA207_SIER_DATA_SRC_MASK (0x7ull << ISA207_SIER_DATA_SRC_SHIFT)
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#define P(a, b) PERF_MEM_S(a, b)
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#define PH(a, b) (P(LVL, HIT) | P(a, b))
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#define PM(a, b) (P(LVL, MISS) | P(a, b))
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int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp);
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int isa207_compute_mmcr(u64 event[], int n_ev,
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unsigned int hwc[], unsigned long mmcr[],
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@ -267,6 +280,7 @@ int isa207_compute_mmcr(u64 event[], int n_ev,
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void isa207_disable_pmc(unsigned int pmc, unsigned long mmcr[]);
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int isa207_get_alternatives(u64 event, u64 alt[],
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const unsigned int ev_alt[][MAX_ALT], int size);
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void isa207_get_mem_data_src(union perf_mem_data_src *dsrc, u32 flags,
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struct pt_regs *regs);
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#endif
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