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dt-bindings: pinctrl: Add RZ/A1 bindings doc
Add device tree bindings documentation for Renesas RZ/A1 gpio and pin controller. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Jacopo Mondi
Geert Uytterhoeven
parent
5a49b644b3
commit
7bb3e8b106
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Renesas RZ/A1 combined Pin and GPIO controller
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The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO controller,
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named "Ports" in the hardware reference manual.
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Pin multiplexing and GPIO configuration is performed on a per-pin basis
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writing configuration values to per-port register sets.
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Each "port" features up to 16 pins, each of them configurable for GPIO
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function (port mode) or in alternate function mode.
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Up to 8 different alternate function modes exist for each single pin.
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Pin controller node
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-------------------
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Required properties:
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- compatible
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this shall be "renesas,r7s72100-ports".
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- reg
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address base and length of the memory area where the pin controller
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hardware is mapped to.
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Example:
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Pin controller node for RZ/A1H SoC (r7s72100)
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pinctrl: pin-controller@fcfe3000 {
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compatible = "renesas,r7s72100-ports";
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reg = <0xfcfe3000 0x4230>;
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};
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Sub-nodes
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---------
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The child nodes of the pin controller node describe a pin multiplexing
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function or a GPIO controller alternatively.
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- Pin multiplexing sub-nodes:
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A pin multiplexing sub-node describes how to configure a set of
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(or a single) pin in some desired alternate function mode.
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A single sub-node may define several pin configurations.
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A few alternate function require special pin configuration flags to be
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supplied along with the alternate function configuration number.
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The hardware reference manual specifies when a pin function requires
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"software IO driven" mode to be specified. To do so use the generic
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properties from the <include/linux/pinctrl/pinconf_generic.h> header file
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to instruct the pin controller to perform the desired pin configuration
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operation.
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Please refer to pinctrl-bindings.txt to get to know more on generic
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pin properties usage.
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The allowed generic formats for a pin multiplexing sub-node are the
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following ones:
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node-1 {
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pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
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GENERIC_PINCONFIG;
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};
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node-2 {
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sub-node-1 {
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pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
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GENERIC_PINCONFIG;
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};
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sub-node-2 {
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pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
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GENERIC_PINCONFIG;
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};
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...
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sub-node-n {
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pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
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GENERIC_PINCONFIG;
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};
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};
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Use the second format when pins part of the same logical group need to have
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different generic pin configuration flags applied.
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Client sub-nodes shall refer to pin multiplexing sub-nodes using the phandle
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of the most external one.
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Eg.
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client-1 {
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...
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pinctrl-0 = <&node-1>;
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...
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};
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client-2 {
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...
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pinctrl-0 = <&node-2>;
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...
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};
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Required properties:
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- pinmux:
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integer array representing pin number and pin multiplexing configuration.
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When a pin has to be configured in alternate function mode, use this
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property to identify the pin by its global index, and provide its
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alternate function configuration number along with it.
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When multiple pins are required to be configured as part of the same
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alternate function they shall be specified as members of the same
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argument list of a single "pinmux" property.
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Helper macros to ease assembling the pin index from its position
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(port where it sits on and pin number) and alternate function identifier
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are provided by the pin controller header file at:
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<include/dt-bindings/pinctrl/r7s72100-pinctrl.h>
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Integers values in "pinmux" argument list are assembled as:
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((PORT * 16 + PIN) | MUX_FUNC << 16)
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Optional generic properties:
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- input-enable:
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enable input bufer for pins requiring software driven IO input
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operations.
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- output-high:
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enable output buffer for pins requiring software driven IO output
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operations. output-low can be used alternatively, as line value is
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ignored by the driver.
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The hardware reference manual specifies when a pin has to be configured to
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work in bi-directional mode and when the IO direction has to be specified
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by software. Bi-directional pins are managed by the pin controller driver
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internally, while software driven IO direction has to be explicitly
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selected when multiple options are available.
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Example:
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A serial communication interface with a TX output pin and an RX input pin.
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&pinctrl {
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scif2_pins: serial2 {
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pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>;
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};
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};
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Pin #0 on port #3 is configured as alternate function #6.
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Pin #2 on port #3 is configured as alternate function #4.
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Example 2:
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I2c master: both SDA and SCL pins need bi-directional operations
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&pinctrl {
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i2c2_pins: i2c2 {
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pinmux = <RZA1_PINMUX(1, 4, 1)>, <RZA1_PINMUX(1, 5, 1)>;
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};
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};
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Pin #4 on port #1 is configured as alternate function #1.
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Pin #5 on port #1 is configured as alternate function #1.
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Both need to work in bi-directional mode, the driver manages this internally.
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Example 3:
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Multi-function timer input and output compare pins.
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Configure TIOC0A as software driven input and TIOC0B as software driven
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output.
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&pinctrl {
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tioc0_pins: tioc0 {
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tioc0_input_pins {
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pinumx = <RZA1_PINMUX(4, 0, 2)>;
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input-enable;
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};
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tioc0_output_pins {
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pinmux = <RZA1_PINMUX(4, 1, 1)>;
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output-enable;
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};
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};
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};
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&tioc0 {
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...
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pinctrl-0 = <&tioc0_pins>;
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...
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};
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Pin #0 on port #4 is configured as alternate function #2 with IO direction
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specified by software as input.
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Pin #1 on port #4 is configured as alternate function #1 with IO direction
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specified by software as output.
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- GPIO controller sub-nodes:
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Each port of the r7s72100 pin controller hardware is itself a GPIO controller.
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Different SoCs have different numbers of available pins per port, but
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generally speaking, each of them can be configured in GPIO ("port") mode
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on this hardware.
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Describe GPIO controllers using sub-nodes with the following properties.
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Required properties:
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- gpio-controller
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empty property as defined by the GPIO bindings documentation.
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- #gpio-cells
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number of cells required to identify and configure a GPIO.
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Shall be 2.
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- gpio-ranges
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Describes a GPIO controller specifying its specific pin base, the pin
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base in the global pin numbering space, and the number of controlled
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pins, as defined by the GPIO bindings documentation. Refer to
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Documentation/devicetree/bindings/gpio/gpio.txt file for a more detailed
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description.
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Example:
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A GPIO controller node, controlling 16 pins indexed from 0.
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The GPIO controller base in the global pin indexing space is pin 48, thus
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pins [0 - 15] on this controller map to pins [48 - 63] in the global pin
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indexing space.
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port3: gpio-3 {
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 48 16>;
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};
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A device node willing to use pins controlled by this GPIO controller, shall
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refer to it as follows:
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led1 {
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gpios = <&port3 10 GPIO_ACTIVE_LOW>;
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};
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