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ARM: smp: Add initialization of CNTVOFF

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The CNTVOFF register from arch timer is uninitialized.
It should be done by the bootloader but it is currently not the case,
even for boot CPU because this SoC is booting in secure mode.
It leads to an random offset value meaning that each CPU will have a
different time, which isn't working very well.

Add assembly code used for boot CPU and secondary CPU cores to make
sure that the CNTVOFF register is initialized. Because this code can
be used by different platforms, add this assembly file in ARM's common
folder.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
This commit is contained in:
Mylène Josserand 2018-05-04 21:05:39 +02:00 committed by Maxime Ripard
parent dff052ccf3
commit 7c607944bc
3 changed files with 41 additions and 0 deletions
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1
arch/arm/common/Makefile
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@ -10,6 +10,7 @@ obj-$(CONFIG_DMABOUNCE) += dmabounce.o
obj-$(CONFIG_SHARP_LOCOMO) += locomo.o
obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o
obj-$(CONFIG_SHARP_SCOOP) += scoop.o
obj-$(CONFIG_SMP) += secure_cntvoff.o
obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o
obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o
CFLAGS_REMOVE_mcpm_entry.o = -pg

32
arch/arm/common/secure_cntvoff.S Normal file
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@ -0,0 +1,32 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2014 Renesas Electronics Corporation
*
* Initialization of CNTVOFF register from secure mode
*
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
ENTRY(secure_cntvoff_init)
.arch armv7-a
/*
* CNTVOFF has to be initialized either from non-secure Hypervisor
* mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
* then it should be handled by the secure code. The CPU must implement
* the virtualization extensions.
*/
cps #MON_MODE
mrc p15, 0, r1, c1, c1, 0 /* Get Secure Config */
orr r0, r1, #1
mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */
isb
mov r0, #0
mcrr p15, 4, r0, r0, c14 /* CNTVOFF = 0 */
isb
mcr p15, 0, r1, c1, c1, 0 /* Set Secure bit */
isb
cps #SVC_MODE
ret lr
ENDPROC(secure_cntvoff_init)

8
arch/arm/include/asm/secure_cntvoff.h Normal file
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@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASMARM_ARCH_CNTVOFF_H
#define __ASMARM_ARCH_CNTVOFF_H
extern void secure_cntvoff_init(void);
#endif