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irq_remapping/amd: Enhance AMD IR driver to support hierarchical irqdomains
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Acked-by: Joerg Roedel <jroedel@suse.de> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: David Cohen <david.a.cohen@linux.intel.com> Cc: Sander Eikelenboom <linux@eikelenboom.it> Cc: David Vrabel <david.vrabel@citrix.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: iommu@lists.linux-foundation.org Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Dimitri Sivanich <sivanich@sgi.com> Cc: Joerg Roedel <joro@8bytes.org> Link: http://lkml.kernel.org/r/1428905519-23704-12-git-send-email-jiang.liu@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Jiang Liu
Thomas Gleixner
parent
b106ee63ab
commit
7c71d306c9
@ -34,6 +34,7 @@
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#include <linux/irq.h>
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#include <linux/msi.h>
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#include <linux/dma-contiguous.h>
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#include <linux/irqdomain.h>
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#include <asm/irq_remapping.h>
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#include <asm/io_apic.h>
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#include <asm/apic.h>
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@ -3851,6 +3852,16 @@ union irte {
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} fields;
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};
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struct amd_ir_data {
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struct irq_2_irte irq_2_irte;
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union irte irte_entry;
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union {
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struct msi_msg msi_entry;
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};
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};
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static struct irq_chip amd_ir_chip;
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#define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
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#define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
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#define DTE_IRQ_TABLE_LEN (8ULL << 1)
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@ -3944,7 +3955,8 @@ out_unlock:
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return table;
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}
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static int alloc_irq_index(struct irq_cfg *cfg, u16 devid, int count)
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static int alloc_irq_index(struct irq_cfg *cfg, struct irq_2_irte *irte_info,
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u16 devid, int count)
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{
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struct irq_remap_table *table;
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unsigned long flags;
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@ -3966,15 +3978,12 @@ static int alloc_irq_index(struct irq_cfg *cfg, u16 devid, int count)
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c = 0;
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if (c == count) {
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struct irq_2_irte *irte_info;
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for (; c != 0; --c)
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table->table[index - c + 1] = IRTE_ALLOCATED;
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index -= count - 1;
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cfg->remapped = 1;
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irte_info = &cfg->irq_2_irte;
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irte_info->devid = devid;
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irte_info->index = index;
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@ -4219,7 +4228,7 @@ static int msi_alloc_irq(struct pci_dev *pdev, int irq, int nvec)
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return -EINVAL;
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devid = get_device_id(&pdev->dev);
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index = alloc_irq_index(cfg, devid, nvec);
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index = alloc_irq_index(cfg, &cfg->irq_2_irte, devid, nvec);
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return index < 0 ? MAX_IRQS_PER_TABLE : index;
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}
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@ -4266,7 +4275,7 @@ static int alloc_hpet_msi(unsigned int irq, unsigned int id)
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if (devid < 0)
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return devid;
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index = alloc_irq_index(cfg, devid, 1);
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index = alloc_irq_index(cfg, &cfg->irq_2_irte, devid, 1);
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if (index < 0)
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return index;
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@ -4277,6 +4286,72 @@ static int alloc_hpet_msi(unsigned int irq, unsigned int id)
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return 0;
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}
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static int get_devid(struct irq_alloc_info *info)
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{
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int devid = -1;
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switch (info->type) {
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case X86_IRQ_ALLOC_TYPE_IOAPIC:
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devid = get_ioapic_devid(info->ioapic_id);
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break;
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case X86_IRQ_ALLOC_TYPE_HPET:
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devid = get_hpet_devid(info->hpet_id);
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break;
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case X86_IRQ_ALLOC_TYPE_MSI:
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case X86_IRQ_ALLOC_TYPE_MSIX:
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devid = get_device_id(&info->msi_dev->dev);
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break;
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default:
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BUG_ON(1);
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break;
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}
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return devid;
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}
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static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
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{
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struct amd_iommu *iommu;
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int devid;
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if (!info)
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return NULL;
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devid = get_devid(info);
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if (devid >= 0) {
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iommu = amd_iommu_rlookup_table[devid];
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if (iommu)
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return iommu->ir_domain;
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}
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return NULL;
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}
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static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
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{
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struct amd_iommu *iommu;
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int devid;
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if (!info)
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return NULL;
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switch (info->type) {
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case X86_IRQ_ALLOC_TYPE_MSI:
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case X86_IRQ_ALLOC_TYPE_MSIX:
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devid = get_device_id(&info->msi_dev->dev);
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if (devid >= 0) {
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iommu = amd_iommu_rlookup_table[devid];
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if (iommu)
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return iommu->msi_domain;
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}
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break;
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default:
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break;
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}
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return NULL;
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}
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struct irq_remap_ops amd_iommu_irq_ops = {
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.prepare = amd_iommu_prepare,
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.enable = amd_iommu_enable,
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@ -4290,5 +4365,247 @@ struct irq_remap_ops amd_iommu_irq_ops = {
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.msi_alloc_irq = msi_alloc_irq,
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.msi_setup_irq = msi_setup_irq,
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.alloc_hpet_msi = alloc_hpet_msi,
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.get_ir_irq_domain = get_ir_irq_domain,
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.get_irq_domain = get_irq_domain,
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};
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static void irq_remapping_prepare_irte(struct amd_ir_data *data,
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struct irq_cfg *irq_cfg,
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struct irq_alloc_info *info,
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int devid, int index, int sub_handle)
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{
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struct irq_2_irte *irte_info = &data->irq_2_irte;
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struct msi_msg *msg = &data->msi_entry;
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union irte *irte = &data->irte_entry;
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struct IO_APIC_route_entry *entry;
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irq_cfg->remapped = 1;
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data->irq_2_irte.devid = devid;
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data->irq_2_irte.index = index + sub_handle;
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/* Setup IRTE for IOMMU */
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irte->val = 0;
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irte->fields.vector = irq_cfg->vector;
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irte->fields.int_type = apic->irq_delivery_mode;
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irte->fields.destination = irq_cfg->dest_apicid;
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irte->fields.dm = apic->irq_dest_mode;
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irte->fields.valid = 1;
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switch (info->type) {
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case X86_IRQ_ALLOC_TYPE_IOAPIC:
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/* Setup IOAPIC entry */
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entry = info->ioapic_entry;
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info->ioapic_entry = NULL;
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memset(entry, 0, sizeof(*entry));
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entry->vector = index;
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entry->mask = 0;
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entry->trigger = info->ioapic_trigger;
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entry->polarity = info->ioapic_polarity;
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/* Mask level triggered irqs. */
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if (info->ioapic_trigger)
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entry->mask = 1;
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break;
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case X86_IRQ_ALLOC_TYPE_HPET:
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case X86_IRQ_ALLOC_TYPE_MSI:
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case X86_IRQ_ALLOC_TYPE_MSIX:
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msg->address_hi = MSI_ADDR_BASE_HI;
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msg->address_lo = MSI_ADDR_BASE_LO;
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msg->data = irte_info->index;
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break;
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default:
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BUG_ON(1);
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break;
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}
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}
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static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *arg)
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{
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struct irq_alloc_info *info = arg;
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struct irq_data *irq_data;
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struct amd_ir_data *data;
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struct irq_cfg *cfg;
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int i, ret, devid;
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int index = -1;
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if (!info)
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return -EINVAL;
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if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
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info->type != X86_IRQ_ALLOC_TYPE_MSIX)
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return -EINVAL;
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/*
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* With IRQ remapping enabled, don't need contiguous CPU vectors
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* to support multiple MSI interrupts.
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*/
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if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
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info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
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devid = get_devid(info);
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if (devid < 0)
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return -EINVAL;
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ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
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if (ret < 0)
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return ret;
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ret = -ENOMEM;
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data = kzalloc(sizeof(*data), GFP_KERNEL);
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if (!data)
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goto out_free_parent;
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if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
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if (get_irq_table(devid, true))
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index = info->ioapic_pin;
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else
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ret = -ENOMEM;
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} else {
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cfg = irq_cfg(virq);
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index = alloc_irq_index(cfg, &data->irq_2_irte, devid, nr_irqs);
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}
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if (index < 0) {
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pr_warn("Failed to allocate IRTE\n");
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kfree(data);
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goto out_free_parent;
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}
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for (i = 0; i < nr_irqs; i++) {
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irq_data = irq_domain_get_irq_data(domain, virq + i);
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cfg = irqd_cfg(irq_data);
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if (!irq_data || !cfg) {
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ret = -EINVAL;
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goto out_free_data;
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}
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if (i > 0) {
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data = kzalloc(sizeof(*data), GFP_KERNEL);
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if (!data)
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goto out_free_data;
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}
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irq_data->hwirq = (devid << 16) + i;
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irq_data->chip_data = data;
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irq_data->chip = &amd_ir_chip;
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irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
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irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
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}
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return 0;
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out_free_data:
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for (i--; i >= 0; i--) {
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irq_data = irq_domain_get_irq_data(domain, virq + i);
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if (irq_data)
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kfree(irq_data->chip_data);
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}
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for (i = 0; i < nr_irqs; i++)
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free_irte(devid, index + i);
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out_free_parent:
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irq_domain_free_irqs_common(domain, virq, nr_irqs);
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return ret;
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}
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static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs)
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{
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struct irq_2_irte *irte_info;
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struct irq_data *irq_data;
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struct amd_ir_data *data;
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int i;
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for (i = 0; i < nr_irqs; i++) {
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irq_data = irq_domain_get_irq_data(domain, virq + i);
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if (irq_data && irq_data->chip_data) {
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data = irq_data->chip_data;
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irte_info = &data->irq_2_irte;
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free_irte(irte_info->devid, irte_info->index);
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kfree(data);
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}
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}
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irq_domain_free_irqs_common(domain, virq, nr_irqs);
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}
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static void irq_remapping_activate(struct irq_domain *domain,
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struct irq_data *irq_data)
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{
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struct amd_ir_data *data = irq_data->chip_data;
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struct irq_2_irte *irte_info = &data->irq_2_irte;
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modify_irte(irte_info->devid, irte_info->index, data->irte_entry);
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}
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static void irq_remapping_deactivate(struct irq_domain *domain,
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struct irq_data *irq_data)
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{
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struct amd_ir_data *data = irq_data->chip_data;
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struct irq_2_irte *irte_info = &data->irq_2_irte;
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union irte entry;
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entry.val = 0;
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modify_irte(irte_info->devid, irte_info->index, data->irte_entry);
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}
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static struct irq_domain_ops amd_ir_domain_ops = {
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.alloc = irq_remapping_alloc,
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.free = irq_remapping_free,
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.activate = irq_remapping_activate,
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.deactivate = irq_remapping_deactivate,
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};
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static int amd_ir_set_affinity(struct irq_data *data,
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const struct cpumask *mask, bool force)
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{
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struct amd_ir_data *ir_data = data->chip_data;
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struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
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struct irq_cfg *cfg = irqd_cfg(data);
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struct irq_data *parent = data->parent_data;
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int ret;
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ret = parent->chip->irq_set_affinity(parent, mask, force);
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if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
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return ret;
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/*
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* Atomically updates the IRTE with the new destination, vector
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* and flushes the interrupt entry cache.
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*/
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ir_data->irte_entry.fields.vector = cfg->vector;
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ir_data->irte_entry.fields.destination = cfg->dest_apicid;
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modify_irte(irte_info->devid, irte_info->index, ir_data->irte_entry);
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/*
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* After this point, all the interrupts will start arriving
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* at the new destination. So, time to cleanup the previous
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* vector allocation.
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*/
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if (cfg->move_in_progress)
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send_cleanup_vector(cfg);
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return IRQ_SET_MASK_OK_DONE;
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}
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static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
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{
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struct amd_ir_data *ir_data = irq_data->chip_data;
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*msg = ir_data->msi_entry;
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}
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static struct irq_chip amd_ir_chip = {
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.irq_ack = ir_ack_apic_edge,
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.irq_set_affinity = amd_ir_set_affinity,
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.irq_compose_msi_msg = ir_compose_msi_msg,
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};
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int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
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{
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iommu->ir_domain = irq_domain_add_tree(NULL, &amd_ir_domain_ops, iommu);
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if (!iommu->ir_domain)
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return -ENOMEM;
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iommu->ir_domain->parent = arch_get_ir_parent_domain();
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iommu->msi_domain = arch_create_msi_irq_domain(iommu->ir_domain);
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return 0;
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}
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#endif
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@ -1124,6 +1124,10 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
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if (ret)
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return ret;
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ret = amd_iommu_create_irq_domain(iommu);
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if (ret)
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return ret;
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/*
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* Make sure IOMMU is not considered to translate itself. The IVRS
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* table tells us so, but this is a lie!
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@ -62,6 +62,15 @@ extern u8 amd_iommu_pc_get_max_counters(u16 devid);
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extern int amd_iommu_pc_get_set_reg_val(u16 devid, u8 bank, u8 cntr, u8 fxn,
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u64 *value, bool is_write);
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#ifdef CONFIG_IRQ_REMAP
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extern int amd_iommu_create_irq_domain(struct amd_iommu *iommu);
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#else
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static inline int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
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{
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return 0;
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}
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#endif
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#define PPR_SUCCESS 0x0
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#define PPR_INVALID 0x1
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#define PPR_FAILURE 0xf
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@ -398,6 +398,7 @@ struct amd_iommu_fault {
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struct iommu_domain;
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struct irq_domain;
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/*
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* This structure contains generic data for IOMMU protection domains
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@ -579,6 +580,10 @@ struct amd_iommu {
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/* The maximum PC banks and counters/bank (PCSup=1) */
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u8 max_banks;
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u8 max_counters;
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#ifdef CONFIG_IRQ_REMAP
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struct irq_domain *ir_domain;
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struct irq_domain *msi_domain;
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#endif
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};
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|
||||
struct devid_map {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user