FEX-Emu/linux
1
0
Fork 0
mirror of https://github.com/FEX-Emu/linux.git synced 2025-01-16 14:38:49 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

ARM: dts: am43xx-clocks: Fix ehrpwm tbclk data on am43xx

Browse Source 
ehrpwm tbclk is wrongly modelled as deriving from dpll_per_m2_ck.
The TRM says tbclk is derived from SYSCLKOUT. SYSCLKOUT nothing but the
functional clock of pwmss (l4ls_gclk).
Fix this by changing source of ehrpwmx_tbclk to l4ls_gclk.

Fixes: 4da1c67719f61 ("add tbclk data for ehrpwm")
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Vignesh R 2015-02-10 11:05:42 +05:30 committed by Tony Lindgren
parent 6e22616eba
commit 7d53d25578
1 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
arch/arm/boot/dts/am43xx-clocks.dtsi
View File

@ -107,7 +107,7 @@
ehrpwm0_tbclk: ehrpwm0_tbclk { ehrpwm0_tbclk: ehrpwm0_tbclk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,gate-clock"; compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>; clocks = <&l4ls_gclk>;
ti,bit-shift = <0>; ti,bit-shift = <0>;
reg = <0x0664>; reg = <0x0664>;
}; };
@ -115,7 +115,7 @@
ehrpwm1_tbclk: ehrpwm1_tbclk { ehrpwm1_tbclk: ehrpwm1_tbclk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,gate-clock"; compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>; clocks = <&l4ls_gclk>;
ti,bit-shift = <1>; ti,bit-shift = <1>;
reg = <0x0664>; reg = <0x0664>;
}; };
@ -123,7 +123,7 @@
ehrpwm2_tbclk: ehrpwm2_tbclk { ehrpwm2_tbclk: ehrpwm2_tbclk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,gate-clock"; compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>; clocks = <&l4ls_gclk>;
ti,bit-shift = <2>; ti,bit-shift = <2>;
reg = <0x0664>; reg = <0x0664>;
}; };
@ -131,7 +131,7 @@
ehrpwm3_tbclk: ehrpwm3_tbclk { ehrpwm3_tbclk: ehrpwm3_tbclk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,gate-clock"; compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>; clocks = <&l4ls_gclk>;
ti,bit-shift = <4>; ti,bit-shift = <4>;
reg = <0x0664>; reg = <0x0664>;
}; };
@ -139,7 +139,7 @@
ehrpwm4_tbclk: ehrpwm4_tbclk { ehrpwm4_tbclk: ehrpwm4_tbclk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,gate-clock"; compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>; clocks = <&l4ls_gclk>;
ti,bit-shift = <5>; ti,bit-shift = <5>;
reg = <0x0664>; reg = <0x0664>;
}; };
@ -147,7 +147,7 @@
ehrpwm5_tbclk: ehrpwm5_tbclk { ehrpwm5_tbclk: ehrpwm5_tbclk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,gate-clock"; compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>; clocks = <&l4ls_gclk>;
ti,bit-shift = <6>; ti,bit-shift = <6>;
reg = <0x0664>; reg = <0x0664>;
}; };