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drm/vmwgfx: Add and make use of a header for surface size calculation.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: Brian Paul <brianp@vmware.com> Reviewed-by: Dmitry Torokhov <dtor@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Thomas Hellstrom
Dave Airlie
parent
543831cfc9
commit
7e8d9da32e
909
drivers/gpu/drm/vmwgfx/svga3d_surfacedefs.h
Normal file
909
drivers/gpu/drm/vmwgfx/svga3d_surfacedefs.h
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/**************************************************************************
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*
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* Copyright © 2008-2012 VMware, Inc., Palo Alto, CA., USA
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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**************************************************************************/
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#ifdef __KERNEL__
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#include <drm/vmwgfx_drm.h>
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#define surf_size_struct struct drm_vmw_size
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#else /* __KERNEL__ */
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#ifndef ARRAY_SIZE
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#define ARRAY_SIZE(_A) (sizeof(_A) / sizeof((_A)[0]))
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#endif /* ARRAY_SIZE */
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#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y))
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#define max_t(type, x, y) ((x) > (y) ? (x) : (y))
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#define surf_size_struct SVGA3dSize
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#define u32 uint32
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#endif /* __KERNEL__ */
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#include "svga3d_reg.h"
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/*
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* enum svga3d_block_desc describes the active data channels in a block.
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*
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* There can be at-most four active channels in a block:
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* 1. Red, bump W, luminance and depth are stored in the first channel.
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* 2. Green, bump V and stencil are stored in the second channel.
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* 3. Blue and bump U are stored in the third channel.
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* 4. Alpha and bump Q are stored in the fourth channel.
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*
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* Block channels can be used to store compressed and buffer data:
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* 1. For compressed formats, only the data channel is used and its size
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* is equal to that of a singular block in the compression scheme.
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* 2. For buffer formats, only the data channel is used and its size is
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* exactly one byte in length.
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* 3. In each case the bit depth represent the size of a singular block.
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*
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* Note: Compressed and IEEE formats do not use the bitMask structure.
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*/
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enum svga3d_block_desc {
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SVGA3DBLOCKDESC_NONE = 0, /* No channels are active */
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SVGA3DBLOCKDESC_BLUE = 1 << 0, /* Block with red channel
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data */
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SVGA3DBLOCKDESC_U = 1 << 0, /* Block with bump U channel
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data */
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SVGA3DBLOCKDESC_UV_VIDEO = 1 << 7, /* Block with alternating video
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U and V */
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SVGA3DBLOCKDESC_GREEN = 1 << 1, /* Block with green channel
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data */
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SVGA3DBLOCKDESC_V = 1 << 1, /* Block with bump V channel
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data */
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SVGA3DBLOCKDESC_STENCIL = 1 << 1, /* Block with a stencil
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channel */
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SVGA3DBLOCKDESC_RED = 1 << 2, /* Block with blue channel
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data */
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SVGA3DBLOCKDESC_W = 1 << 2, /* Block with bump W channel
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data */
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SVGA3DBLOCKDESC_LUMINANCE = 1 << 2, /* Block with luminance channel
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data */
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SVGA3DBLOCKDESC_Y = 1 << 2, /* Block with video luminance
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data */
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SVGA3DBLOCKDESC_DEPTH = 1 << 2, /* Block with depth channel */
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SVGA3DBLOCKDESC_ALPHA = 1 << 3, /* Block with an alpha
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channel */
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SVGA3DBLOCKDESC_Q = 1 << 3, /* Block with bump Q channel
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data */
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SVGA3DBLOCKDESC_BUFFER = 1 << 4, /* Block stores 1 byte of
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data */
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SVGA3DBLOCKDESC_COMPRESSED = 1 << 5, /* Block stores n bytes of
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data depending on the
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compression method used */
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SVGA3DBLOCKDESC_IEEE_FP = 1 << 6, /* Block stores data in an IEEE
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floating point
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representation in
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all channels */
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SVGA3DBLOCKDESC_PLANAR_YUV = 1 << 8, /* Three separate blocks store
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data. */
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SVGA3DBLOCKDESC_U_VIDEO = 1 << 9, /* Block with U video data */
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SVGA3DBLOCKDESC_V_VIDEO = 1 << 10, /* Block with V video data */
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SVGA3DBLOCKDESC_EXP = 1 << 11, /* Shared exponent */
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SVGA3DBLOCKDESC_SRGB = 1 << 12, /* Data is in sRGB format */
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SVGA3DBLOCKDESC_2PLANAR_YUV = 1 << 13, /* 2 planes of Y, UV,
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e.g., NV12. */
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SVGA3DBLOCKDESC_3PLANAR_YUV = 1 << 14, /* 3 planes of separate
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Y, U, V, e.g., YV12. */
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SVGA3DBLOCKDESC_RG = SVGA3DBLOCKDESC_RED |
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SVGA3DBLOCKDESC_GREEN,
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SVGA3DBLOCKDESC_RGB = SVGA3DBLOCKDESC_RG |
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SVGA3DBLOCKDESC_BLUE,
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SVGA3DBLOCKDESC_RGB_SRGB = SVGA3DBLOCKDESC_RGB |
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SVGA3DBLOCKDESC_SRGB,
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SVGA3DBLOCKDESC_RGBA = SVGA3DBLOCKDESC_RGB |
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SVGA3DBLOCKDESC_ALPHA,
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SVGA3DBLOCKDESC_RGBA_SRGB = SVGA3DBLOCKDESC_RGBA |
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SVGA3DBLOCKDESC_SRGB,
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SVGA3DBLOCKDESC_UV = SVGA3DBLOCKDESC_U |
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SVGA3DBLOCKDESC_V,
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SVGA3DBLOCKDESC_UVL = SVGA3DBLOCKDESC_UV |
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SVGA3DBLOCKDESC_LUMINANCE,
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SVGA3DBLOCKDESC_UVW = SVGA3DBLOCKDESC_UV |
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SVGA3DBLOCKDESC_W,
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SVGA3DBLOCKDESC_UVWA = SVGA3DBLOCKDESC_UVW |
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SVGA3DBLOCKDESC_ALPHA,
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SVGA3DBLOCKDESC_UVWQ = SVGA3DBLOCKDESC_U |
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SVGA3DBLOCKDESC_V |
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SVGA3DBLOCKDESC_W |
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SVGA3DBLOCKDESC_Q,
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SVGA3DBLOCKDESC_LA = SVGA3DBLOCKDESC_LUMINANCE |
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SVGA3DBLOCKDESC_ALPHA,
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SVGA3DBLOCKDESC_R_FP = SVGA3DBLOCKDESC_RED |
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SVGA3DBLOCKDESC_IEEE_FP,
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SVGA3DBLOCKDESC_RG_FP = SVGA3DBLOCKDESC_R_FP |
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SVGA3DBLOCKDESC_GREEN,
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SVGA3DBLOCKDESC_RGB_FP = SVGA3DBLOCKDESC_RG_FP |
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SVGA3DBLOCKDESC_BLUE,
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SVGA3DBLOCKDESC_RGBA_FP = SVGA3DBLOCKDESC_RGB_FP |
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SVGA3DBLOCKDESC_ALPHA,
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SVGA3DBLOCKDESC_DS = SVGA3DBLOCKDESC_DEPTH |
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SVGA3DBLOCKDESC_STENCIL,
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SVGA3DBLOCKDESC_YUV = SVGA3DBLOCKDESC_UV_VIDEO |
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SVGA3DBLOCKDESC_Y,
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SVGA3DBLOCKDESC_AYUV = SVGA3DBLOCKDESC_ALPHA |
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SVGA3DBLOCKDESC_Y |
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SVGA3DBLOCKDESC_U_VIDEO |
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SVGA3DBLOCKDESC_V_VIDEO,
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SVGA3DBLOCKDESC_RGBE = SVGA3DBLOCKDESC_RGB |
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SVGA3DBLOCKDESC_EXP,
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SVGA3DBLOCKDESC_COMPRESSED_SRGB = SVGA3DBLOCKDESC_COMPRESSED |
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SVGA3DBLOCKDESC_SRGB,
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SVGA3DBLOCKDESC_NV12 = SVGA3DBLOCKDESC_PLANAR_YUV |
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SVGA3DBLOCKDESC_2PLANAR_YUV,
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SVGA3DBLOCKDESC_YV12 = SVGA3DBLOCKDESC_PLANAR_YUV |
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SVGA3DBLOCKDESC_3PLANAR_YUV,
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};
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/*
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* SVGA3dSurfaceDesc describes the actual pixel data.
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*
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* This structure provides the following information:
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* 1. Block description.
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* 2. Dimensions of a block in the surface.
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* 3. Size of block in bytes.
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* 4. Bit depth of the pixel data.
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* 5. Channel bit depths and masks (if applicable).
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*/
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#define SVGA3D_CHANNEL_DEF(type) \
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struct { \
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union { \
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type blue; \
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type u; \
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type uv_video; \
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type u_video; \
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}; \
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union { \
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type green; \
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type v; \
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type stencil; \
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type v_video; \
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}; \
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union { \
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type red; \
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type w; \
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type luminance; \
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type y; \
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type depth; \
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type data; \
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}; \
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union { \
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type alpha; \
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type q; \
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type exp; \
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}; \
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}
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struct svga3d_surface_desc {
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enum svga3d_block_desc block_desc;
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surf_size_struct block_size;
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u32 bytes_per_block;
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u32 pitch_bytes_per_block;
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struct {
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u32 total;
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SVGA3D_CHANNEL_DEF(uint8);
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} bit_depth;
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struct {
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SVGA3D_CHANNEL_DEF(uint8);
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} bit_offset;
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};
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static const struct svga3d_surface_desc svga3d_surface_descs[] = {
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{SVGA3DBLOCKDESC_NONE,
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{1, 1, 1}, 0, 0, {0, {{0}, {0}, {0}, {0} } },
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{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_FORMAT_INVALID */
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{SVGA3DBLOCKDESC_RGB,
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{1, 1, 1}, 4, 4, {24, {{8}, {8}, {8}, {0} } },
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{{{0}, {8}, {16}, {24} } } }, /* SVGA3D_X8R8G8B8 */
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{SVGA3DBLOCKDESC_RGBA,
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{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
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{{{0}, {8}, {16}, {24} } } }, /* SVGA3D_A8R8G8B8 */
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{SVGA3DBLOCKDESC_RGB,
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{1, 1, 1}, 2, 2, {16, {{5}, {6}, {5}, {0} } },
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{{{0}, {5}, {11}, {0} } } }, /* SVGA3D_R5G6B5 */
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{SVGA3DBLOCKDESC_RGB,
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{1, 1, 1}, 2, 2, {15, {{5}, {5}, {5}, {0} } },
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{{{0}, {5}, {10}, {0} } } }, /* SVGA3D_X1R5G5B5 */
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{SVGA3DBLOCKDESC_RGBA,
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{1, 1, 1}, 2, 2, {16, {{5}, {5}, {5}, {1} } },
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{{{0}, {5}, {10}, {15} } } }, /* SVGA3D_A1R5G5B5 */
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{SVGA3DBLOCKDESC_RGBA,
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{1, 1, 1}, 2, 2, {16, {{4}, {4}, {4}, {4} } },
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{{{0}, {4}, {8}, {12} } } }, /* SVGA3D_A4R4G4B4 */
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{SVGA3DBLOCKDESC_DEPTH,
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{1, 1, 1}, 4, 4, {32, {{0}, {0}, {32}, {0} } },
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{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_Z_D32 */
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{SVGA3DBLOCKDESC_DEPTH,
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{1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
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{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_Z_D16 */
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{SVGA3DBLOCKDESC_DS,
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{1, 1, 1}, 4, 4, {32, {{0}, {8}, {24}, {0} } },
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{{{0}, {24}, {0}, {0} } } }, /* SVGA3D_Z_D24S8 */
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{SVGA3DBLOCKDESC_DS,
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{1, 1, 1}, 2, 2, {16, {{0}, {1}, {15}, {0} } },
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{{{0}, {15}, {0}, {0} } } }, /* SVGA3D_Z_D15S1 */
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{SVGA3DBLOCKDESC_LUMINANCE,
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{1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
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{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_LUMINANCE8 */
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{SVGA3DBLOCKDESC_LA,
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{1, 1, 1}, 1, 1, {8, {{0}, {0}, {4}, {4} } },
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{{{0}, {0}, {0}, {4} } } }, /* SVGA3D_LUMINANCE4_ALPHA4 */
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{SVGA3DBLOCKDESC_LUMINANCE,
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{1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
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{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_LUMINANCE16 */
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{SVGA3DBLOCKDESC_LA,
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{1, 1, 1}, 2, 2, {16, {{0}, {0}, {8}, {8} } },
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{{{0}, {0}, {0}, {8} } } }, /* SVGA3D_LUMINANCE8_ALPHA8 */
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{SVGA3DBLOCKDESC_COMPRESSED,
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{4, 4, 1}, 8, 8, {64, {{0}, {0}, {64}, {0} } },
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{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_DXT1 */
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{SVGA3DBLOCKDESC_COMPRESSED,
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{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
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{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_DXT2 */
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{SVGA3DBLOCKDESC_COMPRESSED,
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{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
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{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_DXT3 */
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{SVGA3DBLOCKDESC_COMPRESSED,
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{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
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{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_DXT4 */
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{SVGA3DBLOCKDESC_COMPRESSED,
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{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
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{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_DXT5 */
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{SVGA3DBLOCKDESC_UV,
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{1, 1, 1}, 2, 2, {16, {{0}, {0}, {8}, {8} } },
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{{{0}, {0}, {0}, {8} } } }, /* SVGA3D_BUMPU8V8 */
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{SVGA3DBLOCKDESC_UVL,
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{1, 1, 1}, 2, 2, {16, {{5}, {5}, {6}, {0} } },
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{{{11}, {6}, {0}, {0} } } }, /* SVGA3D_BUMPL6V5U5 */
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{SVGA3DBLOCKDESC_UVL,
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{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {0} } },
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{{{16}, {8}, {0}, {0} } } }, /* SVGA3D_BUMPX8L8V8U8 */
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{SVGA3DBLOCKDESC_UVL,
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{1, 1, 1}, 3, 3, {24, {{8}, {8}, {8}, {0} } },
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{{{16}, {8}, {0}, {0} } } }, /* SVGA3D_BUMPL8V8U8 */
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{SVGA3DBLOCKDESC_RGBA_FP,
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{1, 1, 1}, 8, 8, {64, {{16}, {16}, {16}, {16} } },
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{{{32}, {16}, {0}, {48} } } }, /* SVGA3D_ARGB_S10E5 */
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{SVGA3DBLOCKDESC_RGBA_FP,
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{1, 1, 1}, 16, 16, {128, {{32}, {32}, {32}, {32} } },
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{{{64}, {32}, {0}, {96} } } }, /* SVGA3D_ARGB_S23E8 */
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{SVGA3DBLOCKDESC_RGBA,
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{1, 1, 1}, 4, 4, {32, {{10}, {10}, {10}, {2} } },
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{{{0}, {10}, {20}, {30} } } }, /* SVGA3D_A2R10G10B10 */
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{SVGA3DBLOCKDESC_UV,
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{1, 1, 1}, 2, 2, {16, {{8}, {8}, {0}, {0} } },
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{{{8}, {0}, {0}, {0} } } }, /* SVGA3D_V8U8 */
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{SVGA3DBLOCKDESC_UVWQ,
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{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
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{{{24}, {16}, {8}, {0} } } }, /* SVGA3D_Q8W8V8U8 */
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{SVGA3DBLOCKDESC_UV,
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{1, 1, 1}, 2, 2, {16, {{8}, {8}, {0}, {0} } },
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{{{8}, {0}, {0}, {0} } } }, /* SVGA3D_CxV8U8 */
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{SVGA3DBLOCKDESC_UVL,
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{1, 1, 1}, 4, 4, {24, {{8}, {8}, {8}, {0} } },
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{{{16}, {8}, {0}, {0} } } }, /* SVGA3D_X8L8V8U8 */
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{SVGA3DBLOCKDESC_UVWA,
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{1, 1, 1}, 4, 4, {32, {{10}, {10}, {10}, {2} } },
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{{{0}, {10}, {20}, {30} } } }, /* SVGA3D_A2W10V10U10 */
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{SVGA3DBLOCKDESC_ALPHA,
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{1, 1, 1}, 1, 1, {8, {{0}, {0}, {0}, {8} } },
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{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_ALPHA8 */
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{SVGA3DBLOCKDESC_R_FP,
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{1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
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{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R_S10E5 */
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{SVGA3DBLOCKDESC_R_FP,
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{1, 1, 1}, 4, 4, {32, {{0}, {0}, {32}, {0} } },
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{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R_S23E8 */
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{SVGA3DBLOCKDESC_RG_FP,
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{1, 1, 1}, 4, 4, {32, {{0}, {16}, {16}, {0} } },
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{{{0}, {16}, {0}, {0} } } }, /* SVGA3D_RG_S10E5 */
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{SVGA3DBLOCKDESC_RG_FP,
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{1, 1, 1}, 8, 8, {64, {{0}, {32}, {32}, {0} } },
|
||||
{{{0}, {32}, {0}, {0} } } }, /* SVGA3D_RG_S23E8 */
|
||||
|
||||
{SVGA3DBLOCKDESC_BUFFER,
|
||||
{1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BUFFER */
|
||||
|
||||
{SVGA3DBLOCKDESC_DEPTH,
|
||||
{1, 1, 1}, 4, 4, {32, {{0}, {0}, {24}, {0} } },
|
||||
{{{0}, {24}, {0}, {0} } } }, /* SVGA3D_Z_D24X8 */
|
||||
|
||||
{SVGA3DBLOCKDESC_UV,
|
||||
{1, 1, 1}, 4, 4, {32, {{16}, {16}, {0}, {0} } },
|
||||
{{{16}, {0}, {0}, {0} } } }, /* SVGA3D_V16U16 */
|
||||
|
||||
{SVGA3DBLOCKDESC_RG,
|
||||
{1, 1, 1}, 4, 4, {32, {{0}, {16}, {16}, {0} } },
|
||||
{{{0}, {0}, {16}, {0} } } }, /* SVGA3D_G16R16 */
|
||||
|
||||
{SVGA3DBLOCKDESC_RGBA,
|
||||
{1, 1, 1}, 8, 8, {64, {{16}, {16}, {16}, {16} } },
|
||||
{{{32}, {16}, {0}, {48} } } }, /* SVGA3D_A16B16G16R16 */
|
||||
|
||||
{SVGA3DBLOCKDESC_YUV,
|
||||
{1, 1, 1}, 2, 2, {16, {{8}, {0}, {8}, {0} } },
|
||||
{{{0}, {0}, {8}, {0} } } }, /* SVGA3D_UYVY */
|
||||
|
||||
{SVGA3DBLOCKDESC_YUV,
|
||||
{1, 1, 1}, 2, 2, {16, {{8}, {0}, {8}, {0} } },
|
||||
{{{8}, {0}, {0}, {0} } } }, /* SVGA3D_YUY2 */
|
||||
|
||||
{SVGA3DBLOCKDESC_NV12,
|
||||
{2, 2, 1}, 6, 2, {48, {{0}, {0}, {48}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_NV12 */
|
||||
|
||||
{SVGA3DBLOCKDESC_AYUV,
|
||||
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
|
||||
{{{0}, {8}, {16}, {24} } } }, /* SVGA3D_AYUV */
|
||||
|
||||
{SVGA3DBLOCKDESC_RGBA,
|
||||
{1, 1, 1}, 16, 16, {128, {{32}, {32}, {32}, {32} } },
|
||||
{{{64}, {32}, {0}, {96} } } }, /* SVGA3D_R32G32B32A32_TYPELESS */
|
||||
|
||||
{SVGA3DBLOCKDESC_RGBA,
|
||||
{1, 1, 1}, 16, 16, {128, {{32}, {32}, {32}, {32} } },
|
||||
{{{64}, {32}, {0}, {96} } } }, /* SVGA3D_R32G32B32A32_UINT */
|
||||
|
||||
{SVGA3DBLOCKDESC_UVWQ,
|
||||
{1, 1, 1}, 16, 16, {128, {{32}, {32}, {32}, {32} } },
|
||||
{{{64}, {32}, {0}, {96} } } }, /* SVGA3D_R32G32B32A32_SINT */
|
||||
|
||||
{SVGA3DBLOCKDESC_RGB,
|
||||
{1, 1, 1}, 12, 12, {96, {{32}, {32}, {32}, {0} } },
|
||||
{{{64}, {32}, {0}, {0} } } }, /* SVGA3D_R32G32B32_TYPELESS */
|
||||
|
||||
{SVGA3DBLOCKDESC_RGB_FP,
|
||||
{1, 1, 1}, 12, 12, {96, {{32}, {32}, {32}, {0} } },
|
||||
{{{64}, {32}, {0}, {0} } } }, /* SVGA3D_R32G32B32_FLOAT */
|
||||
|
||||
{SVGA3DBLOCKDESC_RGB,
|
||||
{1, 1, 1}, 12, 12, {96, {{32}, {32}, {32}, {0} } },
|
||||
{{{64}, {32}, {0}, {0} } } }, /* SVGA3D_R32G32B32_UINT */
|
||||
|
||||
{SVGA3DBLOCKDESC_UVW,
|
||||
{1, 1, 1}, 12, 12, {96, {{32}, {32}, {32}, {0} } },
|
||||
{{{64}, {32}, {0}, {0} } } }, /* SVGA3D_R32G32B32_SINT */
|
||||
|
||||
{SVGA3DBLOCKDESC_RGBA,
|
||||
{1, 1, 1}, 8, 8, {64, {{16}, {16}, {16}, {16} } },
|
||||
{{{32}, {16}, {0}, {48} } } }, /* SVGA3D_R16G16B16A16_TYPELESS */
|
||||
|
||||
{SVGA3DBLOCKDESC_RGBA,
|
||||
{1, 1, 1}, 8, 8, {64, {{16}, {16}, {16}, {16} } },
|
||||
{{{32}, {16}, {0}, {48} } } }, /* SVGA3D_R16G16B16A16_UINT */
|
||||
|
||||
{SVGA3DBLOCKDESC_UVWQ,
|
||||
{1, 1, 1}, 8, 8, {64, {{16}, {16}, {16}, {16} } },
|
||||
{{{32}, {16}, {0}, {48} } } }, /* SVGA3D_R16G16B16A16_SNORM */
|
||||
|
||||
{SVGA3DBLOCKDESC_UVWQ,
|
||||
{1, 1, 1}, 8, 8, {64, {{16}, {16}, {16}, {16} } },
|
||||
{{{32}, {16}, {0}, {48} } } }, /* SVGA3D_R16G16B16A16_SINT */
|
||||
|
||||
{SVGA3DBLOCKDESC_RG,
|
||||
{1, 1, 1}, 8, 8, {64, {{0}, {32}, {32}, {0} } },
|
||||
{{{0}, {32}, {0}, {0} } } }, /* SVGA3D_R32G32_TYPELESS */
|
||||
|
||||
{SVGA3DBLOCKDESC_RG,
|
||||
{1, 1, 1}, 8, 8, {64, {{0}, {32}, {32}, {0} } },
|
||||
{{{0}, {32}, {0}, {0} } } }, /* SVGA3D_R32G32_UINT */
|
||||
|
||||
{SVGA3DBLOCKDESC_UV,
|
||||
{1, 1, 1}, 8, 8, {64, {{0}, {32}, {32}, {0} } },
|
||||
{{{0}, {32}, {0}, {0} } } }, /* SVGA3D_R32G32_SINT */
|
||||
|
||||
{SVGA3DBLOCKDESC_RG,
|
||||
{1, 1, 1}, 8, 8, {64, {{0}, {8}, {32}, {0} } },
|
||||
{{{0}, {32}, {0}, {0} } } }, /* SVGA3D_R32G8X24_TYPELESS */
|
||||
|
||||
{SVGA3DBLOCKDESC_DS,
|
||||
{1, 1, 1}, 8, 8, {64, {{0}, {8}, {32}, {0} } },
|
||||
{{{0}, {32}, {0}, {0} } } }, /* SVGA3D_D32_FLOAT_S8X24_UINT */
|
||||
|
||||
{SVGA3DBLOCKDESC_R_FP,
|
||||
{1, 1, 1}, 8, 8, {64, {{0}, {0}, {32}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R32_FLOAT_X8_X24_TYPELESS */
|
||||
|
||||
{SVGA3DBLOCKDESC_GREEN,
|
||||
{1, 1, 1}, 8, 8, {64, {{0}, {8}, {0}, {0} } },
|
||||
{{{0}, {32}, {0}, {0} } } }, /* SVGA3D_X32_TYPELESS_G8X24_UINT */
|
||||
|
||||
{SVGA3DBLOCKDESC_RGBA,
|
||||
{1, 1, 1}, 4, 4, {32, {{10}, {10}, {10}, {2} } },
|
||||
{{{0}, {10}, {20}, {30} } } }, /* SVGA3D_R10G10B10A2_TYPELESS */
|
||||
|
||||
{SVGA3DBLOCKDESC_RGBA,
|
||||
{1, 1, 1}, 4, 4, {32, {{10}, {10}, {10}, {2} } },
|
||||
{{{0}, {10}, {20}, {30} } } }, /* SVGA3D_R10G10B10A2_UINT */
|
||||
|
||||
{SVGA3DBLOCKDESC_RGB_FP,
|
||||
{1, 1, 1}, 4, 4, {32, {{10}, {11}, {11}, {0} } },
|
||||
{{{0}, {10}, {21}, {0} } } }, /* SVGA3D_R11G11B10_FLOAT */
|
||||
|
||||
{SVGA3DBLOCKDESC_RGBA,
|
||||
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
|
||||
{{{16}, {8}, {0}, {24} } } }, /* SVGA3D_R8G8B8A8_TYPELESS */
|
||||
|
||||
{SVGA3DBLOCKDESC_RGBA,
|
||||
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
|
||||
{{{16}, {8}, {0}, {24} } } }, /* SVGA3D_R8G8B8A8_UNORM */
|
||||
|
||||
{SVGA3DBLOCKDESC_RGBA_SRGB,
|
||||
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
|
||||
{{{16}, {8}, {0}, {24} } } }, /* SVGA3D_R8G8B8A8_UNORM_SRGB */
|
||||
|
||||
{SVGA3DBLOCKDESC_RGBA,
|
||||
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
|
||||
{{{16}, {8}, {0}, {24} } } }, /* SVGA3D_R8G8B8A8_UINT */
|
||||
|
||||
{SVGA3DBLOCKDESC_RGBA,
|
||||
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
|
||||
{{{16}, {8}, {0}, {24} } } }, /* SVGA3D_R8G8B8A8_SINT */
|
||||
|
||||
{SVGA3DBLOCKDESC_RG,
|
||||
{1, 1, 1}, 4, 4, {32, {{0}, {16}, {16}, {0} } },
|
||||
{{{0}, {16}, {0}, {0} } } }, /* SVGA3D_R16G16_TYPELESS */
|
||||
|
||||
{SVGA3DBLOCKDESC_RG_FP,
|
||||
{1, 1, 1}, 4, 4, {32, {{0}, {16}, {16}, {0} } },
|
||||
{{{0}, {16}, {0}, {0} } } }, /* SVGA3D_R16G16_UINT */
|
||||
|
||||
{SVGA3DBLOCKDESC_UV,
|
||||
{1, 1, 1}, 4, 4, {32, {{0}, {16}, {16}, {0} } },
|
||||
{{{0}, {16}, {0}, {0} } } }, /* SVGA3D_R16G16_SINT */
|
||||
|
||||
{SVGA3DBLOCKDESC_RED,
|
||||
{1, 1, 1}, 4, 4, {32, {{0}, {0}, {32}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R32_TYPELESS */
|
||||
|
||||
{SVGA3DBLOCKDESC_DEPTH,
|
||||
{1, 1, 1}, 4, 4, {32, {{0}, {0}, {32}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_D32_FLOAT */
|
||||
|
||||
{SVGA3DBLOCKDESC_RED,
|
||||
{1, 1, 1}, 4, 4, {32, {{0}, {0}, {32}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R32_UINT */
|
||||
|
||||
{SVGA3DBLOCKDESC_RED,
|
||||
{1, 1, 1}, 4, 4, {32, {{0}, {0}, {32}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R32_SINT */
|
||||
|
||||
{SVGA3DBLOCKDESC_RG,
|
||||
{1, 1, 1}, 4, 4, {32, {{0}, {8}, {24}, {0} } },
|
||||
{{{0}, {24}, {0}, {0} } } }, /* SVGA3D_R24G8_TYPELESS */
|
||||
|
||||
{SVGA3DBLOCKDESC_DS,
|
||||
{1, 1, 1}, 4, 4, {32, {{0}, {8}, {24}, {0} } },
|
||||
{{{0}, {24}, {0}, {0} } } }, /* SVGA3D_D24_UNORM_S8_UINT */
|
||||
|
||||
{SVGA3DBLOCKDESC_RED,
|
||||
{1, 1, 1}, 4, 4, {32, {{0}, {0}, {24}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R24_UNORM_X8_TYPELESS */
|
||||
|
||||
{SVGA3DBLOCKDESC_GREEN,
|
||||
{1, 1, 1}, 4, 4, {32, {{0}, {8}, {0}, {0} } },
|
||||
{{{0}, {24}, {0}, {0} } } }, /* SVGA3D_X24_TYPELESS_G8_UINT */
|
||||
|
||||
{SVGA3DBLOCKDESC_RG,
|
||||
{1, 1, 1}, 2, 2, {16, {{0}, {8}, {8}, {0} } },
|
||||
{{{0}, {8}, {0}, {0} } } }, /* SVGA3D_R8G8_TYPELESS */
|
||||
|
||||
{SVGA3DBLOCKDESC_RG,
|
||||
{1, 1, 1}, 2, 2, {16, {{0}, {8}, {8}, {0} } },
|
||||
{{{0}, {8}, {0}, {0} } } }, /* SVGA3D_R8G8_UNORM */
|
||||
|
||||
{SVGA3DBLOCKDESC_RG,
|
||||
{1, 1, 1}, 2, 2, {16, {{0}, {8}, {8}, {0} } },
|
||||
{{{0}, {8}, {0}, {0} } } }, /* SVGA3D_R8G8_UINT */
|
||||
|
||||
{SVGA3DBLOCKDESC_UV,
|
||||
{1, 1, 1}, 2, 2, {16, {{0}, {8}, {8}, {0} } },
|
||||
{{{0}, {8}, {0}, {0} } } }, /* SVGA3D_R8G8_SINT */
|
||||
|
||||
{SVGA3DBLOCKDESC_RED,
|
||||
{1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R16_TYPELESS */
|
||||
|
||||
{SVGA3DBLOCKDESC_RED,
|
||||
{1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R16_UNORM */
|
||||
|
||||
{SVGA3DBLOCKDESC_RED,
|
||||
{1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R16_UINT */
|
||||
|
||||
{SVGA3DBLOCKDESC_U,
|
||||
{1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R16_SNORM */
|
||||
|
||||
{SVGA3DBLOCKDESC_U,
|
||||
{1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R16_SINT */
|
||||
|
||||
{SVGA3DBLOCKDESC_RED,
|
||||
{1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R8_TYPELESS */
|
||||
|
||||
{SVGA3DBLOCKDESC_RED,
|
||||
{1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R8_UNORM */
|
||||
|
||||
{SVGA3DBLOCKDESC_RED,
|
||||
{1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R8_UINT */
|
||||
|
||||
{SVGA3DBLOCKDESC_U,
|
||||
{1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R8_SNORM */
|
||||
|
||||
{SVGA3DBLOCKDESC_U,
|
||||
{1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R8_SINT */
|
||||
|
||||
{SVGA3DBLOCKDESC_RED,
|
||||
{8, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R1_UNORM */
|
||||
|
||||
{SVGA3DBLOCKDESC_RGBE,
|
||||
{1, 1, 1}, 4, 4, {32, {{9}, {9}, {9}, {5} } },
|
||||
{{{18}, {9}, {0}, {27} } } }, /* SVGA3D_R9G9B9E5_SHAREDEXP */
|
||||
|
||||
{SVGA3DBLOCKDESC_RG,
|
||||
{1, 1, 1}, 2, 2, {16, {{0}, {8}, {8}, {0} } },
|
||||
{{{0}, {8}, {0}, {0} } } }, /* SVGA3D_R8G8_B8G8_UNORM */
|
||||
|
||||
{SVGA3DBLOCKDESC_RG,
|
||||
{1, 1, 1}, 2, 2, {16, {{0}, {8}, {8}, {0} } },
|
||||
{{{0}, {8}, {0}, {0} } } }, /* SVGA3D_G8R8_G8B8_UNORM */
|
||||
|
||||
{SVGA3DBLOCKDESC_COMPRESSED,
|
||||
{4, 4, 1}, 8, 8, {64, {{0}, {0}, {64}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC1_TYPELESS */
|
||||
|
||||
{SVGA3DBLOCKDESC_COMPRESSED_SRGB,
|
||||
{4, 4, 1}, 8, 8, {64, {{0}, {0}, {64}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC1_UNORM_SRGB */
|
||||
|
||||
{SVGA3DBLOCKDESC_COMPRESSED,
|
||||
{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC2_TYPELESS */
|
||||
|
||||
{SVGA3DBLOCKDESC_COMPRESSED_SRGB,
|
||||
{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC2_UNORM_SRGB */
|
||||
|
||||
{SVGA3DBLOCKDESC_COMPRESSED,
|
||||
{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC3_TYPELESS */
|
||||
|
||||
{SVGA3DBLOCKDESC_COMPRESSED_SRGB,
|
||||
{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC3_UNORM_SRGB */
|
||||
|
||||
{SVGA3DBLOCKDESC_COMPRESSED,
|
||||
{4, 4, 1}, 8, 8, {64, {{0}, {0}, {64}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC4_TYPELESS */
|
||||
|
||||
{SVGA3DBLOCKDESC_COMPRESSED,
|
||||
{4, 4, 1}, 8, 8, {64, {{0}, {0}, {64}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC4_UNORM */
|
||||
|
||||
{SVGA3DBLOCKDESC_COMPRESSED,
|
||||
{4, 4, 1}, 8, 8, {64, {{0}, {0}, {64}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC4_SNORM */
|
||||
|
||||
{SVGA3DBLOCKDESC_COMPRESSED,
|
||||
{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC5_TYPELESS */
|
||||
|
||||
{SVGA3DBLOCKDESC_COMPRESSED,
|
||||
{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC5_UNORM */
|
||||
|
||||
{SVGA3DBLOCKDESC_COMPRESSED,
|
||||
{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC5_SNORM */
|
||||
|
||||
{SVGA3DBLOCKDESC_RGBA,
|
||||
{1, 1, 1}, 4, 4, {32, {{10}, {10}, {10}, {2} } },
|
||||
{{{0}, {10}, {20}, {30} } } }, /* SVGA3D_R10G10B10_XR_BIAS_A2_UNORM */
|
||||
|
||||
{SVGA3DBLOCKDESC_RGBA,
|
||||
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
|
||||
{{{0}, {8}, {16}, {24} } } }, /* SVGA3D_B8G8R8A8_TYPELESS */
|
||||
|
||||
{SVGA3DBLOCKDESC_RGBA_SRGB,
|
||||
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
|
||||
{{{0}, {8}, {16}, {24} } } }, /* SVGA3D_B8G8R8A8_UNORM_SRGB */
|
||||
|
||||
{SVGA3DBLOCKDESC_RGB,
|
||||
{1, 1, 1}, 4, 4, {24, {{8}, {8}, {8}, {0} } },
|
||||
{{{0}, {8}, {16}, {24} } } }, /* SVGA3D_B8G8R8X8_TYPELESS */
|
||||
|
||||
{SVGA3DBLOCKDESC_RGB_SRGB,
|
||||
{1, 1, 1}, 4, 4, {24, {{8}, {8}, {8}, {0} } },
|
||||
{{{0}, {8}, {16}, {24} } } }, /* SVGA3D_B8G8R8X8_UNORM_SRGB */
|
||||
|
||||
{SVGA3DBLOCKDESC_DEPTH,
|
||||
{1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
|
||||
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_Z_DF16 */
|
||||
|
||||
{SVGA3DBLOCKDESC_DS,
|
||||
{1, 1, 1}, 4, 4, {32, {{0}, {8}, {24}, {0} } },
|
||||
{{{0}, {24}, {0}, {0} } } }, /* SVGA3D_Z_DF24 */
|
||||
|
||||
{SVGA3DBLOCKDESC_DS,
|
||||
{1, 1, 1}, 4, 4, {32, {{0}, {8}, {24}, {0} } },
|
||||
{{{0}, {24}, {0}, {0} } } }, /* SVGA3D_Z_D24S8_INT */
|
||||
};
|
||||
|
||||
static inline u32 clamped_umul32(u32 a, u32 b)
|
||||
{
|
||||
uint64_t tmp = (uint64_t) a*b;
|
||||
return (tmp > (uint64_t) ((u32) -1)) ? (u32) -1 : tmp;
|
||||
}
|
||||
|
||||
static inline const struct svga3d_surface_desc *
|
||||
svga3dsurface_get_desc(SVGA3dSurfaceFormat format)
|
||||
{
|
||||
if (format < ARRAY_SIZE(svga3d_surface_descs))
|
||||
return &svga3d_surface_descs[format];
|
||||
|
||||
return &svga3d_surface_descs[SVGA3D_FORMAT_INVALID];
|
||||
}
|
||||
|
||||
/*
|
||||
*----------------------------------------------------------------------
|
||||
*
|
||||
* svga3dsurface_get_mip_size --
|
||||
*
|
||||
* Given a base level size and the mip level, compute the size of
|
||||
* the mip level.
|
||||
*
|
||||
* Results:
|
||||
* See above.
|
||||
*
|
||||
* Side effects:
|
||||
* None.
|
||||
*
|
||||
*----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
static inline surf_size_struct
|
||||
svga3dsurface_get_mip_size(surf_size_struct base_level, u32 mip_level)
|
||||
{
|
||||
surf_size_struct size;
|
||||
|
||||
size.width = max_t(u32, base_level.width >> mip_level, 1);
|
||||
size.height = max_t(u32, base_level.height >> mip_level, 1);
|
||||
size.depth = max_t(u32, base_level.depth >> mip_level, 1);
|
||||
return size;
|
||||
}
|
||||
|
||||
static inline void
|
||||
svga3dsurface_get_size_in_blocks(const struct svga3d_surface_desc *desc,
|
||||
const surf_size_struct *pixel_size,
|
||||
surf_size_struct *block_size)
|
||||
{
|
||||
block_size->width = DIV_ROUND_UP(pixel_size->width,
|
||||
desc->block_size.width);
|
||||
block_size->height = DIV_ROUND_UP(pixel_size->height,
|
||||
desc->block_size.height);
|
||||
block_size->depth = DIV_ROUND_UP(pixel_size->depth,
|
||||
desc->block_size.depth);
|
||||
}
|
||||
|
||||
static inline bool
|
||||
svga3dsurface_is_planar_surface(const struct svga3d_surface_desc *desc)
|
||||
{
|
||||
return (desc->block_desc & SVGA3DBLOCKDESC_PLANAR_YUV) != 0;
|
||||
}
|
||||
|
||||
static inline u32
|
||||
svga3dsurface_calculate_pitch(const struct svga3d_surface_desc *desc,
|
||||
const surf_size_struct *size)
|
||||
{
|
||||
u32 pitch;
|
||||
surf_size_struct blocks;
|
||||
|
||||
svga3dsurface_get_size_in_blocks(desc, size, &blocks);
|
||||
|
||||
pitch = blocks.width * desc->pitch_bytes_per_block;
|
||||
|
||||
return pitch;
|
||||
}
|
||||
|
||||
/*
|
||||
*-----------------------------------------------------------------------------
|
||||
*
|
||||
* svga3dsurface_get_image_buffer_size --
|
||||
*
|
||||
* Return the number of bytes of buffer space required to store
|
||||
* one image of a surface, optionally using the specified pitch.
|
||||
*
|
||||
* If pitch is zero, it is assumed that rows are tightly packed.
|
||||
*
|
||||
* This function is overflow-safe. If the result would have
|
||||
* overflowed, instead we return MAX_UINT32.
|
||||
*
|
||||
* Results:
|
||||
* Byte count.
|
||||
*
|
||||
* Side effects:
|
||||
* None.
|
||||
*
|
||||
*-----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
static inline u32
|
||||
svga3dsurface_get_image_buffer_size(const struct svga3d_surface_desc *desc,
|
||||
const surf_size_struct *size,
|
||||
u32 pitch)
|
||||
{
|
||||
surf_size_struct image_blocks;
|
||||
u32 slice_size, total_size;
|
||||
|
||||
svga3dsurface_get_size_in_blocks(desc, size, &image_blocks);
|
||||
|
||||
if (svga3dsurface_is_planar_surface(desc)) {
|
||||
total_size = clamped_umul32(image_blocks.width,
|
||||
image_blocks.height);
|
||||
total_size = clamped_umul32(total_size, image_blocks.depth);
|
||||
total_size = clamped_umul32(total_size, desc->bytes_per_block);
|
||||
return total_size;
|
||||
}
|
||||
|
||||
if (pitch == 0)
|
||||
pitch = svga3dsurface_calculate_pitch(desc, size);
|
||||
|
||||
slice_size = clamped_umul32(image_blocks.height, pitch);
|
||||
total_size = clamped_umul32(slice_size, image_blocks.depth);
|
||||
|
||||
return total_size;
|
||||
}
|
||||
|
||||
static inline u32
|
||||
svga3dsurface_get_serialized_size(SVGA3dSurfaceFormat format,
|
||||
surf_size_struct base_level_size,
|
||||
u32 num_mip_levels,
|
||||
bool cubemap)
|
||||
{
|
||||
const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format);
|
||||
u32 total_size = 0;
|
||||
u32 mip;
|
||||
|
||||
for (mip = 0; mip < num_mip_levels; mip++) {
|
||||
surf_size_struct size =
|
||||
svga3dsurface_get_mip_size(base_level_size, mip);
|
||||
total_size += svga3dsurface_get_image_buffer_size(desc,
|
||||
&size, 0);
|
||||
}
|
||||
|
||||
if (cubemap)
|
||||
total_size *= SVGA3D_MAX_SURFACE_FACES;
|
||||
|
||||
return total_size;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* svga3dsurface_get_pixel_offset - Compute the offset (in bytes) to a pixel
|
||||
* in an image (or volume).
|
||||
*
|
||||
* @width: The image width in pixels.
|
||||
* @height: The image height in pixels
|
||||
*/
|
||||
static inline u32
|
||||
svga3dsurface_get_pixel_offset(SVGA3dSurfaceFormat format,
|
||||
u32 width, u32 height,
|
||||
u32 x, u32 y, u32 z)
|
||||
{
|
||||
const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format);
|
||||
const u32 bw = desc->block_size.width, bh = desc->block_size.height;
|
||||
const u32 bd = desc->block_size.depth;
|
||||
const u32 rowstride = DIV_ROUND_UP(width, bw) * desc->bytes_per_block;
|
||||
const u32 imgstride = DIV_ROUND_UP(height, bh) * rowstride;
|
||||
const u32 offset = (z / bd * imgstride +
|
||||
y / bh * rowstride +
|
||||
x / bw * desc->bytes_per_block);
|
||||
return offset;
|
||||
}
|
||||
|
||||
|
||||
static inline u32
|
||||
svga3dsurface_get_image_offset(SVGA3dSurfaceFormat format,
|
||||
surf_size_struct baseLevelSize,
|
||||
u32 numMipLevels,
|
||||
u32 face,
|
||||
u32 mip)
|
||||
|
||||
{
|
||||
u32 offset;
|
||||
u32 mipChainBytes;
|
||||
u32 mipChainBytesToLevel;
|
||||
u32 i;
|
||||
const struct svga3d_surface_desc *desc;
|
||||
surf_size_struct mipSize;
|
||||
u32 bytes;
|
||||
|
||||
desc = svga3dsurface_get_desc(format);
|
||||
|
||||
mipChainBytes = 0;
|
||||
mipChainBytesToLevel = 0;
|
||||
for (i = 0; i < numMipLevels; i++) {
|
||||
mipSize = svga3dsurface_get_mip_size(baseLevelSize, i);
|
||||
bytes = svga3dsurface_get_image_buffer_size(desc, &mipSize, 0);
|
||||
mipChainBytes += bytes;
|
||||
if (i < mip)
|
||||
mipChainBytesToLevel += bytes;
|
||||
}
|
||||
|
||||
offset = mipChainBytes * face + mipChainBytesToLevel;
|
||||
|
||||
return offset;
|
||||
}
|
||||
@ -28,6 +28,7 @@
|
||||
#include "vmwgfx_drv.h"
|
||||
#include "vmwgfx_resource_priv.h"
|
||||
#include <ttm/ttm_placement.h>
|
||||
#include "svga3d_surfacedefs.h"
|
||||
|
||||
/**
|
||||
* struct vmw_user_surface - User-space visible surface resource
|
||||
@ -92,85 +93,6 @@ static const struct vmw_res_func vmw_legacy_surface_func = {
|
||||
.unbind = &vmw_legacy_srf_unbind
|
||||
};
|
||||
|
||||
/**
|
||||
* struct vmw_bpp - Bits per pixel info for surface storage size computation.
|
||||
*
|
||||
* @bpp: Bits per pixel.
|
||||
* @s_bpp: Stride bits per pixel. See definition below.
|
||||
*
|
||||
*/
|
||||
struct vmw_bpp {
|
||||
uint8_t bpp;
|
||||
uint8_t s_bpp;
|
||||
};
|
||||
|
||||
/*
|
||||
* Size table for the supported SVGA3D surface formats. It consists of
|
||||
* two values. The bpp value and the s_bpp value which is short for
|
||||
* "stride bits per pixel" The values are given in such a way that the
|
||||
* minimum stride for the image is calculated using
|
||||
*
|
||||
* min_stride = w*s_bpp
|
||||
*
|
||||
* and the total memory requirement for the image is
|
||||
*
|
||||
* h*min_stride*bpp/s_bpp
|
||||
*
|
||||
*/
|
||||
static const struct vmw_bpp vmw_sf_bpp[] = {
|
||||
[SVGA3D_FORMAT_INVALID] = {0, 0},
|
||||
[SVGA3D_X8R8G8B8] = {32, 32},
|
||||
[SVGA3D_A8R8G8B8] = {32, 32},
|
||||
[SVGA3D_R5G6B5] = {16, 16},
|
||||
[SVGA3D_X1R5G5B5] = {16, 16},
|
||||
[SVGA3D_A1R5G5B5] = {16, 16},
|
||||
[SVGA3D_A4R4G4B4] = {16, 16},
|
||||
[SVGA3D_Z_D32] = {32, 32},
|
||||
[SVGA3D_Z_D16] = {16, 16},
|
||||
[SVGA3D_Z_D24S8] = {32, 32},
|
||||
[SVGA3D_Z_D15S1] = {16, 16},
|
||||
[SVGA3D_LUMINANCE8] = {8, 8},
|
||||
[SVGA3D_LUMINANCE4_ALPHA4] = {8, 8},
|
||||
[SVGA3D_LUMINANCE16] = {16, 16},
|
||||
[SVGA3D_LUMINANCE8_ALPHA8] = {16, 16},
|
||||
[SVGA3D_DXT1] = {4, 16},
|
||||
[SVGA3D_DXT2] = {8, 32},
|
||||
[SVGA3D_DXT3] = {8, 32},
|
||||
[SVGA3D_DXT4] = {8, 32},
|
||||
[SVGA3D_DXT5] = {8, 32},
|
||||
[SVGA3D_BUMPU8V8] = {16, 16},
|
||||
[SVGA3D_BUMPL6V5U5] = {16, 16},
|
||||
[SVGA3D_BUMPX8L8V8U8] = {32, 32},
|
||||
[SVGA3D_ARGB_S10E5] = {16, 16},
|
||||
[SVGA3D_ARGB_S23E8] = {32, 32},
|
||||
[SVGA3D_A2R10G10B10] = {32, 32},
|
||||
[SVGA3D_V8U8] = {16, 16},
|
||||
[SVGA3D_Q8W8V8U8] = {32, 32},
|
||||
[SVGA3D_CxV8U8] = {16, 16},
|
||||
[SVGA3D_X8L8V8U8] = {32, 32},
|
||||
[SVGA3D_A2W10V10U10] = {32, 32},
|
||||
[SVGA3D_ALPHA8] = {8, 8},
|
||||
[SVGA3D_R_S10E5] = {16, 16},
|
||||
[SVGA3D_R_S23E8] = {32, 32},
|
||||
[SVGA3D_RG_S10E5] = {16, 16},
|
||||
[SVGA3D_RG_S23E8] = {32, 32},
|
||||
[SVGA3D_BUFFER] = {8, 8},
|
||||
[SVGA3D_Z_D24X8] = {32, 32},
|
||||
[SVGA3D_V16U16] = {32, 32},
|
||||
[SVGA3D_G16R16] = {32, 32},
|
||||
[SVGA3D_A16B16G16R16] = {64, 64},
|
||||
[SVGA3D_UYVY] = {12, 12},
|
||||
[SVGA3D_YUY2] = {12, 12},
|
||||
[SVGA3D_NV12] = {12, 8},
|
||||
[SVGA3D_AYUV] = {32, 32},
|
||||
[SVGA3D_BC4_UNORM] = {4, 16},
|
||||
[SVGA3D_BC5_UNORM] = {8, 32},
|
||||
[SVGA3D_Z_DF16] = {16, 16},
|
||||
[SVGA3D_Z_DF24] = {24, 24},
|
||||
[SVGA3D_Z_D24S8_INT] = {32, 32}
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* struct vmw_surface_dma - SVGA3D DMA command
|
||||
*/
|
||||
@ -307,9 +229,9 @@ static void vmw_surface_dma_encode(struct vmw_surface *srf,
|
||||
bool to_surface)
|
||||
{
|
||||
uint32_t i;
|
||||
uint32_t bpp = vmw_sf_bpp[srf->format].bpp;
|
||||
uint32_t stride_bpp = vmw_sf_bpp[srf->format].s_bpp;
|
||||
struct vmw_surface_dma *cmd = (struct vmw_surface_dma *)cmd_space;
|
||||
const struct svga3d_surface_desc *desc =
|
||||
svga3dsurface_get_desc(srf->format);
|
||||
|
||||
for (i = 0; i < srf->num_sizes; ++i) {
|
||||
SVGA3dCmdHeader *header = &cmd->header;
|
||||
@ -324,7 +246,8 @@ static void vmw_surface_dma_encode(struct vmw_surface *srf,
|
||||
|
||||
body->guest.ptr = *ptr;
|
||||
body->guest.ptr.offset += cur_offset->bo_offset;
|
||||
body->guest.pitch = (cur_size->width * stride_bpp + 7) >> 3;
|
||||
body->guest.pitch = svga3dsurface_calculate_pitch(desc,
|
||||
cur_size);
|
||||
body->host.sid = srf->res.id;
|
||||
body->host.face = cur_offset->face;
|
||||
body->host.mipmap = cur_offset->mip;
|
||||
@ -341,8 +264,9 @@ static void vmw_surface_dma_encode(struct vmw_surface *srf,
|
||||
cb->d = cur_size->depth;
|
||||
|
||||
suffix->suffixSize = sizeof(*suffix);
|
||||
suffix->maximumOffset = body->guest.pitch*cur_size->height*
|
||||
cur_size->depth*bpp / stride_bpp;
|
||||
suffix->maximumOffset =
|
||||
svga3dsurface_get_image_buffer_size(desc, cur_size,
|
||||
body->guest.pitch);
|
||||
suffix->flags.discard = 0;
|
||||
suffix->flags.unsynchronized = 0;
|
||||
suffix->flags.reserved = 0;
|
||||
@ -743,11 +667,10 @@ int vmw_surface_define_ioctl(struct drm_device *dev, void *data,
|
||||
uint32_t cur_bo_offset;
|
||||
struct drm_vmw_size *cur_size;
|
||||
struct vmw_surface_offset *cur_offset;
|
||||
uint32_t stride_bpp;
|
||||
uint32_t bpp;
|
||||
uint32_t num_sizes;
|
||||
uint32_t size;
|
||||
struct vmw_master *vmaster = vmw_master(file_priv->master);
|
||||
const struct svga3d_surface_desc *desc;
|
||||
|
||||
if (unlikely(vmw_user_surface_size == 0))
|
||||
vmw_user_surface_size = ttm_round_pot(sizeof(*user_srf)) +
|
||||
@ -766,6 +689,12 @@ int vmw_surface_define_ioctl(struct drm_device *dev, void *data,
|
||||
ttm_round_pot(num_sizes * sizeof(struct vmw_surface_offset));
|
||||
|
||||
|
||||
desc = svga3dsurface_get_desc(req->format);
|
||||
if (unlikely(desc->block_desc == SVGA3DBLOCKDESC_NONE)) {
|
||||
DRM_ERROR("Invalid surface format for surface creation.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = ttm_read_lock(&vmaster->lock, true);
|
||||
if (unlikely(ret != 0))
|
||||
return ret;
|
||||
@ -826,25 +755,21 @@ int vmw_surface_define_ioctl(struct drm_device *dev, void *data,
|
||||
cur_offset = srf->offsets;
|
||||
cur_size = srf->sizes;
|
||||
|
||||
bpp = vmw_sf_bpp[srf->format].bpp;
|
||||
stride_bpp = vmw_sf_bpp[srf->format].s_bpp;
|
||||
|
||||
for (i = 0; i < DRM_VMW_MAX_SURFACE_FACES; ++i) {
|
||||
for (j = 0; j < srf->mip_levels[i]; ++j) {
|
||||
uint32_t stride =
|
||||
(cur_size->width * stride_bpp + 7) >> 3;
|
||||
uint32_t stride = svga3dsurface_calculate_pitch
|
||||
(desc, cur_size);
|
||||
|
||||
cur_offset->face = i;
|
||||
cur_offset->mip = j;
|
||||
cur_offset->bo_offset = cur_bo_offset;
|
||||
cur_bo_offset += stride * cur_size->height *
|
||||
cur_size->depth * bpp / stride_bpp;
|
||||
cur_bo_offset += svga3dsurface_get_image_buffer_size
|
||||
(desc, cur_size, stride);
|
||||
++cur_offset;
|
||||
++cur_size;
|
||||
}
|
||||
}
|
||||
res->backup_size = cur_bo_offset;
|
||||
|
||||
if (srf->scanout &&
|
||||
srf->num_sizes == 1 &&
|
||||
srf->sizes[0].width == 64 &&
|
||||
|
||||
Loading…
Reference in New Issue
Block a user