power: bq24257: Add bit definition for temp sense enable

Adding a missing bit definition for the sake of consistency device model
vs. bit field representation. No change in functionality.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@intel.com>
Signed-off-by: Sebastian Reichel <sre@kernel.org>
This commit is contained in:
Andreas Dannenberg 2015-09-28 17:33:54 -05:00 committed by Sebastian Reichel
parent bf02dca9ee
commit 7ef62365c6

View File

@ -66,7 +66,7 @@ enum bq24257_fields {
F_VBAT, F_USB_DET, /* REG 3 */ F_VBAT, F_USB_DET, /* REG 3 */
F_ICHG, F_ITERM, /* REG 4 */ F_ICHG, F_ITERM, /* REG 4 */
F_LOOP_STATUS, F_LOW_CHG, F_DPDM_EN, F_CE_STATUS, F_VINDPM, /* REG 5 */ F_LOOP_STATUS, F_LOW_CHG, F_DPDM_EN, F_CE_STATUS, F_VINDPM, /* REG 5 */
F_X2_TMR_EN, F_TMR, F_SYSOFF, F_TS_STAT, /* REG 6 */ F_X2_TMR_EN, F_TMR, F_SYSOFF, F_TS_EN, F_TS_STAT, /* REG 6 */
F_VOVP, F_CLR_VDP, F_FORCE_BATDET, F_FORCE_PTM, /* REG 7 */ F_VOVP, F_CLR_VDP, F_FORCE_BATDET, F_FORCE_PTM, /* REG 7 */
F_MAX_FIELDS F_MAX_FIELDS
@ -156,6 +156,7 @@ static const struct reg_field bq24257_reg_fields[] = {
[F_X2_TMR_EN] = REG_FIELD(BQ24257_REG_6, 7, 7), [F_X2_TMR_EN] = REG_FIELD(BQ24257_REG_6, 7, 7),
[F_TMR] = REG_FIELD(BQ24257_REG_6, 5, 6), [F_TMR] = REG_FIELD(BQ24257_REG_6, 5, 6),
[F_SYSOFF] = REG_FIELD(BQ24257_REG_6, 4, 4), [F_SYSOFF] = REG_FIELD(BQ24257_REG_6, 4, 4),
[F_TS_EN] = REG_FIELD(BQ24257_REG_6, 3, 3),
[F_TS_STAT] = REG_FIELD(BQ24257_REG_6, 0, 2), [F_TS_STAT] = REG_FIELD(BQ24257_REG_6, 0, 2),
/* REG 7 */ /* REG 7 */
[F_VOVP] = REG_FIELD(BQ24257_REG_7, 5, 7), [F_VOVP] = REG_FIELD(BQ24257_REG_7, 5, 7),