FEX-Emu/linux
1
0
Fork 0
mirror of https://github.com/FEX-Emu/linux.git synced 2024-12-27 20:07:09 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

drm: sti: fix delay in VTG programming

Browse Source 
The HDMI path introduce a delay of 6 pixels.
This delay should be take into account while programming
VTG for the HDMI. Without this delay, the HDMI active
window area is shift of 6 pixel on the right.

Set also timing for DVO output.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
This commit is contained in:
Benjamin Gaignard 2014-12-05 10:14:11 +01:00
parent ca279601fb
commit 7f2d479c01
1 changed files with 28 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
drivers/gpu/drm/sti/sti_vtg.c
View File

@ -51,10 +51,19 @@
#define VTG_TOP_V_HD_3 0x010C
#define VTG_BOT_V_HD_3 0x0110
#define VTG_H_HD_4 0x0120
#define VTG_TOP_V_VD_4 0x0124
#define VTG_BOT_V_VD_4 0x0128
#define VTG_TOP_V_HD_4 0x012c
#define VTG_BOT_V_HD_4 0x0130
#define VTG_IRQ_BOTTOM BIT(0)
#define VTG_IRQ_TOP BIT(1)
#define VTG_IRQ_MASK (VTG_IRQ_TOP | VTG_IRQ_BOTTOM)
/* Delay introduced by the HDMI in nb of pixel */
#define HDMI_DELAY (6)
/* delay introduced by the Arbitrary Waveform Generator in nb of pixels */
#define AWG_DELAY_HD (-9)
#define AWG_DELAY_ED (-8)
@ -133,10 +142,10 @@ static void vtg_set_mode(struct sti_vtg *vtg,
writel(tmp, vtg->regs + VTG_VID_TFS);
writel(tmp, vtg->regs + VTG_VID_BFS);
/* prepare VTG set 1 and 2 for HDMI and VTG set 3 for HD DAC */
tmp = (mode->hsync_end - mode->hsync_start) << 16;
/* prepare VTG set 1 for HDMI */
tmp = (mode->hsync_end - mode->hsync_start + HDMI_DELAY) << 16;
tmp |= HDMI_DELAY;
writel(tmp, vtg->regs + VTG_H_HD_1);
writel(tmp, vtg->regs + VTG_H_HD_2);
tmp = (mode->vsync_end - mode->vsync_start + 1) << 16;
tmp |= 1;
@ -146,6 +155,11 @@ static void vtg_set_mode(struct sti_vtg *vtg,
writel(0, vtg->regs + VTG_BOT_V_HD_1);
/* prepare VTG set 2 for for HD DCS */
tmp = (mode->hsync_end - mode->hsync_start) << 16;
writel(tmp, vtg->regs + VTG_H_HD_2);
tmp = (mode->vsync_end - mode->vsync_start + 1) << 16;
tmp |= 1;
writel(tmp, vtg->regs + VTG_TOP_V_VD_2);
writel(tmp, vtg->regs + VTG_BOT_V_VD_2);
writel(0, vtg->regs + VTG_TOP_V_HD_2);
@ -166,6 +180,17 @@ static void vtg_set_mode(struct sti_vtg *vtg,
writel(tmp, vtg->regs + VTG_TOP_V_HD_3);
writel(tmp, vtg->regs + VTG_BOT_V_HD_3);
/* Prepare VTG set 4 for DVO */
tmp = (mode->hsync_end - mode->hsync_start) << 16;
writel(tmp, vtg->regs + VTG_H_HD_4);
tmp = (mode->vsync_end - mode->vsync_start + 1) << 16;
tmp |= 1;
writel(tmp, vtg->regs + VTG_TOP_V_VD_4);
writel(tmp, vtg->regs + VTG_BOT_V_VD_4);
writel(0, vtg->regs + VTG_TOP_V_HD_4);
writel(0, vtg->regs + VTG_BOT_V_HD_4);
/* mode */
writel(type, vtg->regs + VTG_MODE);
}