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drm/gma500/psb: Make use of generic clock code
Add chip specific callbacks for the generic and non-generic clock calculation code. Also remove as much dupilicated code as possible. Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
This commit is contained in:
Patrik Jakobsson
parent
fe477cc1b0
commit
7f67c06721
@ -25,7 +25,7 @@
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#include "psb_reg.h"
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#include "psb_intel_reg.h"
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#include "intel_bios.h"
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#include "psb_device.h"
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static int psb_output_init(struct drm_device *dev)
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{
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@ -380,6 +380,7 @@ const struct psb_ops psb_chip_ops = {
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.crtc_helper = &psb_intel_helper_funcs,
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.crtc_funcs = &psb_intel_crtc_funcs,
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.clock_funcs = &psb_clock_funcs,
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.output_init = psb_output_init,
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24
drivers/gpu/drm/gma500/psb_device.h
Normal file
24
drivers/gpu/drm/gma500/psb_device.h
Normal file
@ -0,0 +1,24 @@
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/*
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* Copyright © 2013 Patrik Jakobsson
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* Copyright © 2011 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef _PSB_DEVICE_H_
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#define _PSB_DEVICE_H_
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extern const struct gma_clock_funcs psb_clock_funcs;
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#endif
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@ -26,39 +26,13 @@
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#include "psb_drv.h"
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#include "psb_intel_drv.h"
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#include "psb_intel_reg.h"
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#include "psb_intel_display.h"
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#include "gma_display.h"
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#include "power.h"
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struct psb_intel_clock_t {
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/* given values */
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int n;
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int m1, m2;
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int p1, p2;
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/* derived values */
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int dot;
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int vco;
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int m;
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int p;
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};
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struct psb_intel_range_t {
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int min, max;
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};
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struct psb_intel_p2_t {
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int dot_limit;
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int p2_slow, p2_fast;
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};
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struct psb_intel_limit_t {
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struct psb_intel_range_t dot, vco, n, m, m1, m2, p, p1;
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struct psb_intel_p2_t p2;
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};
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#define INTEL_LIMIT_I9XX_SDVO_DAC 0
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#define INTEL_LIMIT_I9XX_LVDS 1
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static const struct psb_intel_limit_t psb_intel_limits[] = {
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static const struct gma_limit_t psb_intel_limits[] = {
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{ /* INTEL_LIMIT_I9XX_SDVO_DAC */
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.dot = {.min = 20000, .max = 400000},
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.vco = {.min = 1400000, .max = 2800000},
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@ -68,8 +42,8 @@ static const struct psb_intel_limit_t psb_intel_limits[] = {
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.m2 = {.min = 3, .max = 7},
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.p = {.min = 5, .max = 80},
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.p1 = {.min = 1, .max = 8},
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.p2 = {.dot_limit = 200000,
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.p2_slow = 10, .p2_fast = 5},
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.p2 = {.dot_limit = 200000, .p2_slow = 10, .p2_fast = 5},
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.find_pll = gma_find_best_pll,
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},
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{ /* INTEL_LIMIT_I9XX_LVDS */
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.dot = {.min = 20000, .max = 400000},
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@ -83,23 +57,24 @@ static const struct psb_intel_limit_t psb_intel_limits[] = {
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/* The single-channel range is 25-112Mhz, and dual-channel
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* is 80-224Mhz. Prefer single channel as much as possible.
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*/
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.p2 = {.dot_limit = 112000,
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.p2_slow = 14, .p2_fast = 7},
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.p2 = {.dot_limit = 112000, .p2_slow = 14, .p2_fast = 7},
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.find_pll = gma_find_best_pll,
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},
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};
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static const struct psb_intel_limit_t *psb_intel_limit(struct drm_crtc *crtc)
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static const struct gma_limit_t *psb_intel_limit(struct drm_crtc *crtc,
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int refclk)
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{
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const struct psb_intel_limit_t *limit;
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const struct gma_limit_t *limit;
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if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
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if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
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limit = &psb_intel_limits[INTEL_LIMIT_I9XX_LVDS];
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else
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limit = &psb_intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
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return limit;
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}
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static void psb_intel_clock(int refclk, struct psb_intel_clock_t *clock)
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static void psb_intel_clock(int refclk, struct gma_clock_t *clock)
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{
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clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
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clock->p = clock->p1 * clock->p2;
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@ -107,130 +82,6 @@ static void psb_intel_clock(int refclk, struct psb_intel_clock_t *clock)
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clock->dot = clock->vco / clock->p;
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}
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/**
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* Returns whether any output on the specified pipe is of the specified type
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*/
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bool psb_intel_pipe_has_type(struct drm_crtc *crtc, int type)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_mode_config *mode_config = &dev->mode_config;
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struct drm_connector *l_entry;
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list_for_each_entry(l_entry, &mode_config->connector_list, head) {
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if (l_entry->encoder && l_entry->encoder->crtc == crtc) {
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struct psb_intel_encoder *psb_intel_encoder =
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psb_intel_attached_encoder(l_entry);
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if (psb_intel_encoder->type == type)
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return true;
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}
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}
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return false;
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}
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#define INTELPllInvalid(s) { /* ErrorF (s) */; return false; }
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/**
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* Returns whether the given set of divisors are valid for a given refclk with
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* the given connectors.
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*/
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static bool psb_intel_PLL_is_valid(struct drm_crtc *crtc,
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struct psb_intel_clock_t *clock)
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{
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const struct psb_intel_limit_t *limit = psb_intel_limit(crtc);
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if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
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INTELPllInvalid("p1 out of range\n");
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if (clock->p < limit->p.min || limit->p.max < clock->p)
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INTELPllInvalid("p out of range\n");
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if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
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INTELPllInvalid("m2 out of range\n");
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if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
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INTELPllInvalid("m1 out of range\n");
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if (clock->m1 <= clock->m2)
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INTELPllInvalid("m1 <= m2\n");
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if (clock->m < limit->m.min || limit->m.max < clock->m)
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INTELPllInvalid("m out of range\n");
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if (clock->n < limit->n.min || limit->n.max < clock->n)
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INTELPllInvalid("n out of range\n");
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if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
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INTELPllInvalid("vco out of range\n");
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/* XXX: We may need to be checking "Dot clock"
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* depending on the multiplier, connector, etc.,
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* rather than just a single range.
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*/
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if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
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INTELPllInvalid("dot out of range\n");
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return true;
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}
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/**
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* Returns a set of divisors for the desired target clock with the given
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* refclk, or FALSE. The returned values represent the clock equation:
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* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
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*/
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static bool psb_intel_find_best_PLL(struct drm_crtc *crtc, int target,
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int refclk,
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struct psb_intel_clock_t *best_clock)
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{
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struct drm_device *dev = crtc->dev;
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struct psb_intel_clock_t clock;
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const struct psb_intel_limit_t *limit = psb_intel_limit(crtc);
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int err = target;
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if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
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(REG_READ(LVDS) & LVDS_PORT_EN) != 0) {
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/*
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* For LVDS, if the panel is on, just rely on its current
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* settings for dual-channel. We haven't figured out how to
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* reliably set up different single/dual channel state, if we
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* even can.
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*/
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if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
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LVDS_CLKB_POWER_UP)
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clock.p2 = limit->p2.p2_fast;
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else
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clock.p2 = limit->p2.p2_slow;
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} else {
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if (target < limit->p2.dot_limit)
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clock.p2 = limit->p2.p2_slow;
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else
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clock.p2 = limit->p2.p2_fast;
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}
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memset(best_clock, 0, sizeof(*best_clock));
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for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
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clock.m1++) {
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for (clock.m2 = limit->m2.min;
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clock.m2 < clock.m1 && clock.m2 <= limit->m2.max;
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clock.m2++) {
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for (clock.n = limit->n.min;
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clock.n <= limit->n.max; clock.n++) {
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for (clock.p1 = limit->p1.min;
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clock.p1 <= limit->p1.max;
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clock.p1++) {
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int this_err;
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psb_intel_clock(refclk, &clock);
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if (!psb_intel_PLL_is_valid
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(crtc, &clock))
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continue;
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this_err = abs(clock.dot - target);
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if (this_err < err) {
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*best_clock = clock;
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err = this_err;
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}
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}
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}
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}
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}
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return err != target;
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}
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void psb_intel_wait_for_vblank(struct drm_device *dev)
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{
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/* Wait for 20ms, i.e. one cycle at 50hz. */
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@ -484,12 +335,13 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
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int pipe = psb_intel_crtc->pipe;
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const struct psb_offset *map = &dev_priv->regmap[pipe];
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int refclk;
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struct psb_intel_clock_t clock;
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struct gma_clock_t clock;
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u32 dpll = 0, fp = 0, dspcntr, pipeconf;
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bool ok, is_sdvo = false;
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bool is_lvds = false, is_tv = false;
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struct drm_mode_config *mode_config = &dev->mode_config;
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struct drm_connector *connector;
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const struct gma_limit_t *limit;
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/* No scan out no play */
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if (crtc->fb == NULL) {
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@ -520,10 +372,13 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
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refclk = 96000;
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ok = psb_intel_find_best_PLL(crtc, adjusted_mode->clock, refclk,
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limit = psb_intel_crtc->clock_funcs->limit(crtc, refclk);
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ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
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&clock);
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if (!ok) {
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dev_err(dev->dev, "Couldn't find PLL settings for mode!\n");
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DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d",
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adjusted_mode->clock, clock.dot);
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return 0;
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}
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@ -1022,7 +877,7 @@ static int psb_intel_crtc_clock_get(struct drm_device *dev,
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const struct psb_offset *map = &dev_priv->regmap[pipe];
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u32 dpll;
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u32 fp;
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struct psb_intel_clock_t clock;
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struct gma_clock_t clock;
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bool is_lvds;
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struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
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@ -1190,6 +1045,12 @@ const struct drm_crtc_funcs psb_intel_crtc_funcs = {
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.destroy = psb_intel_crtc_destroy,
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};
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const struct gma_clock_funcs psb_clock_funcs = {
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.clock = psb_intel_clock,
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.limit = psb_intel_limit,
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.pll_is_valid = gma_pll_is_valid,
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};
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/*
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* Set the default value of cursor control and base register
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* to zero. This is a workaround for h/w defect on Oaktrail
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@ -20,6 +20,4 @@
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#ifndef _INTEL_DISPLAY_H_
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#define _INTEL_DISPLAY_H_
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bool psb_intel_pipe_has_type(struct drm_crtc *crtc, int type);
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#endif
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