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https://github.com/FEX-Emu/linux.git
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Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm
Pull ARM fixes from Russell King: "Some small fixes for this merge window, most of them quite self explanatory - the biggest thing here is a fix for the ARMv7 LPAE suspend/resume support" * 'fixes' of git://git.linaro.org/people/rmk/linux-arm: ARM: 7894/1: kconfig: select GENERIC_CLOCKEVENTS if HAVE_ARM_ARCH_TIMER ARM: 7893/1: bitops: only emit .arch_extension mp if CONFIG_SMP ARM: 7892/1: Fix warning for V7M builds ARM: 7888/1: seccomp: not compatible with ARM OABI ARM: 7886/1: make OABI default to off ARM: 7885/1: Save/Restore 64-bit TTBR registers on LPAE suspend/resume ARM: 7884/1: mm: Fix ECC mem policy printk ARM: 7883/1: fix mov to mvn conversion in case of 64 bit phys_addr_t and BE ARM: 7882/1: mm: fix __phys_to_virt to work with 64 bit phys_addr_t in BE case ARM: 7881/1: __fixup_smp read of SCU config should do byteswap in BE case ARM: Fix nommu.c build warning
This commit is contained in:
Linus Torvalds
commit
7fa850ab4f
@ -25,7 +25,7 @@ config ARM
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select HARDIRQS_SW_RESEND
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select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
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select HAVE_ARCH_KGDB
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select HAVE_ARCH_SECCOMP_FILTER
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select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
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select HAVE_ARCH_TRACEHOOK
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select HAVE_BPF_JIT
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select HAVE_CONTEXT_TRACKING
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@ -1496,6 +1496,7 @@ config HAVE_ARM_ARCH_TIMER
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bool "Architected timer support"
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depends on CPU_V7
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select ARM_ARCH_TIMER
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select GENERIC_CLOCKEVENTS
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help
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This option enables support for the ARM architected timer
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@ -1719,7 +1720,6 @@ config AEABI
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config OABI_COMPAT
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bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
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depends on AEABI && !THUMB2_KERNEL
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default y
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help
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This option preserves the old syscall interface along with the
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new (ARM EABI) one. It also provides a compatibility layer to
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@ -1727,11 +1727,16 @@ config OABI_COMPAT
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in memory differs between the legacy ABI and the new ARM EABI
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(only for non "thumb" binaries). This option adds a tiny
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overhead to all syscalls and produces a slightly larger kernel.
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The seccomp filter system will not be available when this is
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selected, since there is no way yet to sensibly distinguish
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between calling conventions during filtering.
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If you know you'll be using only pure EABI user space then you
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can say N here. If this option is not selected and you attempt
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to execute a legacy ABI binary then the result will be
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UNPREDICTABLE (in fact it can be predicted that it won't work
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at all). If in doubt say Y.
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at all). If in doubt say N.
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config ARCH_HAS_HOLES_MEMORYMODEL
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bool
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@ -226,7 +226,14 @@ static inline phys_addr_t __virt_to_phys(unsigned long x)
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static inline unsigned long __phys_to_virt(phys_addr_t x)
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{
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unsigned long t;
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__pv_stub(x, t, "sub", __PV_BITS_31_24);
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/*
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* 'unsigned long' cast discard upper word when
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* phys_addr_t is 64 bit, and makes sure that inline
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* assembler expression receives 32 bit argument
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* in place where 'r' 32 bit operand is expected.
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*/
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__pv_stub((unsigned long) x, t, "sub", __PV_BITS_31_24);
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return t;
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}
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@ -508,6 +508,7 @@ __fixup_smp:
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teq r0, #0x0 @ '0' on actual UP A9 hardware
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beq __fixup_smp_on_up @ So its an A9 UP
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ldr r0, [r0, #4] @ read SCU Config
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ARM_BE8(rev r0, r0) @ byteswap if big endian
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and r0, r0, #0x3 @ number of CPUs
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teq r0, #0x0 @ is 1?
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movne pc, lr
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@ -643,8 +644,12 @@ ARM_BE8(rev16 ip, ip)
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ldrcc r7, [r4], #4 @ use branch for delay slot
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bcc 1b
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bx lr
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#else
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#ifdef CONFIG_CPU_ENDIAN_BE8
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moveq r0, #0x00004000 @ set bit 22, mov to mvn instruction
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#else
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moveq r0, #0x400000 @ set bit 22, mov to mvn instruction
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#endif
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b 2f
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1: ldr ip, [r7, r3]
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#ifdef CONFIG_CPU_ENDIAN_BE8
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@ -653,7 +658,7 @@ ARM_BE8(rev16 ip, ip)
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tst ip, #0x000f0000 @ check the rotation field
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orrne ip, ip, r6, lsl #24 @ mask in offset bits 31-24
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biceq ip, ip, #0x00004000 @ clear bit 22
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orreq ip, ip, r0, lsl #24 @ mask in offset bits 7-0
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orreq ip, ip, r0 @ mask in offset bits 7-0
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#else
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bic ip, ip, #0x000000ff
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tst ip, #0xf00 @ check the rotation field
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@ -856,7 +856,7 @@ static void __init kuser_init(void *vectors)
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memcpy(vectors + 0xfe0, vectors + 0xfe8, 4);
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}
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#else
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static void __init kuser_init(void *vectors)
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static inline void __init kuser_init(void *vectors)
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{
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}
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#endif
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@ -10,7 +10,7 @@ UNWIND( .fnstart )
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and r3, r0, #31 @ Get bit offset
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mov r0, r0, lsr #5
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add r1, r1, r0, lsl #2 @ Get word offset
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#if __LINUX_ARM_ARCH__ >= 7
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#if __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)
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.arch_extension mp
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ALT_SMP(W(pldw) [r1])
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ALT_UP(W(nop))
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@ -558,8 +558,8 @@ static void __init build_mem_type_table(void)
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mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
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break;
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}
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printk("Memory policy: ECC %sabled, Data cache %s\n",
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ecc_mask ? "en" : "dis", cp->policy);
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pr_info("Memory policy: %sData cache %s\n",
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ecc_mask ? "ECC enabled, " : "", cp->policy);
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for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
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struct mem_type *t = &mem_types[i];
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@ -18,6 +18,7 @@
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#include <asm/mach/arch.h>
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#include <asm/cputype.h>
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#include <asm/mpu.h>
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#include <asm/procinfo.h>
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#include "mm.h"
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@ -92,7 +92,7 @@ ENDPROC(cpu_v7_dcache_clean_area)
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/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
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.globl cpu_v7_suspend_size
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.equ cpu_v7_suspend_size, 4 * 8
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.equ cpu_v7_suspend_size, 4 * 9
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#ifdef CONFIG_ARM_CPU_SUSPEND
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ENTRY(cpu_v7_do_suspend)
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stmfd sp!, {r4 - r10, lr}
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@ -101,13 +101,17 @@ ENTRY(cpu_v7_do_suspend)
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stmia r0!, {r4 - r5}
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#ifdef CONFIG_MMU
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mrc p15, 0, r6, c3, c0, 0 @ Domain ID
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#ifdef CONFIG_ARM_LPAE
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mrrc p15, 1, r5, r7, c2 @ TTB 1
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#else
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mrc p15, 0, r7, c2, c0, 1 @ TTB 1
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#endif
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mrc p15, 0, r11, c2, c0, 2 @ TTB control register
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#endif
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mrc p15, 0, r8, c1, c0, 0 @ Control register
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mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
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mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
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stmia r0, {r6 - r11}
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stmia r0, {r5 - r11}
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ldmfd sp!, {r4 - r10, pc}
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ENDPROC(cpu_v7_do_suspend)
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@ -118,16 +122,19 @@ ENTRY(cpu_v7_do_resume)
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ldmia r0!, {r4 - r5}
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mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
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mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
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ldmia r0, {r6 - r11}
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ldmia r0, {r5 - r11}
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#ifdef CONFIG_MMU
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mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
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mcr p15, 0, r6, c3, c0, 0 @ Domain ID
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#ifndef CONFIG_ARM_LPAE
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#ifdef CONFIG_ARM_LPAE
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mcrr p15, 0, r1, ip, c2 @ TTB 0
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mcrr p15, 1, r5, r7, c2 @ TTB 1
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#else
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ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
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ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
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#endif
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mcr p15, 0, r1, c2, c0, 0 @ TTB 0
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mcr p15, 0, r7, c2, c0, 1 @ TTB 1
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#endif
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mcr p15, 0, r11, c2, c0, 2 @ TTB control register
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ldr r4, =PRRR @ PRRR
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ldr r5, =NMRR @ NMRR
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