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x86, pci: move arch/x86/pci/pci.h to arch/x86/include/asm/pci_x86.h

Browse Source 
Impact: cleanup

Now that arch/x86/pci/pci.h is used in a number of other places as well,
move the lowlevel x86 pci definitions into the architecture include files.
(not to be confused with the existing arch/x86/include/asm/pci.h file,
which provides public details about x86 PCI)

Tested on: X86_32_UP, X86_32_SMP and X86_64_SMP

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Jaswinder Singh Rajput 2008-12-27 18:32:28 +05:30 committed by Ingo Molnar
parent c854c91979
commit 824877111c
23 changed files with 33 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
arch/x86/pci/pci.h → arch/x86/include/asm/pci_x86.h
View File

@ -57,7 +57,8 @@ extern struct pci_ops pci_root_ops;
struct irq_info {
u8 bus, devfn; /* Bus, device and function */
struct {
u8 link; /* IRQ line ID, chipset dependent, 0=not routed */
u8 link; /* IRQ line ID, chipset dependent,
0 = not routed */
u16 bitmap; /* Available IRQs */
} __attribute__((packed)) irq[4];
u8 slot; /* Slot number, 0=onboard */
@ -69,11 +70,13 @@ struct irq_routing_table {
u16 version; /* PIRQ_VERSION */
u16 size; /* Table size in bytes */
u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */
u16 exclusive_irqs; /* IRQs devoted exclusively to PCI usage */
u16 rtr_vendor, rtr_device; /* Vendor and device ID of interrupt router */
u16 exclusive_irqs; /* IRQs devoted exclusively to
PCI usage */
u16 rtr_vendor, rtr_device; /* Vendor and device ID of
interrupt router */
u32 miniport_data; /* Crap */
u8 rfu[11];
u8 checksum; /* Modulo 256 checksum must give zero */
u8 checksum; /* Modulo 256 checksum must give 0 */
struct irq_info slots[0];
} __attribute__((packed));
@ -148,15 +151,15 @@ static inline unsigned int mmio_config_readl(void __iomem *pos)
static inline void mmio_config_writeb(void __iomem *pos, u8 val)
{
asm volatile("movb %%al,(%1)" :: "a" (val), "r" (pos) : "memory");
asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory");
}
static inline void mmio_config_writew(void __iomem *pos, u16 val)
{
asm volatile("movw %%ax,(%1)" :: "a" (val), "r" (pos) : "memory");
asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory");
}
static inline void mmio_config_writel(void __iomem *pos, u32 val)
{
asm volatile("movl %%eax,(%1)" :: "a" (val), "r" (pos) : "memory");
asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory");
}

3
arch/x86/kernel/mmconf-fam10h_64.c
View File

@ -13,8 +13,7 @@
#include <asm/msr.h>
#include <asm/acpi.h>
#include <asm/mmconfig.h>
#include "../pci/pci.h"
#include <asm/pci_x86.h>
struct pci_hostbridge_probe {
u32 bus;

3
arch/x86/kernel/reboot.c
View File

@ -12,6 +12,7 @@
#include <asm/proto.h>
#include <asm/reboot_fixups.h>
#include <asm/reboot.h>
#include <asm/pci_x86.h>
#ifdef CONFIG_X86_32
# include <linux/dmi.h>
@ -22,8 +23,6 @@
#endif
#include <mach_ipi.h>
#include "../pci/pci.h"
/*
* Power off function, if any

2
arch/x86/pci/acpi.c
View File

@ -4,7 +4,7 @@
#include <linux/irq.h>
#include <linux/dmi.h>
#include <asm/numa.h>
#include "pci.h"
#include <asm/pci_x86.h>
struct pci_root_info {
char *name;

2
arch/x86/pci/amd_bus.c
View File

@ -2,7 +2,7 @@
#include <linux/pci.h>
#include <linux/topology.h>
#include <linux/cpu.h>
#include "pci.h"
#include <asm/pci_x86.h>
#ifdef CONFIG_X86_64
#include <asm/pci-direct.h>

3
arch/x86/pci/common.c
View File

@ -14,8 +14,7 @@
#include <asm/segment.h>
#include <asm/io.h>
#include <asm/smp.h>
#include "pci.h"
#include <asm/pci_x86.h>
unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1 | PCI_PROBE_CONF2 |
PCI_PROBE_MMCONF;

2
arch/x86/pci/direct.c
View File

@ -5,7 +5,7 @@
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/dmi.h>
#include "pci.h"
#include <asm/pci_x86.h>
/*
* Functions for accessing PCI base (first 256 bytes) and extended

2
arch/x86/pci/early.c
View File

@ -2,7 +2,7 @@
#include <linux/pci.h>
#include <asm/pci-direct.h>
#include <asm/io.h>
#include "pci.h"
#include <asm/pci_x86.h>
/* Direct PCI access. This is used for PCI accesses in early boot before
the PCI subsystem works. */

3
arch/x86/pci/fixup.c
View File

@ -6,8 +6,7 @@
#include <linux/dmi.h>
#include <linux/pci.h>
#include <linux/init.h>
#include "pci.h"
#include <asm/pci_x86.h>
static void __devinit pci_fixup_i450nx(struct pci_dev *d)
{

2
arch/x86/pci/i386.c
View File

@ -34,8 +34,8 @@
#include <asm/pat.h>
#include <asm/e820.h>
#include <asm/pci_x86.h>
#include "pci.h"
static int
skip_isa_ioresource_align(struct pci_dev *dev) {

2
arch/x86/pci/init.c
View File

@ -1,6 +1,6 @@
#include <linux/pci.h>
#include <linux/init.h>
#include "pci.h"
#include <asm/pci_x86.h>
/* arch_initcall has too random ordering, so call the initializers
in the right sequence from here. */

3
arch/x86/pci/irq.c
View File

@ -16,8 +16,7 @@
#include <asm/io_apic.h>
#include <linux/irq.h>
#include <linux/acpi.h>
#include "pci.h"
#include <asm/pci_x86.h>
#define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
#define PIRQ_VERSION 0x0100

2
arch/x86/pci/legacy.c
View File

@ -3,7 +3,7 @@
*/
#include <linux/init.h>
#include <linux/pci.h>
#include "pci.h"
#include <asm/pci_x86.h>
/*
* Discover remaining PCI buses in case there are peer host bridges.

3
arch/x86/pci/mmconfig-shared.c
View File

@ -15,8 +15,7 @@
#include <linux/acpi.h>
#include <linux/bitmap.h>
#include <asm/e820.h>
#include "pci.h"
#include <asm/pci_x86.h>
/* aperture is up to 256MB but BIOS may reserve less */
#define MMCONFIG_APER_MIN (2 * 1024*1024)

2
arch/x86/pci/mmconfig_32.c
View File

@ -13,7 +13,7 @@
#include <linux/init.h>
#include <linux/acpi.h>
#include <asm/e820.h>
#include "pci.h"
#include <asm/pci_x86.h>
/* Assume systems with more busses have correct MCFG */
#define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG))

3
arch/x86/pci/mmconfig_64.c
View File

@ -10,8 +10,7 @@
#include <linux/acpi.h>
#include <linux/bitmap.h>
#include <asm/e820.h>
#include "pci.h"
#include <asm/pci_x86.h>
/* Static virtual mapping of the MMCONFIG aperture */
struct mmcfg_virt {

2
arch/x86/pci/numaq_32.c
View File

@ -7,7 +7,7 @@
#include <linux/nodemask.h>
#include <mach_apic.h>
#include <asm/mpspec.h>
#include "pci.h"
#include <asm/pci_x86.h>
#define XQUAD_PORTIO_BASE 0xfe400000
#define XQUAD_PORTIO_QUAD 0x40000 /* 256k per quad. */

2
arch/x86/pci/olpc.c
View File

@ -29,7 +29,7 @@
#include <linux/init.h>
#include <asm/olpc.h>
#include <asm/geode.h>
#include "pci.h"
#include <asm/pci_x86.h>
/*
* In the tables below, the first two line (8 longwords) are the

5
arch/x86/pci/pcbios.c
View File

@ -6,9 +6,8 @@
#include <linux/init.h>
#include <linux/module.h>
#include <linux/uaccess.h>
#include "pci.h"
#include "pci-functions.h"
#include <asm/pci_x86.h>
#include <asm/mach-default/pci-functions.h>
/* BIOS32 signature: "_32_" */
#define BIOS32_SIGNATURE (('_' << 0) + ('3' << 8) + ('2' << 16) + ('_' << 24))

3
arch/x86/pci/visws.c
View File

@ -9,11 +9,10 @@
#include <linux/init.h>
#include <asm/setup.h>
#include <asm/pci_x86.h>
#include <asm/visws/cobalt.h>
#include <asm/visws/lithium.h>
#include "pci.h"
static int pci_visws_enable_irq(struct pci_dev *dev) { return 0; }
static void pci_visws_disable_irq(struct pci_dev *dev) { }

2
drivers/pci/hotplug/cpqphp_core.c
View File

@ -45,7 +45,7 @@
#include "cpqphp.h"
#include "cpqphp_nvram.h"
#include "../../../arch/x86/pci/pci.h" /* horrible hack showing how processor dependent we are... */
#include <asm/pci_x86.h>
/* Global variables */

2
drivers/pci/hotplug/cpqphp_pci.c
View File

@ -37,7 +37,7 @@
#include "../pci.h"
#include "cpqphp.h"
#include "cpqphp_nvram.h"
#include "../../../arch/x86/pci/pci.h" /* horrible hack showing how processor dependent we are... */
#include <asm/pci_x86.h>
u8 cpqhp_nic_irq;

2
drivers/pci/hotplug/ibmphp_core.c
View File

@ -35,7 +35,7 @@
#include <linux/delay.h>
#include <linux/wait.h>
#include "../pci.h"
#include "../../../arch/x86/pci/pci.h" /* for struct irq_routing_table */
#include <asm/pci_x86.h> /* for struct irq_routing_table */
#include "ibmphp.h"
#define attn_on(sl) ibmphp_hpc_writeslot (sl, HPC_SLOT_ATTNON)