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ARM: dts: bcm: Add missing UARTs for bcm11351 (bcm281xx)

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This adds in three more UARTs that were not declared earlier.

Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Reviewed-by: Matt Porter <matt.porter@linaro.org>
Signed-off-by: Christian Daudt <bcm@fixthebug.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Tim Kryger 2013-09-23 10:49:57 -07:00 committed by Olof Johansson
parent 71469fe801
commit 84491c0fc5
1 changed files with 30 additions and 0 deletions
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30
arch/arm/boot/dts/bcm11351.dtsi
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@ -49,6 +49,36 @@
reg-io-width = <4>;
};
uart@3e001000 {
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
status = "disabled";
reg = <0x3e001000 0x1000>;
clock-frequency = <13000000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
};
uart@3e002000 {
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
status = "disabled";
reg = <0x3e002000 0x1000>;
clock-frequency = <13000000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
};
uart@3e003000 {
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
status = "disabled";
reg = <0x3e003000 0x1000>;
clock-frequency = <13000000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
};
L2: l2-cache {
compatible = "brcm,bcm11351-a2-pl310-cache";
reg = <0x3ff20000 0x1000>;